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Interrupt Controller Modules
Field
15–9
Enable core's priority elevation on priority levels. Each ELVLPRI[7:1] bit corresponds to the available priority
ELVLPRI
levels 1 – 7. If set, the assertion of the corresponding level-n request to the core causes the processor's bus
master priority to be temporarily elevated in the device's crossbar switch arbitration logic. The processor's bus
master arbitration priority remains elevated until the level-n request is negated. If round-robin arbitration is
enabled, this bit has no effect.
If cleared, the assertion of a level-n request does not affect the processor's bus master priority.
8–6
Reserved, must be cleared.
5
If set, the interrupt controller automatically loads the level of an interrupt request into the CLMASK (current level
EMASK
mask) when the acknowledge is performed. At the exact same cycle, the value of the current interrupt level mask is
saved in the SLMASK (saved level mask) register.
This feature can be used to support software-managed nested interrupts, and is intended to complement the
interrupt masking functions supported in the ColdFire processor. The value of SLMASK register should be read from
the interrupt controller and saved in the interrupt stack frame in memory, and restored near the service routine's exit.
If cleared, the INTC does not perform any automatic masking of interrupt levels. The state of this bit does not affect
the ColdFire processor's interrupt masking logic in any manner.
4–0
Reserved, must be cleared.
17.2.5
Set Interrupt Mask Register (SIMRn)
The SIMRn register provides a simple mechanism to set a given bit in the IMRn registers to mask the
corresponding interrupt request. The value written to the SIMR field causes the corresponding bit in the
IMRn register to be set. The SIMRn[SALL] bit provides a global set function, forcing the entire contents
of IMRn to be set, thus masking all interrupts. Reads of this register return all zeroes. This register is
provided so interrupt service routines can easily mask the given interrupt request without the need to
perform a read-modify-write sequence on the IMRn register.
Address: 0xFC04_801C (SIMR0)
0xFC04_C01C (SIMR1)
7
R
0
W
Reset:
0
Field
7
Reserved, must be cleared.
6
Set all bits in the IMRn register, masking all interrupt requests.
SALL
0 Only set those bits specified in the SIMR field.
1 Set all bits in IMRn register. The SIMR field is ignored.
5–0
Set the corresponding bit in the IMRn register, masking the interrupt request.
SIMR
17-8
Table 17-9. ICONFIG Field Descriptions
6
5
4
0
0
0
SALL
0
0
0
Figure 17-8. Set Interrupt Mask Register (SIMRn)
Table 17-10. SIMRn Field Descriptions
Description
3
2
0
0
SIMR
0
0
Description
Access: User write-only
1
0
0
0
0
0
Freescale Semiconductor
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