Download Print this page

Freescale Semiconductor MCF5329 Reference Manual

Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329

Table Of Contents

page of 924

/ 924
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

MCF5329 Reference Manual

Devices Supported:

MCF5327

MCF5328

MCF53281

MCF5329

Document Number: MCF5329RM

Rev. 3

12/2008

Table of Contents

Advertisement

Table of Contents

Need help?

Need help?

Do you have a question about the MCF5329 and is the answer not in the manual?

Questions and answers

Summary of Contents for Freescale Semiconductor MCF5329

Page 1 MCF5329 Reference Manual Devices Supported: MCF5327 MCF5328 MCF53281 MCF5329 Document Number: MCF5329RM Rev. 3 12/2008...
Page 2 Freescale Semiconductor product could Asia/Pacific: create a situation where personal injury or death may occur. Should Buyer Freescale Semiconductor Hong Kong Ltd.
Page 3 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) Crossbar Switch (XBS) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) Enhanced Direct Memory Access (eDMA) FlexBus SDRAM Controller (SDRAMC)
Page 4 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) Crossbar Switch (XBS) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) Enhanced Direct Memory Access (eDMA) FlexBus SDRAM Controller (SDRAMC)
Page 5: Table Of Contents
UARTs ........................... 1-13 1.3.14 C Bus........................... 1-13 1.3.15 QSPI..........................1-13 1.3.16 Pulse Width Modulation (PWM) Timer ................ 1-13 1.3.17 Real Time Clock ......................1-13 1.3.18 DMA Timers (DTIM0-DTIM3) ..................1-13 1.3.19 Software Watchdog Timer..................... 1-14 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 6: Paragraph Number
2.3.16 UART Module Signals ....................2-17 2.3.17 DMA Timer Signals....................... 2-17 2.3.18 Debug Support Signals ....................2-17 2.3.19 Test Signals........................2-19 2.3.20 Power and Ground Pins ....................2-19 External Boot Mode ........................2-20 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 7 Functional Description ........................4-8 4.3.1 Fractional Operation Mode .................... 4-10 4.3.2 EMAC Instruction Set Summary ................... 4-12 4.3.3 EMAC Instruction Execution Times ................4-13 4.3.4 Data Representation ....................... 4-14 4.3.5 MAC Opcodes ....................... 4-14 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 8 SRAM Initialization Code ....................6-4 6.3.2 Power Management ......................6-5 Chapter 7 Clock Module Introduction ............................ 7-1 7.1.1 Block Diagram ......................... 7-3 7.1.2 Features ..........................7-3 7.1.3 Modes of Operation ......................7-3 Memory Map/Register Definition....................7-5 MCF5329 Reference Manual, Rev 3 viii Freescale Semiconductor...
Page 9 Block Diagram ......................... 9-1 9.1.2 Features ..........................9-1 9.1.3 Modes of Operation ......................9-1 External Signal Descriptions......................9-2 9.2.1 RCON ..........................9-2 9.2.2 D[9:86:1] (Reset Configuration Override) ..............9-2 Memory Map/Register Definition....................9-2 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 10 Concurrent Resets ......................10-7 Chapter 11 System Control Module (SCM) 11.1 Introduction ..........................11-1 11.1.1 Overview........................11-1 11.1.2 Features .......................... 11-1 11.2 Memory Map/Register Definition....................11-2 11.2.1 Master Privilege Register 0 (MPR0) ................11-3 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 11 13.1.2 Features .......................... 13-3 13.2 External Signal Description ......................13-3 13.3 Memory Map/Register Definition....................13-11 13.3.1 Port Output Data Registers (PODR_ ) ................ 13-14 13.3.2 Port Data Direction Registers (PDDR_ ) ..............13-17 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 12 Low-Power Wake-up Operation .................. 14-18 14.4 Initialization/Application Information ..................14-19 14.4.1 Interrupt Service Routines ................... 14-19 Chapter 15 Edge Port Module (EPORT) 15.1 Introduction ..........................15-1 15.2 Low-Power Mode Operation......................15-2 15.3 Interrupt/GPIO Pin Descriptions....................15-2 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 13 16.6.15 eDMA Channel n Priority Registers (DCHPRIn)............16-16 16.6.16 Transfer Control Descriptors (TCD ) ................. 16-17 16.7 Functional Description ....................... 16-24 16.7.1 eDMA Microarchitecture..................... 16-24 16.7.2 eDMA Basic Data Flow....................16-25 16.8 Initialization/Application Information ..................16-28 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xiii...
Page 14 Bus Cycle Execution....................17-12 17.4.5 FlexBus Timing Examples................... 17-13 17.4.6 Burst Cycles ......................... 17-24 17.4.7 Misaligned Operands ....................17-30 17.4.8 Bus Errors ........................17-30 Chapter 18 SDRAM Controller (SDRAMC) 18.1 Introduction ..........................18-1 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 15 19.4 Memory Map/Register Definition....................19-6 19.4.1 MIB Block Counters Memory Map................19-7 19.4.2 Ethernet Interrupt Event Register (EIR) ................ 19-9 19.4.3 Interrupt Mask Register (EIMR).................. 19-11 19.4.4 Receive Descriptor Active Register (RDAR) .............. 19-11 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 16 19.5.12 Inter-Packet Gap (IPG) Time..................19-41 19.5.13 Collision Managing...................... 19-41 19.5.14 MII Internal and External Loopback ................19-41 19.5.15 Ethernet Error-Managing Procedure................19-41 Chapter 20 Universal Serial Bus Interface – Host Module 20.1 Introduction ..........................20-1 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 17 Device Operation ......................21-54 21.5.4 Servicing Interrupts...................... 21-72 21.5.5 Deviations from the EHCI Specifications ..............21-73 Chapter 22 Liquid Crystal Display Controller (LCDC) 22.1 Introduction ..........................22-1 22.1.1 Block Diagram ....................... 22-1 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xvii...
Page 18 22.4.6 Gray-Scale Operation ....................22-33 22.4.7 Color Generation......................22-34 22.4.8 Frame Rate Modulation Control (FRC)............... 22-36 22.4.9 Panel Interface Signals and Timing ................22-37 22.4.10 8 bpp Mode Color STN Panel..................22-40 MCF5329 Reference Manual, Rev 3 xviii Freescale Semiconductor...
Page 19 Overview........................24-2 24.1.2 Features .......................... 24-3 24.1.3 Modes of Operation ....................... 24-3 24.2 External Signal Description ......................24-5 24.2.1 SSI_CLKIN — SSI Clock Input..................24-5 24.2.2 SSI_BCLK — Serial Bit Clock ..................24-5 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 20 Transmit Interrupt Enable Bit Description ..............24-48 24.5 Initialization/Application Information ..................24-49 Chapter 25 Real-Time Clock 25.1 Introduction ..........................25-1 25.1.1 Overview........................25-1 25.1.2 Features .......................... 25-2 25.1.3 Modes of Operation ....................... 25-2 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 21 PWM Channel Counter Registers (PWMCNT ) ............26-9 26.2.10 PWM Channel Period Registers (PWMPER )............26-10 26.2.11 PWM Channel Duty Registers (PWMDTYn) ............. 26-10 26.2.12 PWM Shutdown Register (PWMSDN) ............... 26-11 26.3 Functional Description ....................... 26-12 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 22 Interrupt Operation ......................28-7 Chapter 29 DMA Timers (DTIM0–DTIM3) 29.1 Introduction ..........................29-1 29.1.1 Overview........................29-1 29.1.2 Features .......................... 29-2 29.2 Memory Map/Register Definition....................29-3 29.2.1 DMA Timer Mode Registers (DTMR )................ 29-3 MCF5329 Reference Manual, Rev 3 xxii Freescale Semiconductor...
Page 23 30.4 Functional Description ......................... 30-9 30.4.1 QSPI RAM........................30-11 30.4.2 Baud Rate Selection..................... 30-12 30.4.3 Transfer Delays......................30-13 30.4.4 Transfer Length......................30-14 30.4.5 Data Transfer ....................... 30-14 30.5 Initialization/Application Information ..................30-15 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xxiii...
Page 24 Chapter 32 C Interface 32.1 Introduction ..........................32-1 32.1.1 Block Diagram ....................... 32-1 32.1.2 Overview........................32-2 32.1.3 Features .......................... 32-2 32.2 Memory Map/Register Definition....................32-3 32.2.1 C Address Register (I2ADR) ..................32-3 MCF5329 Reference Manual, Rev 3 xxiv Freescale Semiconductor...
Page 25 MDHA Data Size Register (MDDSR)................. 33-11 33.2.7 MDHA Input FIFO (MDIN)..................33-11 33.2.8 MDHA Message Digest Registers 0 (MDx0).............. 33-11 33.2.9 MDHA Message Data Size Register (MDMDS)............33-12 33.2.10 MDHA Message Digest Registers 1 (MDx1).............. 33-12 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 26 35.2.4 SKHA Status Register (SKSR)..................35-9 35.2.5 SKHA Error Status and Mask Registers (SKESR, SKESMR)........35-10 35.2.6 SKHA Key Size Register (SKKSR) ................35-12 35.2.7 SKHA Data Size Register (SKDSR) ................35-12 MCF5329 Reference Manual, Rev 3 xxvi Freescale Semiconductor...
Page 27 Concurrent BDM and Processor Operation ..............36-40 36.4.4 Real-Time Trace Support..................... 36-40 36.4.5 Debug Translate Block ....................36-43 36.4.6 Processor Status, Debug Data Definition ..............36-44 36.4.7 Freescale-Recommended BDM Pinout ............... 36-49 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xxvii...
Page 28 Changes Between Rev. 2 and Rev. 3 ................B-1 Changes Between Rev. 1 and Rev. 2 ................B-5 Changes Between Rev. 0.1 and Rev. 1 ................B-12 Changes Between Rev. 0 and Rev. 0.1 ................B-17 MCF5329 Reference Manual, Rev 3 xxviii Freescale Semiconductor...
Page 29: About This Book
About This Book The primary objective of this reference manual is to define the functionality of the MCF5329 processor for use by software and hardware developers. In addition, this manual supports the MCF5327, MCF5328, and MCF53281. This book is written from the perspective of the MCF5329, and unless otherwise noted, the information applies also to the MCF5327, MCF5328, and MCF53281.
Page 30 SCM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. • Chapter 15, “Edge Port Module (EPORT),” describes EPORT module functionality, including operation in low power mode. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 31 DMA timer modules. These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or triggers. This chapter also provides programming examples. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xxxi...
Page 32: Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. Hardware Specification The MCF5329EC document contains the mechanical and electrical specifications of the MCF52329. It can be found at http://www.freescale.com/coldfire. MCF5329 Reference Manual, Rev 3 xxxii Freescale Semiconductor...
Page 33: General Information
• Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire.
Page 34: Register Figure Conventions
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. MCF5329 Reference Manual, Rev 3 xxxiv...
Page 35: Acronyms And Abbreviations
FIFO First-in, first-out GPIO General-purpose I/O Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers Instruction fetch pipeline Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xxxv...
Page 36: Terminology Conventions
System integration module Start of frame Test access port Transistor transistor logic Transmit UART Universal asynchronous/synchronous receiver transmitter Universal serial bus Terminology Conventions Table 2 shows terminology conventions used throughout this document. MCF5329 Reference Manual, Rev 3 xxxvi Freescale Semiconductor...
Page 37 <xxx> identifies an absolute address referencing memory Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor xxxvii...
Page 38 Calculated effective address (pointer) Bit selection (example: Bit 3 of D0) Least significant bit (example: lsb of D0) Least significant byte Least significant word Most significant bit Most significant byte Most significant word MCF5329 Reference Manual, Rev 3 xxxviii Freescale Semiconductor...
Page 39: Overview
CAN module, and cryptography hardware accelerators. This chapter provides an overview of the MCF5327, MCF5328, MCF53281, and MCF5329 microprocessors. It was written from the perspective of the MCF5329 device. See the following section for a summary of differences between the devices.
Page 40: Block Diagram
MAPBGA Block Diagram The superset device in the MCF532x family is available in a 256 mold array process ball grid array (MAPBGA) package. Figure 1-1 shows a top-level block diagram of the MCF5329. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 41: Features
(4096x32)x2 (To/From XBS) Figure 1-1. MCF5329 Block Diagram Features The following is a brief summary of the functional blocks in the MCF5329 superset device. • Version 3 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data path on-chip —...
Page 42: Overview
Universal serial bus (USB) host controller — Fully compliant with the Universal Serial Bus Specification, Revision 2.0 — Support for full speed (FS = 12 Mbps) and low speed (LS = 1.5 Mbps) with on-chip MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 43 FlexCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard Data and Remote Frames (up to 109 bits long) – Extended Data and Remote Frames (up to 127 bits long) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 44 — Software selection of PWM duty pulse polarity for each channel • Real time clock — Full clock - days, hours, minutes, seconds — Minute countdown timer with interrupt — Programmable daily alarm with interrupt MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 45 — External request pins for up to four channels • FlexBus (external interface) — Glueless connections to 8-, 16-, or 32-bit external memory devices (SRAM, Flash, ROM, etc.) — Support for independent primary and secondary wait states per chip select MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 46: V3 Core Overview
– Status flag indication of source of last reset • General purpose I/O interface — Up to 94 bits of GPIO for the MCF5328, MCF53281, and MCF5329 — Up to 64 bits of GPIO for the MCF5327 — Bit manipulation supported via set/clear functions —...
Page 47: Debug Module
• Drive output pins to stable levels 1.3.4 On-chip Memories 1.3.4.1 Cache The MCF5329 architecture includes a 16-Kbyte unified cache. This four-way, set-associative cache provides pipelined, single-cycle access on cached instructions and operands. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 48: Lcd Controller
The product is suitable for applications that require real-time two-way voice communications and control interfaces, including: • Building intercom systems • Building fire and alarm panels • Emergency panels and poles • Drive-thru kiosks • Self-serve kiosks • Elevator control panels MCF5329 Reference Manual, Rev 3 1-10 Freescale Semiconductor...
Page 49: Sdr/Ddr Sdram Controller
1.3.8 USB Host and OTG Controllers MCF5329 supports two separate USB 2.0 compliant controllers on chip; a host-only core and an On-The-Go (or dual-role) core. Both controllers support full-speed (12 Mbps) and/or low-speed (1.5 Mbps) USB data rates via on-chip transceivers (The USB OTG module in device mode does not support low-speed).
Page 50: Synchronous Serial Interface (Ssi)
This allows for the implementation of common Internet security protocol cryptography operations with performance well in excess of software-only algorithms. Each of the three accelerator modules contains a DMA option for transferring data. MCF5329 Reference Manual, Rev 3 1-12 Freescale Semiconductor...
Page 51: Flexcan
32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTnIN MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 52: Software Watchdog Timer
1.3.22 Interrupt Controllers There are two interrupt controllers on the MCF5329, which can support up to 126 interrupt sources. Each interrupt source has a unique interrupt vector, and all sources of a given controller provide a programmable level (1-7).
Page 53: Flexbus External Interface
Most of the pins associated with the FlexBus interface may be used for several different functions. Their primary function is to provide an external interface to access off-chip resources. When not used for this, the pins may be used as general-purpose digital I/O pins. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 1-15...
Page 54: Documentation
Overview Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale World Wide Web address at http://www.freescale.com/coldfire. MCF5329 Reference Manual, Rev 3 1-16 Freescale Semiconductor...
Page 55: Signal Descriptions
Pins that are muxed with GPIO default to their GPIO functionality. Table 2-1. MCF5327/8/9 Signal Information and Muxing MCF53281 MCF5327 MCF5328 MCF5329 Signal Name GPIO Alternate 1 Alternate 2 MAPBGA MAPBGA MAPBGA Reset RESET — — — EVDD RSTOUT — — — EVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 56 R6, N7, P7, N5, P5, L6 R7, T7, P8, R7, T7, P8, — FB_D[16] — SDVDD BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] — SDVDD H4, P3, G1, L4, P6, L3, L4, P6, L3, PBUSCTL3 — — SDVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 57 PIRQ6 USBHOST_ — EVDD — VBUS_EN IRQ5 PIRQ5 USBHOST_ — EVDD — VBUS_OC IRQ4 PIRQ4 SSI_MCLK — EVDD IRQ3 PIRQ3 — — EVDD IRQ2 PIRQ2 USB_CLKIN — EVDD IRQ1 PIRQ1 DREQ1 SSI_CLKIN EVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 58 PLCDDM[3:0] — — EVDD C5, D5, A4, D6, E6, A5, D6, E6, A5, LCD_D7 PLCDDL7 — — EVDD LCD_D6 PLCDDL6 — — EVDD LCD_D5 PLCDDL5 — — EVDD LCD_D4 PLCDDL4 — — EVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 59 USBHOST_P — — — FlexCAN (MCF53281 & MCF5329 only) CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing: I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX. PWM7 PPWM7 —...
Page 60 — — EVDD U0RTS PUARTL2 — — EVDD U0TXD PUARTL1 — — EVDD U0RXD PUARTL0 — — EVDD Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 61 SD_VDD — — — — — E8, E9, E9, F9–F11, E9, F9–F11, F8–F10, G11, H11, G11, H11, J5–J7, K7 J5, J6, K5, J5, J6, K5, K6, L5–L8, K6, L5–L8, M6, M7 M6, M7 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 62: Internal Pull-Up/Pull-Downs Resistors
Always, except JTAG mode XTAL When not in crystal oscillator mode (intended for factory test) IRQ[7:2] IRQ mode only IRQ1 IRQ and DREQ modes Only when used as TA QSPI_DOUT C mode only (I2C_SDA) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 63: Signal Primary Functions
RSTOUT is driven low for 512 FB_CLK clock cycles in response to any internal or external reset. 2.3.2 PLL and Clock Signals Table 2-4 describes signals that are used to support the on-chip clock generation circuitry. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 64: Mode Selection
Controls whether certain pins act as FlexBus or SDRAMC signals. Select When asserted, D[31:0] dynamically switches between SDR data and FlexBus data. When negated, D[31:16] are dedicated for DDR data while D[15:0] are dedicated for FlexBus data. MCF5329 Reference Manual, Rev 3 2-10 Freescale Semiconductor...
Page 65: Flexbus Signals
Transfer Start Bus control output signal indicating the start of a transfer. Chip Selects FB_CS[5:0] These output signals select external devices for external bus transactions. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 2-11...
Page 66: Sdram Controller Signals
Table 2-8 describes the external interrupt signals. Table 2-8. External Interrupt Signals Signal Name Abbreviation Function External Interrupts IRQ[7:1] External interrupt sources. 2.3.7 DMA Signals Table 2-9 describes the external DMA signals. MCF5329 Reference Manual, Rev 3 2-12 Freescale Semiconductor...
Page 67: Lcd Controller Signals
Management Data FEC_MDC In Ethernet mode, FEC_MDC is an output clock which provides a Clock timing reference to the PHY for data transfers on the FEC_MDIO signal. Applies to MII mode operation. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 2-13...
Page 68: I2C I/O Signals
FEC_RXDV—indicates that the PHY has detected an error in the current frame. When FEC_RXDV is not asserted FEC_RXER has no effect. Applies to MII mode operation. 2.3.10 C I/O Signals Table 2-12 describes the I C serial interface module signals. MCF5329 Reference Manual, Rev 3 2-14 Freescale Semiconductor...
Page 69: Flexcan Signals
QSPI_CS[2:0] Provide QSPI peripheral chip selects that can be programmed to be Chip Selects active high or low. 2.3.13 Synchronous Serial Interface (SSI) Signals The SSI module uses the signals in this section. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 2-15...
Page 70: Universal Serial Bus (Usb) Signals
60MHz clock which is generated on-chip USB Off-Chip Clock USBCLKIN Section 2.3.2, “PLL and Clock Signals” 2.3.15 Pulse Width Modulation (PWM) Module Signals The following table describes the signals for the PWM module. MCF5329 Reference Manual, Rev 3 2-16 Freescale Semiconductor...
Page 71: Uart Module Signals
2.3.18 Debug Support Signals These signals are used as the interface to the on-chip JTAG controller and the BDM logic. Pin functionality between JTAG and BDM is dependent upon the JTAG_EN pin. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 2-17...
Page 72 Entry into user mode 0100 Begin execution of PULSE and WDDATA instructions 0101 Begin execution of taken branch 0110 Reserved 0111 Begin execution of RTE instruction 1000 Begin one-byte transfer on DDATA MCF5329 Reference Manual, Rev 3 2-18 Freescale Semiconductor...
Page 73: Test Signals
These pins supply positive power to the USB controllers. — USB Ground USB_VSS These pins are the negative supply (ground) for the USB controllers. — Ground These pins are the negative supply (ground) for the device. — MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 2-19...
Page 74: External Boot Mode
Signal Descriptions External Boot Mode After reset, the address bus, data bus, FlexBus control signals, and SDRAM control signals default to their bus functionalities. All other signals default to GPIO inputs (if applicable). MCF5329 Reference Manual, Rev 3 2-20 Freescale Semiconductor...
Page 75: Coldfire Core
3.1.1 Overview As with all ColdFire cores, the V3 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 76 — Instruction fetch cycle 2 (IC2) — Completes prefetch on the processor’s local bus — Instruction early decode (IED) — Generates time-critical decode signals needed for the OEP — Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO queue MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 77 Given that the two pipelines are decoupled, in many cases, the target instruction is available to the OEP immediately after the BRA instruction, making its execution time appear as a single cycle. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 78: Memory Map/Register Description
• 32-bit supervisor stack pointer (SSP) • 32-bit vector base register (VBR) • 32-bit cache control register (CACR) • 32-bit access control registers (ACR0, ACR1) • One 32-bit memory base address register (RAMBAR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 79 RAM Base Address Register (RAMBAR) See Section 3.2.10/3-10 The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see Chapter 36, “Debug Module”. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 80: Data Registers (D0-D7)
SR[S] = 1 then A7 = Supervisor Stack Pointer OTHER_A7 = User Stack Pointer else A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Pointer MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 81: Condition Code Register (Ccr)
The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed. BDM: LSB of Status Register (SR) Access: User read/write BDM read/write Reset: — — — — — Figure 3-5. Condition Code Register (CCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 82: Program Counter (Pc)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. The CACR is described in Section 5.2.1, “Cache Control Register (CACR).” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 83: Access Control Registers (Acrn)
— — — — Figure 3-8. Status Register (SR) Table 3-3. SR Field Descriptions Field Description Trace enable. When set, the processor performs a trace exception after every instruction. Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 84: Memory Base Address Register (Rambar)
IED stage with the feedback to the prefetch address logic in the IAG stage. The OEP is essentially unchanged from the Version 2 design with the exception of the extended opword provided from the IFP as part of the instruction interface: MCF5329 Reference Manual, Rev 3 3-10 Freescale Semiconductor...
Page 85: Instruction Set Architecture (Isa_A+)
Instruction Set Architecture (ISA_A+) The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code. The ISA was optimized for code compiled MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-11...
Page 86: Exception Processing Overview
All ColdFire processors use an instruction restart exception model. However, Version 3 ColdFire processors require more software support to recover from certain access errors. See Section 3.3.4.1, “Access Error Exception” for details. MCF5329 Reference Manual, Rev 3 3-12 Freescale Semiconductor...
Page 87 Number(s) Offset (Hex) Counter 0x000 — Initial supervisor stack pointer 0x004 — Initial program counter 0x008 Fault Access error 0x00C Fault Address error 0x010 Fault Illegal instruction 0x014 Fault Divide by zero MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-13...
Page 88: Exception Stack Frame Definition
A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor, indicating a two-longword frame format. See Table 3-6. MCF5329 Reference Manual, Rev 3 3-14 Freescale Semiconductor...
Page 89: Processor Exceptions
For this type of exception, the programming model has not been altered by the instruction generating the access error. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-15...
Page 90 (opmode), and the low-order 6 bits define the effective address. See Figure 3-12. The opword line definition is shown in Table 3-8. Line OpMode Effective Address Mode Register Figure 3-12. ColdFire Instruction Operation Word (Opword) Format MCF5329 Reference Manual, Rev 3 3-16 Freescale Semiconductor...
Page 91 There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in user mode for debugging purposes. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-17...
Page 92 The processor does not generate an IACK cycle, but rather calculates the vector number internally (vector number 12). Additionally, SR[M,I] are unaffected by the interrupt. MCF5329 Reference Manual, Rev 3 3-18 Freescale Semiconductor...
Page 93 Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-19...
Page 94 Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-13. BDM: Load: 0x080 (D0) Access: User read-only BDM read-only Store: 0x180 (D0) Reset R MAC DIV EMAC FPU DEBUG Reset Figure 3-13. D0 Hardware Configuration Info MCF5329 Reference Manual, Rev 3 3-20 Freescale Semiconductor...
Page 95 Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core. DEBUG 0000 DEBUG_A 0001 DEBUG_B 0010 DEBUG_C 0011 DEBUG_D 0100 DEBUG_E 1001 DEBUG_B+ (This is the value used for this device.) 1011 DEBUG_D+ 1111 DEBUG_D+PST Buffer Else Reserved MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-21...
Page 96 0001 512 bytes 0010 1 Kbytes 0011 2 Kbytes 0100 4 Kbytes 0101 8 Kbytes 0110 16 Kbytes (This is the value used for this device) 0111 32 Kbytes Else Reserved for future use MCF5329 Reference Manual, Rev 3 3-22 Freescale Semiconductor...
Page 97: Instruction Execution Timing
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-23...
Page 98: Move Instruction Execution Times
(d16,Ay) 4(1/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — (d8,Ay,Xi*SF) 5(1/0) 5(1/1) 5(1/1) 5(1/1) — — — xxx.w 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — — xxx.l 4(1/0) 4(1/1) 4(1/1) 4(1/1) — — — MCF5329 Reference Manual, Rev 3 3-24 Freescale Semiconductor...
Page 99 1(0/1) 1(0/1) 2(0/1) 1(0/1) — EXT.W 1(0/0) — — — — — — — EXT.L 1(0/0) — — — — — — — EXTB.L 1(0/0) — — — — — — — MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-25...
Page 100 4(1/1) — BSET #imm,<ea> 2(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) — — — BTST Dy,<ea> 2(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) — BTST #imm,<ea> 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — — MCF5329 Reference Manual, Rev 3 3-26 Freescale Semiconductor...
Page 101: Miscellaneous Instruction Execution Times
— — MOVE.W CCR,Dx 1(0/0) — — — — — — — MOVE.W <ea>,CCR 1(0/0) — — — — — — 1(0/0) MOVE.W SR,Dx 1(0/0) — — — — — — — MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-27...
Page 102: Emac Instruction Execution Times
MOVE.L <ea>y, Raccx 1(0/0) — — — — — — 1(0/0) MOVE.L Raccy,Raccx 1(0/0) — — — — — — — MOVE.L <ea>y, MACSR 5(0/0) — — — — — — 5(0/0) MCF5329 Reference Manual, Rev 3 3-28 Freescale Semiconductor...
Page 103 In general, these store operations require only a single cycle for execution, but if preceded immediately by a load, MAC, or MSAC instruction, the depth of the EMAC pipeline is exposed and the execution time is four cycles. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-29...
Page 104 3. For conditional branch opcodes (bcc), a static algorithm is used to determine the prediction state of the branch. This algorithm is: if bcc is a forward branch if CCR[P] == 0 MCF5329 Reference Manual, Rev 3 3-30 Freescale Semiconductor...
Page 105 3-20. The execution time for the predicted correctly as taken column can vary between 1 to 3 cycles depending on the amount of decoupling between the IFP and OEP as previously discussed. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 3-31...
Page 106 ColdFire Core MCF5329 Reference Manual, Rev 3 3-32 Freescale Semiconductor...
Page 107: Enhanced Multiply-Accumulate Unit (Emac)
The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module (Figure 4-1). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 108 ( )x i k b 0 ( )x i ( ) b 1 ( )x i 1 b 2 ( )x i 2 b 3 ( )x i 3 Eqn. 4-2 – – – – MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 109: Memory Map/Register Definition
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator is used to form the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 110 MULS and MULU instructions. Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 111: Mask Register (Mask)
For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows: mac.sz Ry,RxSF,<ea>yand ,Rw MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 112: Accumulator Registers (Acc0-3)
Performs a simple AND with the operand address for MAC instructions. MASK 4.2.3 Accumulator Registers (ACC0–3) The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 113: Accumulator Extension Registers (Accext01, Accext23)
Table 4-6. ACCext01 Field Descriptions Field Description 31–24 Accumulator 0 upper extension byte ACC0U 23–16 Accumulator 0 lower extension byte ACC0L 15–8 Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 114: Functional Description
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 115 Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 116: Fractional Operation Mode
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). MCF5329 Reference Manual, Rev 3 4-10 Freescale Semiconductor...
Page 117 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory This code performs the EMAC state restore: EMAC_state_restore: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 4-11...
Page 118: Emac Instruction Set Summary
Store MAC Mask Reg Writes the contents of the MASK to a CPU register move.l MASK,Rx Load Accumulator move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit Extensions 01 operand MCF5329 Reference Manual, Rev 3 4-12 Freescale Semiconductor...
Page 119: Emac Instruction Execution Times
1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 4-13...
Page 120: Data Representation
For the EMAC, assemblers support this syntax and no explicit reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. MCF5329 Reference Manual, Rev 3 4-14 Freescale Semiconductor...
Page 121 = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 4-15...
Page 122 (MACSR.OMC == 0 || MACSR.PAVn == 0) then { MACSR.PAVn = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) MCF5329 Reference Manual, Rev 3 4-16 Freescale Semiconductor...
Page 123 MACSR.PAVn = 0 /* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 4-17...
Page 124 {MACSR.PAVn = 1 MACSR.V = 1 if (inst == MSAC and and MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ MCF5329 Reference Manual, Rev 3 4-18 Freescale Semiconductor...
Page 125 ACCx[47:0] = result[47:0] MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1 break; MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 4-19...
Page 126 Enhanced Multiply-Accumulate Unit (EMAC) MCF5329 Reference Manual, Rev 3 4-20 Freescale Semiconductor...
Page 127: Introduction
For a read, the cache supplies data to the processor. In write, the processor updates the cache. If an access does not match a cache entry (misses the cache) or if a write access must be written MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 128: Memory Map/Register Definition
Figure 5-2. Cache Control Register (CACR) Table 5-2. CACR Field Descriptions Field Description Enable cache. 0 Cache disabled. The data cache is not operationa;l however, data and tags are preserved. 1 Cache enabled. Reserved, should be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 129 11 Cache-inhibited, imprecise exception model. Precise and imprecise accesses are described in Section 5.3.4, “Cache-Inhibited Accesses.” 7–6 Reserved, should be cleared. Default write protect. Indicates the default write privilege. 0 Read and write accesses permitted 1 Write accesses not permitted MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 130: Access Control Registers (Acr0–Acr1)
16 Mbytes. The mask can define multiple noncontiguous regions Mask of memory. Enable. Enables or disables the other ACRn bits. 0 Access control attributes disabled 1 Access control attributes enabled MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 131: Functional Description
All four longwords must be loaded for the cache line to be valid. Figure 5-4 shows cache organization and terminology used. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 132 After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the cacheable entry is loaded into the same set in way 1, as shown in Figure 5-5 (D). This process is described in detail in Section 5.3, “Functional Description.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 133: Cache Operation
CACR[CINVA] before the cache is enabled. Figure 5-5. Data Cache: A) at Reset; B) after Invalidation; C and D) Loading Pattern 5.3.2 Cache Operation Figure 5-6 shows the general flow of a caching operation. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 134 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to the next way. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 135 In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can service additional read accesses from this buffer until another fill or a cache-invalidate-all operation occurs. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 136: Caching Modes
Copyback regions are typically used for local data structures or stacks to minimize external bus use and reduce write-access latency. Write accesses to regions specified as copyback that hit in the cache update the cache line and set the corresponding M bit without an external bus access. MCF5329 Reference Manual, Rev 3 5-10 Freescale Semiconductor...
Page 137: Cache-Inhibited Accesses
All CPU space-register accesses, such as MOVEC, are treated as cache-inhibited and precise. 5.3.5 Cache Protocol The following sections describe the cache protocol for processor accesses and assumes that the data is cacheable (that is, write-through or copyback). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 5-11...
Page 138: Read Miss
First execute a CPUSHL instruction or set CACR[CINVA] before switching the cache mode. MCF5329 Reference Manual, Rev 3 5-12 Freescale Semiconductor...
Page 139: Cache Coherency
Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 140 The NOP instruction should be used only to synchronize the pipeline. The preferred no-op function is the TPF instruction. See the ColdFire Programmer’s Reference Manual for more information on the TPF instruction. MCF5329 Reference Manual, Rev 3 5-14 Freescale Semiconductor...
Page 141: Cache Locking
Ways 0 and 1 remain updated on write hits (D in Figure 5-8) and may be pushed or cleared only explicitly by using specific cache push/invalidate instructions. However, new cache lines cannot be allocated in ways 0 and 1. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 5-15...
Page 142: Cache Management
The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware reset clears CACR, disabling the cache and removing all configuration information; however, reset does not affect the tags, state information, and data in the cache. MCF5329 Reference Manual, Rev 3 5-16 Freescale Semiconductor...
Page 143: Cache Operation Summary
Before replacement, modified lines are temporarily buffered and later copied back to memory after the new line has been read from memory. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 5-17...
Page 144 Read hit (C,W)I2 Not possible. (C,W)V2 Supply data to processor; CD2 Supply data to processor; stay in valid state. stay in modified state. MCF5329 Reference Manual, Rev 3 5-18 Freescale Semiconductor...
Page 145 Cache (C,W)I7 No action; (C,W)V7 No action; CD7 Push modified line to push stay in invalid state. stay in valid state. memory; go to valid state MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 5-19...
Page 146 Write hit (copy-back) Write data to cache. Go to modified state. Write hit (write-through) Write data to memory and to cache. Stay in valid state. Cache invalidate (C,W)V5 No action. Go to invalid state. MCF5329 Reference Manual, Rev 3 5-20 Freescale Semiconductor...
Page 147 CD5 No action (modified data lost). Go to invalid state. Cache push CD6 Push modified line to memory. Go to invalid state. Cache push CD7 Push modified line to memory. Go to valid state MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 5-21...
Page 148 Cache MCF5329 Reference Manual, Rev 3 5-22 Freescale Semiconductor...
Page 149: Introduction
• One 32 Kbyte SRAM • Single-cycle access • Physically located on the processor's high-speed local bus • Memory location programmable on any 0-modulo-32 Kbyte address • Byte, word, and longword address capabilities MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 150: Memory Map/Register Description
SRAM memory. For example, writes to addresses 0x8000_0000 and 0x8000_8000 modify the same memory location. System software should ensure SRAM address pointers do not exceed the SRAM size to prevent unwanted overwriting of SRAM. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 151 0 Allows read and write accesses to the SRAM module from non-core masters. 1 Allows only read accesses to the SRAM module from non-core masters. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 152: Initialization/Application Information
The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros. RAMBASE EQU 0x80000000 ;set this variable to 0x80000000 RAMVALID EQU 0x00000001 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 153: Power Management
Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation. Table 6-3 shows examples of typical RAMBAR settings. Table 6-3. Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR[7:0] Instruction Only 0x2B Data Only 0x35 Instructions and Data 0x21 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 154 Static RAM (SRAM) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 155: Introduction
(e.g. clocks to the SDRAMC and USB are disabled when the device is in limp mode, and the clocks to individual modules may be disabled via the peripheral power management registers). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 156 EXTAL DMA Timers XTAL32K QSPI Oscillator (32kHz) UART Clock Module EXTAL32K GPIO RNG, SKHA, MDHA SSICLKIN MISCCR[SSISRC] USBCLKIN USB Host & OTG MISCCR[USBSRC] FlexCAN CANCTRLn[CLK_SRC] Real Time Clock Figure 7-1. Device Clock Connections MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 157: Block Diagram
The PLL operational mode must be configured during reset. The reset configuration pins must be driven to the appropriate state for the desired mode from the time RSTOUT asserts until it negates. Refer to Chapter 9, “Chip Configuration Module (CCM).” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 158 1. Code execution must be transferred to another memory resource. Primary options are whatever memory device is attached to the FlexBus boot chip select or on-chip SRAM (but not the CPU cache, as it may have to be flushed upon limp mode entrance or exit). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 159: Memory Map/Register Definition
The PLL module programming model consists of the following registers: Table 7-2. PLL Memory Map Width Address Register Access Reset Value Section/Page (bits) 0xFC0C_0000 PLL Output Divider Register (PODR) 0x26 7.2.1/7-6 0xFC0C_0004 PLL Control Register (PCR) 0x00 7.2.2/7-6 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 160: Pll Output Divider Register (Podr)
Value Core Clock Bus Clock 0010 VCO/2 Reserved 0110 Reserved VCO/6 Else Reserved Reserved 7.2.2 PLL Control Register (PCR) Address: 0xFC0C_0004 (PCR) Access:User read/write DITHEN DITHDEV Reset: Figure 7-4. PLL Control Register (PCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 161: Pll Modulation Divider Register (Pmdr)
Note: This field should only be written when dithering mode is disabled (PCR[DITHEN] = 0). Else, unpredictable PLL operation results. 7.2.3 PLL Modulation Divider Register (PMDR) Address: 0xFC0C_0008 (PMDR) Access: User read/write MODDIV Reset: Figure 7-5. PLL Modulation Divider Register (PMDR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 162: Pll Feedback Divider Register (Pfdr)
The PLL is capable of generating output clocks with a frequency that modulates in a triangular waveform with a specified percentage frequency deviation and a specified dither modulation frequency. This modulation of the output clock is called dithered operation. When the PLL operates at a fixed frequency, MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 163: Dithering Waveform Definition
(or dithering deviation) and the modulation period (which is the inverse of the dither modulation frequency) are shown in Figure 7-7. The dithering deviation is controlled by PCR[DITHDEV] field, while the dither modulation frequency is controlled by the PMDR[MODDIV] field. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 164: Pll Frequency Multiplication Factor Select
PLL Frequency Multiplication Factor Select The frequency multiplication factor of the PLL is defined by the feedback divider in the following equation: ⎛ ⎞ PFDR × -------------------------------------------------- - Eqn. 7-2 ⎝ ⎠ × PODR[CPUDIV] MCF5329 Reference Manual, Rev 3 7-10 Freescale Semiconductor...
Page 165: System Clock Modes
PLL output clock frequencies are not stable and not within specification. The MISCCR[PLLLOCK] bit is set after RESET has negated for a minimum of 1 ms. When this bit is set, the PLL is in frequency lock. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 7-11...
Page 166: External Reset
This bit is set after the PLL lock period of 1 ms has passed. CAUTION When running in an unlocked state, the clocks generated by the PLL are not guaranteed to be stable and may exceed the maximum specified frequency of the device. MCF5329 Reference Manual, Rev 3 7-12 Freescale Semiconductor...
Page 167: Introduction
0xFC04_0030 Peripheral Power Management High Register 0 (PPMHR0) 0x0000_0000 8.2.4/8-4 0xFC04_0034 Peripheral Power Management Low Register 0 (PPMLR0) 0x0000_0000 8.2.4/8-4 0xFC04_0038 Peripheral Power Management High Register 1 (PPMHR1) 0x0000_0000 8.2.4/8-4 0xFC0A_0007 Low-Power Control Register (LPCR) 0x00 8.2.5/8-7 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 168: Wake-Up Control Register
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks. 7. With the processor clocks enabled, the core processes the pending interrupt request. Address: 0xFC04_0013 (WCR) Access: Supervisor read/write ENBWCR PRILVL Reset: Figure 8-1. Wake-up Control Register (WCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 169: Peripheral Power Management Set Registers (Ppmsr0 & Ppmsr1)
Reads of these registers return all zeroes. Address: 0xFC04_002C (PPMSR0) Access: Supervisor Write-only 0xFC04_002E (PPMSR1) SAMCD SMCD Reset: Figure 8-2. Peripheral Power Management Set Registers (PPMSRn) Table 8-3. PPMSRn Field Descriptions Field Description Reserved, should be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 170: Peripheral Power Management Clear Registers (Ppmcr0 & Ppmcr1)
Recall each peripheral module is mapped into 16 kByte slots within the memory map. The PPMR registers provide a unique control bit for each of these address spaces that defines whether the module clock for the given space is enabled or disabled. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 171 CD38 CD37 CD36 CD35 CD34 CD33 CD32 Reset Figure 8-5. Peripheral Power Management High Register (PPMHR0) Table 8-6. PPMHR0[CDn] Assignments Slot Number Peripheral CD32 PIT 0 CD33 PIT 1 CD34 PIT 2 CD35 PIT 3 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 172 Figure 8-6. Peripheral Power Management Low Registers (PPMLR0) Table 8-7. PPMLR0[CDn] Assignments Slot Number Peripheral FlexBus FlexCAN CD12 CD17 eDMA Controller CD18 Interrupt Controller 0 CD19 Interrupt Controller 1 CD21 IACK CD22 CD23 QSPI MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 173: Low-Power Control Register (Lpcr)
8.2.5 Low-Power Control Register (LPCR) The LPCR register controls chip operation and module operation during low-power modes. Address: 0xFC0A_0007 (LPCR) Access: Supervisor read/write LPMD FWKUP STPMD Reset: Figure 8-7. Low-Power Control Register (LPCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 174: Functional Description
The device may also be booted into a low-frequency limp mode, in which the PLL is bypassed and the device runs from a factor of the input clock (EXTAL). In this mode, EXTAL feeds a 5-bit programmable MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 175: Low-Power Modes
Doze Mode Doze mode affects the CPU in the same manner as wait mode, except that some peripherals define individual operational characteristics in doze mode. Peripherals which continue to run and have the MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 176: Peripheral Behavior In Low-Power Modes
When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support systems using FB_CLK as the clock source. See Section 8.2.5, “Low-Power Control Register (LPCR),” for more information about operating the PLL in stop mode. MCF5329 Reference Manual, Rev 3 8-10 Freescale Semiconductor...
Page 177 If low-power mode is exited by a reset, the state of the I/O pins reverts to their default direction settings. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 178 SDRAM. When stop mode is exited, setting the SDCR[CKE] bit causes the SDRAM controller to exit the self-refresh mode and allow bus cycles to the SDRAM to resume. MCF5329 Reference Manual, Rev 3 8-12 Freescale Semiconductor...
Page 179 If stop mode is asserted while the FlexCAN is BUSOFF (see error and status register), then the FlexCAN enters stop mode and stops counting the synchronization sequence; it continues this count after stop mode is exited. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 8-13...
Page 180 8.3.4.20 Queued Serial Peripheral Interface (QSPI) In wait and doze modes, the QSPI module is unaffected and may generate an interrupt to exit these low-power modes. MCF5329 Reference Manual, Rev 3 8-14 Freescale Semiconductor...
Page 181: Summary Of Peripheral State During Low-Power Modes
Individual peripherals may be disabled by programming its dedicated control bits. The wake-up capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 8-15...
Page 182 Interrupt Stopped UARTs Enabled Interrupt Enabled Interrupt Stopped C Module Enabled Interrupt Enabled Interrupt Stopped Cryptography Modules (RNG, SKHA, MDHA) Enabled Interrupt Enabled Interrupt Stopped JTAG Enabled Enabled Enabled Enabled Enabled Enabled MCF5329 Reference Manual, Rev 3 8-16 Freescale Semiconductor...
Page 183 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any lower-power mode. Upon exit from halt mode, the previous low-power mode is re-entered and changes made in halt mode remain in effect. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 184 Power Management MCF5329 Reference Manual, Rev 3 8-18 Freescale Semiconductor...
Page 185: Introduction
The only chip operating mode available on this device is master mode. In master mode, the ColdFire core can access external memories and peripherals.The external bus consists of a 32-bit data bus and 24 address MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 186: External Signal Descriptions
See Section 9.3.1/9-3 0xFC0A_0008 Reset Configuration Register (RCON) 0x0001 9.3.2/9-4 0xFC0A_000A Chip Identification Register (CIR) See Section 9.3.3/9-4 0xFC0A_0010 Miscellaneous Control Register (MISCCR) See Section 9.3.4/9-5 0xFC0A_0012 Clock Divider Register (CDR) 0x0001 9.3.5/9-6 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 187: Chip Configuration Register (Ccr)
1 High drive strength, high slew rate 4–3 Boot port size field. Indicates the selection for the boot port size. BOOTPS 00 32 bits 01 16 bits 10 8 bits 11 32 bits MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 188: Reset Configuration Register (Rcon)
0x058 MCF53281 0x059 MCF5328 0x061 MCF5327 5–0 Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 189: Miscellaneous Control Register (Misccr)
SSI RXD/TXD pull select. Selects whether the internal weak pull cells enabled by the SSIPUE bit are pull up or SSIPUS pull down. 0 SSI data pins are pulled down. 1 SSI data pins are pulled up. Note: The SSIPUS bit has no effect when the SSIPUE bit is cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 190: Clock Divider Register
MISCCR[LIMP] bit is set. ---------------- Eqn. 9-1 System Clocks LPDIV Note: When LPDIV = 0 (divide-by-1), the internal bus clock and FB_CLK do not have a 50/50 duty cycle. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 191: Usb Host Controller Status Register (Uhcsr)
USB On-the-Go Controller Status Register (UOCSR) The UOCSR register controls and reflects various features of the USB OTG module. When any bit of this register generates an interrupt, that interrupt can be cleared by reading the UOCSR register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 192 1 Power fault has occured. USB OTG controller wakeup event. Reflects if a wakeup event has occured on the USB OTG Controller Bus WKUP 0 No outstanding wakeup event. 1 Wakup event has occurred. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 193: Functional Description
RCON register or fixed defaults, regardless of the states of the external data pins. The internal configuration signals are driven to levels specified by the RCON register’s reset state for default module configuration. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 194 Chip Select Configuration A[23:22] = A[23:22] (default) Reserved A23 = FB_CS5 and A22 = A22 A[23:22] = FB_CS[5:4] Modifying the default configurations is possible only if the external RCON pin is asserted. MCF5329 Reference Manual, Rev 3 9-10 Freescale Semiconductor...
Page 195: Pll Mode Selection
Output pads configured for low drive strength D5 driven low Output pads configured for full drive strength D5 driven high Modifying the default configurations is possible only if the external RCON pin is asserted low. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 9-11...
Page 196: Chip Select Configuration
The chip select configuration (FB_CS[5:4]) is selected during reset and reflected in the CCR[CSC] field. After reset is exited, the chip select configuration cannot be changed. Table 9-10 shows the different chip select configurations that can be implemented during reset configuration. MCF5329 Reference Manual, Rev 3 9-12 Freescale Semiconductor...
Page 197: Introduction
— On-chip watchdog timer — Phase locked-loop (PLL) loss of lock — Software • Software-assertable RSTOUT pin independent of chip reset state • Software-readable status flags indicating the cause of the last reset MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 10-1...
Page 198: External Signal Description
0x00 10.3.1/10-2 0xFC0A_0001 Reset Status Register (RSR) See Section 10.3.2/10-3 10.3.1 Reset Control Register (RCR) The RCR allows software control for requesting a reset, and for independently asserting the external RSTOUT pin. MCF5329 Reference Manual, Rev 3 10-2 Freescale Semiconductor...
Page 199: Reset Status Register (Rsr)
Description 7–6 Reserved, should be cleared. Software reset flag. Indicates that the last reset was caused by software. SOFT 0 Last reset not caused by software 1 Last reset caused by software MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 10-3...
Page 200: Functional Description
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system. MCF5329 Reference Manual, Rev 3 10-4 Freescale Semiconductor...
Page 201: Reset Control Flow
Figure 10-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 10-5...
Page 202 At this point the RSTOUT pin is asserted (5). The reset control logic waits until the RESET signal is negated (6) and for the PLL to attain lock (7) before waiting 512 FB_CLK cycles (8). The MCF5329 Reference Manual, Rev 3 10-6...
Page 203: Concurrent Resets
If other sources of reset are asserted after the RSR status bits have been latched (4 or 5), the device is held in reset (8) until all sources have negated and the subsequent sources are not reflected in the RSR contents. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 204 Reset Controller Module MCF5329 Reference Manual, Rev 3 10-8 Freescale Semiconductor...
Page 205: Introduction
— Core watchdog control register (CWCR) for watchdog timer control — Core watchdog service register (CWSR) to service watchdog timer — SCM interrupt status register (SCMISR) to service a bus fault or watchdog interrupt — Bus monitor timeout register (BMT) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-1...
Page 206: Memory Map/Register Definition
11.2.11/11-12 0xFC04_0077 Core Fault Attributes Register (CFATR) Undefined 11.2.12/11-12 0xFC04_007C Core Fault Data Register (CFDTR) Undefined 11.2.13/11-13 Take note of register location. The WCR register is described in Chapter 8, “Power Management.” MCF5329 Reference Manual, Rev 3 11-2 Freescale Semiconductor...
Page 207: Master Privilege Register 0 (Mpr0)
Reserved, should be cleared. Master trusted for read. Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-3...
Page 208: Master Privilege Register 1 (Mpr1)
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 11-5. Peripheral Access Control Register B (PACRB) MCF5329 Reference Manual, Rev 3 11-4...
Page 209 Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 11-11. Peripheral Access Control Register H (PACRH) Each peripheral is assigned to its PACRn field as shown below: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-5...
Page 210 PACR37 Edge Port PACR38 On-chip Watchdog Timer PACR40 CCM, Reset Controller, Power Management PACR41 GPIO Module PACR42 Real Time Clock PACR43 LCD Controller PACR44 USB On-the-Go PACR45 USB Host PACR46 SDRAM Controller MCF5329 Reference Manual, Rev 3 11-6 Freescale Semiconductor...
Page 211 Thus, the SCMISR[CFEI] bit is set, and an interrupt to the interrupt controller is generated if the CFIER[ECFEI] bit is set. At reset, the BMT is enabled with a maximum timeout value. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 212 1 CWCR is read-only. A system reset is required to clear this register. The setting of this bit is intended to prevent accidental writes of the CWCR from changing the defined core watchdog configuration. 14–9 Reserved, should be cleared. MCF5329 Reference Manual, Rev 3 11-8 Freescale Semiconductor...
Page 213: Core Watchdog Service Register (Cwsr)
0x55 or 0xAA causes an immediate system reset, regardless of the value in the CWCR[CWRI] field. Address: 0xFC04_001B (CWSR) Access: User read/write CWSR Reset: — — — — — — — — Figure 11-15. Core Watchdog Service Register (CWSR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-9...
Page 214: Scm Interrupt Status Register (Scmisr)
The BCR register is used to enable or disable the LCD controller, USB host, and USB On-the-Go modules for bursting to/from the cross-bar switch slave modules. There is an enable field for the slaves, and either direction (read and write) is supported via the GBR and GBW bits. MCF5329 Reference Manual, Rev 3 11-10 Freescale Semiconductor...
Page 215: Core Fault Address Register (Cfadr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11-18. Core Fault Address Register (CFADR) Table 11-10. CFADR Field Descriptions Field Description 31–0 Indicates the faulting address of the last core access terminated with an error response. ADDR MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-11...
Page 216: Core Fault Interrupt Enable Register (Cfier)
1 Error occurred within the core. 6–0 Reserved, should be cleared. 11.2.12 Core Fault Attributes Register (CFATR) The read-only CFATR register captures the processor’s attributes of the last faulted core access to the system bus. MCF5329 Reference Manual, Rev 3 11-12 Freescale Semiconductor...
Page 217: Core Fault Data Register (Cfdtr)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 11-22. Core Fault Data Register (CFDTR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 218: Functional Description
To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by performing the following sequence: 1. Write 0x55 to CWSR. MCF5329 Reference Manual, Rev 3 11-14 Freescale Semiconductor...
Page 219: Core Data Fault Recovery Registers
The details on the core fault recovery registers are provided in the above sections. It is important to note these registers are used to capture fault recovery information on any processor-initiated system bus cycle that is terminated with an error. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 11-15...
Page 220 System Control Module (SCM) MCF5329 Reference Manual, Rev 3 11-16 Freescale Semiconductor...
Page 221: Overview
The MCF5329 devices have up to seven masters and four slaves (7Mx4S) connected to the crossbar switch. The seven masters are the ColdFire core, eDMA controller, FEC, LCD controller, USB host, USB OTG modules, and a reserved master for factory test.
Page 222 (e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-cacheable, and one ACR then identifies cacheable addresses, e.g., ADDR[31] equals 0 identifies the cacheable space. MCF5329 Reference Manual, Rev 3 12-2 Freescale Semiconductor...
Page 223: Features
0xFC00_4100 Priority Register Slave 1 (XBS_PRS1) 0x6543_0210 12.4.1/12-4 0xFC00_4110 Control Register Slave 1 (XBS_CRS1) 0x0000_0000 12.4.2/12-5 0xFC00_4400 Priority Register Slave 4 (XBS_PRS4) 0x6543_0210 12.4.1/12-4 0xFC00_4410 Control Register Slave 4 (XBS_CRS4) 0x0000_0000 12.4.2/12-5 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 12-3...
Page 224 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 (lowest) priority when accessing the slave port. Else Reserved Reserved, must be cleared. 26–24 Master 6 (USB OTG) priority. See M7 description. MCF5329 Reference Manual, Rev 3 12-4 Freescale Semiconductor...
Page 225 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 After this bit is set, only a hardware reset clears it. Figure 12-3. XBS Control Registers Slave n (XBS_CRSn) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 12-5...
Page 226: Arbitration
When operating in fixed-priority mode, each master is assigned a unique priority level in the XBS_PRSn (priority registers). If two masters request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. MCF5329 Reference Manual, Rev 3 12-6 Freescale Semiconductor...
Page 227: Initialization/Application Information
No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. Settings and priorities should be programmed to achieve maximum system performance. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 12-7...
Page 228 Crossbar Switch (XBS) MCF5329 Reference Manual, Rev 3 12-8 Freescale Semiconductor...
Page 229: Introduction
The GPIO functionality of the port IRQ pins is selected by the edge port module. They are shown in the below figure only for completeness. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-1...
Page 230: Overview
The GPIO module controls the configuration for various external pins, including those used for: • External bus accesses • External chip selection • Ethernet data and control • C serial control • QSPI • 32-bit DMA timers MCF5329 Reference Manual, Rev 3 13-2 Freescale Semiconductor...
Page 231: Features
Pins that are muxed with GPIO default to their GPIO functionality. Table 13-1. MCF5327/8/9 Signal Information and Muxing MCF53281 MCF5327 MCF5328 MCF5329 Signal Name GPIO Alternate 1 Alternate 2 MAPBGA MAPBGA MAPBGA Reset RESET — — — EVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-3...
Page 232 R6, N7, P7, R6, N7, P7, N5, P5, L6 R7, T7, P8, R7, T7, P8, — FB_D[16] — SDVDD BE/BWE[3:0] PBE[3:0] SD_DQM[3:0] — SDVDD H4, P3, G1, L4, P6, L3, L4, P6, L3, MCF5329 Reference Manual, Rev 3 13-4 Freescale Semiconductor...
Page 233 — — EVDD IRQ6 PIRQ6 USBHOST_ — — EVDD VBUS_EN IRQ5 PIRQ5 USBHOST_ — — EVDD VBUS_OC IRQ4 PIRQ4 SSI_MCLK — EVDD IRQ3 PIRQ3 — — EVDD IRQ2 PIRQ2 USB_CLKIN — EVDD MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-5...
Page 234 — — EVDD C5, D5, A4, D6, E6, A5, D6, E6, A5, LCD_D7 PLCDDL7 — — EVDD LCD_D6 PLCDDL6 — — EVDD LCD_D5 PLCDDL5 — — EVDD LCD_D4 PLCDDL4 — — EVDD MCF5329 Reference Manual, Rev 3 13-6 Freescale Semiconductor...
Page 235 USBHOST_P — — — FlexCAN (MCF53281 & MCF5329 only) CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing: I2C_SDA, SSI_RXD, or LCD_D16 for CANRX and I2C_SCL, SSI_TXD, or LCD_D17 for CANTX. PWM7 PPWM7 —...
Page 236 — EVDD U0RTS PUARTL2 — — EVDD U0TXD PUARTL1 — — EVDD U0RXD PUARTL0 — — EVDD Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins. MCF5329 Reference Manual, Rev 3 13-8 Freescale Semiconductor...
Page 237 — — — — — E8, E9, E9, F9–F11, E9, F9–F11, F8–F10, G11, H11, G11, H11, J5–J7, K7 J5, J6, K5, J5, J6, K5, K6, L5–L8, K6, L5–L8, M6, M7 M6, M7 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-9...
Page 238 Table 13-2. Multiple-Pin Functions Function Direction Associated Pins FB_CS5 FB_CS5 , A23 FB_CS5 FB_CS4 , A22 I2C_SDA I2C_SDA, QSPI_DOUT, FEC_MDIO I2C_SCL I2C_SCL, QSPI_CLK, FEC_MDC CANRX LCD_D16, I2C_SDA, SSI_RXD CANTX LCD_D17, I2C_SCL, SSI_TXD MCF5329 Reference Manual, Rev 3 13-10 Freescale Semiconductor...
Page 239: Memory Map/Register Definition
0xFC0A_4002 PODR_SSI 0x1F 13.3.1/13-14 0xFC0A_4003 PODR_BUSCTL 0x0F 13.3.1/13-14 0xFC0A_4004 PODR_BE 0x0F 13.3.1/13-14 0xFC0A_4005 PODR_CS 0x3E 13.3.1/13-14 0xFC0A_4006 PODR_PWM 0x3C 13.3.1/13-14 0xFC0A_4007 PODR_FECI2C 0x0F 13.3.1/13-14 0xFC0A_4009 PODR_UART 0xFF 13.3.1/13-14 0xFC0A_400A PODR_QSPI 0x3F 13.3.1/13-14 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-11...
Page 240 See Section 13.3.3/13-19 0xFC0A_402A PPDSDR_SSI See Section 13.3.3/13-19 0xFC0A_402B PPDSDR_BUSCTL See Section 13.3.3/13-19 0xFC0A_402C PPDSDR_BE See Section 13.3.3/13-19 0xFC0A_402D PPDSDR_CS See Section 13.3.3/13-19 0xFC0A_402E PPDSDR_PWM See Section 13.3.3/13-19 0xFC0A_402F PPDSDR_FECI2C See Section 13.3.3/13-19 MCF5329 Reference Manual, Rev 3 13-12 Freescale Semiconductor...
Page 241 13.3.4/13-21 0xFC0A_404D PCLRR_LCDCTLL 0x00 13.3.4/13-21 Pin Assignment Registers 0xFC0A_4050 PAR_FEC 0x00 13.3.5.8/13-29 0xFC0A_4051 PAR_PWM 0x00 13.3.5.11/13-31 0xFC0A_4052 PAR_BUSCTL 0xF8 13.3.5.1/13-24 0xFC0A_4053 PAR_FECI2C 0x00 13.3.5.4/13-26 0xFC0A_4054 PAR_BE 0x0F 13.3.5.2/13-24 0xFC0A_4055 PAR_CS 0x3E 13.3.5.3/13-25 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-13...
Page 242 PODR_x register, set the PODR_x bits, or set the corresponding bits in the PPDSDR_x register. To clear bits in a PODR_x register, clear the PODR_x bits, or clear the corresponding bits in the PCLRR_x register. MCF5329 Reference Manual, Rev 3 13-14...
Page 243 Address: 0xFC0A_4006 (PODR_PWM) Access: User read/write PODR_PWM Reset: Figure 13-4. Port PWM Output Data Register (PODR_PWM) Address: 0xFC0A_400A (PODR_QSPI) Access: User read/write PODR_QSPI Reset: Figure 13-5. Port QSPI Output Data Register (PODR_QSPI) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-15...
Page 244 0 Drives 0 when the port x pin is general purpose output 1 Drives 1 when the port x pin is general purpose output Note: See above figures for bit field positions. MCF5329 Reference Manual, Rev 3 13-16 Freescale Semiconductor...
Page 245 0xFC0A_401D (PDDR_UART) 0xFC0A_4022 (PDDR_LCDDATAM) 0xFC0A_4023 (PDDR_LCDDATAL) 0xFC0A_4025 (PDDR_LCDCTLL) PDDR_x Reset: Figure 13-11. Port Data Direction Registers (PDDR_x) Address: 0xFC0A_401A (PDDR_PWM) Access: User read/write PDDR_PWM Reset: Figure 13-12. Port PWM Data Direction Register (PDDR_PWM) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-17...
Page 246 Address: 0xFC0A_4021 (PDDR_LCDDATAH) Access: User read/write PDDR_LCDDATAH Reset: Figure 13-16. Port LCDDATAH Data Direction Register (PDDR_LCDDATAH) Address: 0xFC0A_4024 (PDDR_LCDCTLH) Access: User read/write PDDR_ LCDCTLH Reset: Figure 13-17. Port LCDCTLH Data Direction Register (PDDR_LCDCTLH) MCF5329 Reference Manual, Rev 3 13-18 Freescale Semiconductor...
Page 247 Access: User read/write 0xFC0A_4029 (PPDSDR_FECL) 0xFC0A_4031 (PPDSDR_UART) 0xFC0A_4036 (PPDSDR_LCDDATAM) 0xFC0A_4037 (PPDSDR_LCDDATAL) 0xFC0A_4039 (PPDSDR_LCDCTLL) PPDR_x PSDR_x Reset: [Px7] [Px6] [Px5] [Px4] [Px3] [Px2] [Px1] [Px0] Figure 13-19. Port Pin Data/Set Data Registers (PPDSDR_x) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-19...
Page 248 [PSSI1] [PSSI0] Figure 13-23. Port SSI Pin Data/Set Data Register (PPDSDR_SSI) Address: 0xFC0A_4035 (PPDSDR_LCDDATAH) Access: User read/write PPDSDR_LCDDATAH Reset: [PLCD [PLCD DATAH1] DATAH0] Figure 13-24. Port LCDDATAH Pin Data/Set Data Register (PPDSDR_LCDDATAH) MCF5329 Reference Manual, Rev 3 13-20 Freescale Semiconductor...
Page 249 The register definitions for all ports are shown in the figures below. Address: 0xFC0A_403F (PCLRR_BUSCTL) Access: User write-only 0xFC0A_4040 (PCLRR_BE) 0xFC0A_4043 (PCLRR_FECI2C) 0xFC0A_4047 (PCLRR_TIMER) PCLRR_x Reset: Figure 13-26. Port Clear Output Data Registers (PCLRR_x) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-21...
Page 250 Address: 0xFC0A_4046 (PCLRR_QSPI) Access: User write-only PCLRR_QSPI Reset: Figure 13-29. Port QSPI Clear Output Data Register (PCLRR_QSPI) Address: 0xFC0A_4041 (PCLRR_CS) Access: User write-only PCLRR_CS Reset: Figure 13-30. Port CS Clear Output Data Register (PCLRR_CS) MCF5329 Reference Manual, Rev 3 13-22 Freescale Semiconductor...
Page 251 Note: See above figures for bit field positions. 13.3.5 Pin Assignment Registers (PAR_x) The pin assignment registers control which functions are currently active on the external pins. All pin assignment registers are read/write. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-23...
Page 252 Byte Enable Pin Assignment Register (PAR_BE) The PAR_BE register controls the functions of the byte enable pins. Address: 0xFC0A_4054 (PAR_BE) Access: User read/write PAR_BE Reset: Figure 13-35. Byte Enable Pin Assignment Register (PAR_BE) MCF5329 Reference Manual, Rev 3 13-24 Freescale Semiconductor...
Page 253 0 FB_CS2 pin configured for GPIO 1 FB_CS2 pin configured for FlexBus FB_CS2 function FB_CS1 pin assignment. PAR_CS1 0 FB_CS1 pin configured for GPIO 1 FB_CS1 pin configured for FlexBus FB_CS1 function Reserved, should be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-25...
Page 254 QSPI Pin Assignment Register (PAR_QSPI) The PAR_QSPI register controls the functions of the QSPI pins. Address: 0xFC0A_405A (PAR_QSPI) Access: User read/write PAR_PCS2 PAR_PCS1 PAR_PCS0 PAR_DIN PAR_DOUT PAR_SCK Reset Figure 13-38. QSPI Pin Assignment (PAR_QSPI) MCF5329 Reference Manual, Rev 3 13-26 Freescale Semiconductor...
Page 255 DMA Timer pin assignment. These bit fields configure the DMA Timer pins for one of their primary functions or GPIO. PAR_T3IN 5–4 PAR_T3IN PAR_T2IN PAR_T1IN PAR_T0IN PAR_T2IN GPIO GPIO GPIO GPIO 3–2 PAR_T1IN U2RXD U2TXD DACK1 DREQ0 1–0 PAR_T0IN T3OUT T2OUT T1OUT T0OUT T3IN T2IN T1IN T0IN MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-27...
Page 256 0 U0RXD pin configured for GPIO 1 U0RXD pin configured for UART0 RXD function U0TXD pin assignment. PAR_U0TXD 0 U0TXD pin configured for GPIO 1 U0TXD pin configured for UART0 TXD function MCF5329 Reference Manual, Rev 3 13-28 Freescale Semiconductor...
Page 257 Reserved ULPI_DATA7 ULPI_DATA6 ULPI_DATA5 — ULPI_DIR FEC_RXD3 FEC_RXD2 FEC_RXD1 FEC_RXER FEC_CRS FEC_TXD3 FEC_TXD2 FEC_TXD1 FEC_TXER GPIO GPIO GPIO GPIO Reserved Reserved Reserved Reserved ULPI_DATA3 ULPI_DATA2 ULPI_DATA1 — FEC_TXD3 FEC_TXD2 FEC_TXD1 FEC_TXER Note: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-29...
Page 258 13.3.5.10 SSI Pin Assignment Register (PAR_SSI) The PAR_SSI register controls the functions of the SSI pins. Address: 0xFC0A_4056 (PAR_SSI) Access: User read/write PAR_ PAR_BCLK PAR_FS PAR_RXD PAR_TXD MCLK Reset Figure 13-43. SSI Pin Assignment (PAR_SSI) MCF5329 Reference Manual, Rev 3 13-30 Freescale Semiconductor...
Page 259 Figure 13-44. PWM Pin Assignment (PAR_PWM) Table 13-18. PAR_PWM Field Descriptions Field Description 7–6 Reserved, should be cleared. PWM7 pin assignment. PAR_PWM7 0 PWM7 pin configured as GPIO. 1 PWM7 pin configured for PWM 7 function. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-31...
Page 260 LCD data pin assignment. These bit fields configure the LCD data pins for one of their primary functions or GPIO. PAR_LD17 5–4 PAR_LD17 PAR_LD16 PAR_LD15_8 PAR_LD7_0 PAR_LD16 GPIO GPIO GPIO GPIO 3–2 PAR_LD15_8 Reserved Reserved Reserved Reserved 1–0 PAR_LD7_0 CANTX CANRX Reserved Reserved LCD_D17 LCD_D16 LCD_D[15:8] LCD_D[7:0] MCF5329 Reference Manual, Rev 3 13-32 Freescale Semiconductor...
Page 261 0 LCD_PS pin configured as GPIO. 1 LCD_PS pin configured for LCD controller PS function. LCD_CLS pin assignment. PAR_CLS 0 LCD_CLS pin configured as GPIO. 1 LCD_CLS pin configured for LCD controller CLS function. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-33...
Page 262 The MSCR_SDRAM register controls the output mode selects of the following dedicated SDRAM pins: SD_A10, SD_CAS, SD_CKE, SD_CLK, SD_CLK, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, and SD_WE. Address: 0xFC0A_4065 (MSCR_SDRAM) Access: User read/write MSCR_SDCLKB MSCR_SDCLK MSCR_SDRAM Reset: Figure 13-48. SDRAM Mode Select Control Register (MSCR_SDRAM) MCF5329 Reference Manual, Rev 3 13-34 Freescale Semiconductor...
Page 263 DT3IN, DT2IN, DT1IN, and DT0IN DSCR_SSI SSI_MCLK, SSI_BCLK, SSI_RXD, and SSI_TXD DSCR_LCD LCD_D[17:0], ACD/OE, CLS, CONTRAST, FLM/SYNC, LP/VSYNC, LSCLK, PS, REV, and SPL_SPR. DSCR_DEBUG PSTCLK, PST[3:0], DDATA[3:0], ALLPST, and DSO DSCR_IRQ IRQ[7:1] MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-35...
Page 264 UART0_DSE Reset: See Note See Note Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0. Figure 13-50. UART Drive Strength Control Register (DSCR_UART) MCF5329 Reference Manual, Rev 3 13-36 Freescale Semiconductor...
Page 265 FB_CLK mode select control. This bit field controls the strength of the FlexBus clock pin. MSCR_FBCLK 00 Half strength 1.8V. 01 Open drain. 10 Full strength 1.8V. 11 2.5V or 3.3V with roughly equal rise and fall delays. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-37...
Page 266: Overview
Figure 13-52. General Purpose Input Timing Data written to the PODR_x register of any pin configured as a general purpose output is immediately driven to its respective pin, as shown in Figure 13-53. MCF5329 Reference Manual, Rev 3 13-38 Freescale Semiconductor...
Page 267: Initialization/Application Information
The initialization for the ports module is done during reset configuration. All registers are reset to a predetermined state. Refer to Section 13.3, “Memory Map/Register Definition,” for more details on reset and initialization. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 13-39...
Page 268 General Purpose I/O Module MCF5329 Reference Manual, Rev 3 13-40 Freescale Semiconductor...
Page 269: Introduction
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-1...
Page 270: Memory Map/Register Definition
Global IACK Registers Space 0xFC05_4000 This address space only contains the global SWIACK and global L1ACK-L7IACK registers. See Section 14.2.10, “Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn – L7IACKn)" for more information MCF5329 Reference Manual, Rev 3 14-2 Freescale Semiconductor...
Page 271 0xFC04_C040 + n Interrupt Control Registers (ICR1n) 0x00 14.2.9/14-11 (n=1:63) 0xFC04_C0E0 Software Interrupt Acknowledge (SWIACK1) 0x00 14.2.10/14-15 0xFC04_C0E0 + 4n Level n Interrupt Acknowledge Registers (LnIACK1) 0x18 14.2.10/14-15 (n=1:7) Global IACK Registers MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-3...
Page 272 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14-2. Interrupt Pending Register Low (IPRLn) MCF5329 Reference Manual, Rev 3 14-4...
Page 273 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 14-3. Interrupt Mask Register High (IMRHn) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 274 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14-5. Interrupt Force Register High (INTFRCHn) MCF5329 Reference Manual, Rev 3 14-6...
Page 275 Only one copy of this register exists among the 2 interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. Address: 0xFC04_801A (ICONFIG) Access: User read/write ELVLPRI EMASK Reset Figure 14-7. Interrupt Configuration Register (ICONFIG) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-7...
Page 276 0 Only set those bits specified in the SIMR field. 1 Set all bits in IMRn register. The SIMR field is ignored. 5–0 Set the corresponding bit in the IMRn register, masking the interrupt request. SIMR MCF5329 Reference Manual, Rev 3 14-8 Freescale Semiconductor...
Page 277 In addition, an interrupt service routine can explicitly load this register with a lower priority value to query for any pending interrupts via software interrupt acknowledge cycles. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-9...
Page 278: Saved Level Mask Register (Slmask)
NOTE Only one copy of this register exists among the two interrupt controller modules. All reads and writes to this register must be made to the INTC0 memory space. MCF5329 Reference Manual, Rev 3 14-10 Freescale Semiconductor...
Page 279 7 interrupt is given the highest priority. If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the controller to automatically mask all interrupt requests of level-n and lower. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-11...
Page 280: Interrupt Sources
Core Watchdog Timeout Write SCMISR[CWIC] = 1 UART0 UISR0 register UART0 Interrupt Request Automatically cleared UART1 UISR1 register UART1 Interrupt Request Automatically cleared UART2 UISR2 register UART2 Interrupt Request Automatically cleared Not Used MCF5329 Reference Manual, Rev 3 14-12 Freescale Semiconductor...
Page 281 Write EIR[EBERR] = 1 EIR[BABT] Babbling transmit error Write EIR[BABT] = 1 EIR[BABR] Babbling receive error Write EIR[BABR] = 1 49–61 Not Used SCMIR[CFEI] Core bus error interrupt Write SCMIR[CFEI] = 1 Not Used MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-13...
Page 282 Write 1 to corresponding bit in the USB_STS. USB_STS USB host interrupt Write 1 to corresponding bit in the USB_STS. Host SSI_ISR SSI interrupt Various, see chapter for details. PWMSDN[IF] PWM interrupt Write PWMSDN[IF] = 1 MCF5329 Reference Manual, Rev 3 14-14 Freescale Semiconductor...
Page 283: Software And Level 1 - 7 Iack Registers (Swiackn, L1Iackn - L7Iackn)
A read from one of the global LnIACK (GLnIACK) registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt controllers. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-15...
Page 284: Functional Description
The level is fully programmable for all sources. The 3-bit level is defined in the interrupt control register (ICR0n, ICR1n). The operation of the interrupt controller can be broadly partitioned into three activities: MCF5329 Reference Manual, Rev 3 14-16 Freescale Semiconductor...
Page 285: Interrupt Prioritization
24) is returned and it is the responsibility of the service routine to manage this error situation. This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the interrupt controller completely services the acknowledge. This means the interrupt source must be MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-17...
Page 286: Prioritization Between Interrupt Controllers
7 interrupt request or an interrupt request with a priority level greater than the value programmed in WCR[PRILVL]. 5. After an appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the SCM responds by asserting the request to exit low-power mode. MCF5329 Reference Manual, Rev 3 14-18 Freescale Semiconductor...
Page 287: Initialization/Application Information
In A, an interrupt request is asserted, which is then signalled to the core. As B begins, the interrupt request is recognized, and the core begins interrupt exception processing. During the core’s exception processing, the IACK cycle performs and the interrupt controller returns the MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 14-19...
Page 288 Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a flexible, responsive system for managing interrupt requests within the device. MCF5329 Reference Manual, Rev 3 14-20 Freescale Semiconductor...
Page 289: Edge Port Module (Eport)
Figure 15-1. EPORT Block Diagram NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”) prior to configuring the edge-port module. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 15-1...
Page 290: Low-Power Mode Operation
EPORT data register (EPDR). All bits in the EPDR are set at reset. 15.4 Memory Map/Register Definition This subsection describes the memory map and register structure. Refer to Table 15-2 for a description of the EPORT memory map. MCF5329 Reference Manual, Rev 3 15-2 Freescale Semiconductor...
Page 291: Eport Pin Assignment Register (Eppar)
The EPORT pin assignment register (EPPAR) controls the function of each pin individually. Address: 0xFC09_4000 (EPPAR) Access: Supervisor read/write EPPA7 EPPA6 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1 EPPA0 Reset Figure 15-2. EPORT Pin Assignment Register (EPPAR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 15-3...
Page 292: Eport Data Direction Register (Epddr)
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear. Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output. 0 Corresponding EPORT pin configured as input 1 Corresponding EPORT pin configured as output MCF5329 Reference Manual, Rev 3 15-4 Freescale Semiconductor...
Page 293: Edge Port Interrupt Enable Register (Epier)
Reading EDPR returns the data stored in the register. Reset sets EPD7 – EPD0. 15.4.5 Edge Port Pin Data Register (EPPDR) The EPORT pin data register (EPPDR) reflects the current state of the pins. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 15-5...
Page 294: Edge Port Flag Register (Epfr)
1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register. 0 Selected edge for IRQn pin has not been detected. 1 Selected edge for IRQn pin has been detected. MCF5329 Reference Manual, Rev 3 15-6 Freescale Semiconductor...
Page 295: Enhanced Direct Memory Access (Edma)
Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 16-1. eDMA Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-1...
Page 296: Features
(TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. A major loop is the number of minor loop iterations defining a task. MCF5329 Reference Manual, Rev 3 16-2 Freescale Semiconductor...
Page 297: Debug Mode
After a service request has been initiated, it cannot be canceled. Removing a service request after it has been asserted may result in one of three actions depending on the DMA engine’s status: • The request is never recognized because another channel is executing. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-3...
Page 298: Memory Map/Register Definition
The channel priority registers assign the priorities (see Section 16.6.15, “eDMA Channel n Priority Registers (DCHPRIn)”). In round-robin arbitration mode, the channel priorities are ignored, and channels are cycled through without regard to priority. MCF5329 Reference Manual, Rev 3 16-4 Freescale Semiconductor...
Page 299: Edma Control Register (Edma_Cr)
The minor loop byte count must be a multiple of the source and destination transfer sizes. • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-5...
Page 300 Address: 0xFC04_4004 (EDMA_ES) Access: User read-only R VLD Reset ERRCHN Reset Figure 16-4. eDMA Error Status Register (EDMA_ES) MCF5329 Reference Manual, Rev 3 16-6 Freescale Semiconductor...
Page 301 1 The last recorded error was a bus error on a source read. Destination bus error. 0 No destination bus error. 1 The last recorded error was a bus error on a destination write. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-7...
Page 302: Edma Enable Request Register (Edma_Erq)
UISR1[FFULL/RXRDY] UART1 Receive UISR1[TXRDY] UART1 Transmit UISR2[FFULL/RXRDY] UART2 Receive UISR2[TXRDY] UART2 Transmit DTER0[CAP] or DTER0[REF] / Timer 0 / SSI0 Receive SSISR[RFF0] DTER1[CAP] or DTER1[REF] / Timer 1 / SSI1 Receive SSISR[RFF1] MCF5329 Reference Manual, Rev 3 16-8 Freescale Semiconductor...
Page 303: Edma Enable Error Interrupt Registers (Edma_Eei)
The EDMA_SERQ provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 304: Edma Clear Enable Request Register (Edma_Cerq)
Table 16-9. EDMA_CERQ Field Descriptions Field Description Reserved, must be cleared. Clear all enable requests. CAER 0 Clear only those EDMA_ERQ bits specified in the CERQ field. 1 Clear all bits in EDMA_ERQ. MCF5329 Reference Manual, Rev 3 16-10 Freescale Semiconductor...
Page 305: Edma Set Enable Error Interrupt Register (Edma_Seei)
EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-11...
Page 306: Edma Clear Interrupt Request Register (Edma_Cint)
Table 16-12. EDMA_CINT Field Descriptions Field Description Reserved, must be cleared. Clear all interrupt requests. CAIR 0 Clear only those EDMA_INT bits specified in the CINT field. 1 Clear all bits in EDMA_INT. MCF5329 Reference Manual, Rev 3 16-12 Freescale Semiconductor...
Page 307: Edma Clear Error Register (Edma_Cerr)
The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-13...
Page 308: Edma Clear Done Status Bit Register (Edma_Cdne)
0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field. 1 Clears all bits in TCDn_CSR[DONE] 5–4 Reserved, must be cleared. 3–0 Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE]. CDNE MCF5329 Reference Manual, Rev 3 16-14 Freescale Semiconductor...
Page 309: Edma Interrupt Request Register (Edma_Int)
A zero in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CERR is provided so the error indicator for a single channel can easily be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-15...
Page 310: Edma Channel N Priority Registers (Dchprin)
– Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. Figure 16-17. eDMA Channel n Priority Register (DCHPRIn) MCF5329 Reference Manual, Rev 3 16-16 Freescale Semiconductor...
Page 311: Transfer Control Descriptors (Tcdn)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 16-18. TCDn Source Address (TCDn_SADDR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 312 Address: 0xFC04_5006 + (0x20 × n) (TCDn_SOFF) Access: User read/write SOFF Reset — — — — — — — — — — — — — — — — Figure 16-20. TCDn Signed Source Address Offset (TCDn_SOFF) MCF5329 Reference Manual, Rev 3 16-18 Freescale Semiconductor...
Page 313 Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Figure 16-23. TCDn Destination Address (TCDn_DADDR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 314 Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. MCF5329 Reference Manual, Rev 3 16-20 Freescale Semiconductor...
Page 315 LINKCH BITER E_LINK = 0 E_LINK BITER Reset — — — — — — — — — — — — — — — — Figure 16-27. TCDn Beginning Major Iteration Count (TCDn_BITER) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-21...
Page 316 INT_ INT_ MAJOR_LINKCH DONE ACTIVE E_SG D_REQ START E_LINK HALF MAJOR Reset — — — — — — — — — — — — — Figure 16-28. TCDn Control and Status (TCDn_CSR) MCF5329 Reference Manual, Rev 3 16-22 Freescale Semiconductor...
Page 317 Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding DMAERQ bit D_REQ when the current major iteration count reaches zero. 0 The channel’s DMAERQ bit is not affected. 1 The channel’s DMAERQ bit is cleared when the major loop is complete. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-23...
Page 318: Functional Description
If the major iteration count is exhausted, additional processing are performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. MCF5329 Reference Manual, Rev 3 16-24 Freescale Semiconductor...
Page 319: Edma Basic Data Flow
The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-25...
Page 320 The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. MCF5329 Reference Manual, Rev 3 16-26 Freescale Semiconductor...
Page 321 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 16-31. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-27...
Page 322: Initialization/Application Information
4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the EDMA_ERQ. 6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware (slave device asserting its eDMA peripheral request signal). MCF5329 Reference Manual, Rev 3 16-28 Freescale Semiconductor...
Page 323 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-29...
Page 324 Current Major Loop Iteration Count (CITER) DMA Request Minor Loop DMA Request Minor Loop Major Loop DMA Request Minor Loop Table 16-33 lists the memory array terms and how the TCD settings interrelate. MCF5329 Reference Manual, Rev 3 16-30 Freescale Semiconductor...
Page 325: Dma Programming Errors
16.8.3 DMA Arbitration Mode Considerations 16.8.3.1 Fixed Channel Arbitration In this mode, the channel service request from the highest priority channel is selected to execute. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-31...
Page 326: Dma Transfer
4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. MCF5329 Reference Manual, Rev 3 16-32 Freescale Semiconductor...
Page 327 Write longword to location 0x2004 → second iteration of the minor loop. e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-33...
Page 328 MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits MCF5329 Reference Manual, Rev 3 16-34...
Page 329: Edma Tcdn Status Monitoring
TCDn_CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. The TCD status bits execute the following sequence for a hardware-activated channel: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-35...
Page 330: Channel Linking
The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major MCF5329 Reference Manual, Rev 3 16-36 Freescale Semiconductor...
Page 331: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 16.8.7.1 Dynamic Channel Linking and Dynamic Scatter/Gather Dynamic channel linking and dynamic scatter/gather is the process of changing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 16-37...
Page 332 NOTE Software must clear the TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. MCF5329 Reference Manual, Rev 3 16-38 Freescale Semiconductor...
Page 333: Flexbus
See Table 13-1 for more details. Chip-select FB_CS0 can be dedicated to boot memory access and programmed to be byte (8 bits), word MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-1...
Page 334: Features
Because this device shares the FlexBus signals with the SDRAM controller, these signals tristate between bus cycles. MCF5329 Reference Manual, Rev 3 17-2 Freescale Semiconductor...
Page 335: Chip Selects (Fb_Cs[5:0])
This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA during a write cycle, the bus cycle is terminated. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-3...
Page 336: Memory Map/Register Definition
The only applicable address ranges for which the chip-selects can be active are 0x0000_0000 – 0x3FFF_FFFF and 0xC000_0000 – 0xDFFF_FFFF. Set the CSARn registers appropriately. MCF5329 Reference Manual, Rev 3 17-4 Freescale Semiconductor...
Page 337: Chip-Select Mask Registers (Csmr0 - Csmr5)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-2. Chip-Select Mask Registers (CSMRn) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-5...
Page 338: Chip-Select Control Registers (Cscr0 - Cscr5)
Each CSCRn controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states. To support the global chip-select, FB_CS0, the CSCR0 reset values differ from the MCF5329 Reference Manual, Rev 3 17-6 Freescale Semiconductor...
Page 339 01 Assert FB_CSn on second rising clock edge after address is asserted. 10 Assert FB_CSn on third rising clock edge after address is asserted. 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-7...
Page 340 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if SBM = 0 or FB_D[7:0] if SBM = 1 1x 16-bit port size. Valid data sampled and driven on FB_D[31:16] if SBM = 0 or FB_D[15:0] if SBM = 1 MCF5329 Reference Manual, Rev 3 17-8...
Page 341: Functional Description
See Section 17.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5).” FB_CS0 is a global chip-select after reset and provides external boot memory capability. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-9...
Page 342: Data Transfer Operation
The address, write data, FB_TS, FB_CSn, and all attribute signals change on the rising edge of the FlexBus clock (FB_CLK). Read data is latched into the device on the rising edge of the clock. MCF5329 Reference Manual, Rev 3 17-10...
Page 343: Data Byte Alignment And Physical Connections
Byte 1 Memory Byte 2 Byte 3 8-Bit Port Byte 0 Memory Driven with Byte 1 address values Byte 2 Byte 3 Figure 17-5. Connections for External Memory Port Sizes (CSCRn[SBM] = 1) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-11...
Page 344: Bus Cycle Execution
The read or write cycle is initiated. On the rising clock edge, the device places a valid address on FB_A[ :0], asserts FB_TS, and drives FB_R/W high for a read and low for a write. MCF5329 Reference Manual, Rev 3 17-12 Freescale Semiconductor...
Page 345: Flexbus Timing Examples
17.4.5.1 Basic Read Bus Cycle During a read cycle, the ColdFire device receives data from memory or a peripheral device. Figure 17-7 is a read cycle flowchart. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-13...
Page 346 The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read bus cycles the address signals are indeterminate. MCF5329 Reference Manual, Rev 3 17-14 Freescale Semiconductor...
Page 347: Basic Write Bus Cycle
FlexBus asserts internal FB_TA (auto acknowledge/internal termination). 2. Latch data on FB_D[31:X]. Sample FB_TA low. Assert FB_TA (external termination). 1. Negate FB_TA (external termination). 1. Start next cycle. Figure 17-9. Write-Cycle Flowchart MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-15...
Page 348 The external device returns the read data on FB_D[31:24] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:24] ADDR[31:24] DATA[7:0] FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 17-11. Single Byte-Read Transfer MCF5329 Reference Manual, Rev 3 17-16 Freescale Semiconductor...
Page 349 FB_D[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted. FB_CLK FB_A[23:0] ADDR[23:0] ADDR[31:16] FB_D[31:16] DATA[15:0] FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 17-13. Single Word-Read Transfer MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-17...
Page 350 FB_TA Figure 17-14. Single Word-Write Transfer Figure 17-15 depicts a longword read from a 32-bit device. FB_CLK FB_A[23:0] ADDR[23:0] ADDR[31:0] FB_D[31:0] DATA[31:0] FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 17-15. Longword-Read Transfer MCF5329 Reference Manual, Rev 3 17-18 Freescale Semiconductor...
Page 351: Timing Variations
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states can give the peripheral or memory more time to return read data or sample write data. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 352 FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 17-17. Basic Read-Bus Cycle (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 17-18. Basic Write-Bus Cycle (No Wait States) MCF5329 Reference Manual, Rev 3 17-20 Freescale Semiconductor...
Page 353 The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 354 Figure 17-21. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 17-22. Write-Bus Cycle with Two Clock Address Setup (No Wait States) MCF5329 Reference Manual, Rev 3 17-22 Freescale Semiconductor...
Page 355 Figure 17-23. Read Cycle with Two-Clock Address Hold (No Wait States) FB_CLK FB_A[23:0] ADDR[23:0] FB_D[31:X] DATA ADDR[31:X] FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB_TA Figure 17-24. Write Cycle with Two-Clock Address Hold (No Wait States) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-23...
Page 356: Burst Cycles
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits. MCF5329 Reference Manual, Rev 3 17-24 Freescale Semiconductor...
Page 357 The first beat of any write burst cycle has at least one wait state. If the bus cycle is programmed for zero wait states (CSCRn[WS] = 0), one wait state is added. Otherwise, the programmed number of wait states are used. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-25...
Page 358 ADDR + 1 ADDR + 2 ADDR + 3 ADDR[23:0] ADDR FB_D[31:24] DATA DATA DATA DATA DATA [31:24] FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 17-28. Longword-Read Burst-Inhibited from 8-Bit Port (No Wait States) MCF5329 Reference Manual, Rev 3 17-26 Freescale Semiconductor...
Page 359 ADDR + 1 ADDR + 2 ADDR + 3 ADDR[23:0] FB_D[31:24] ADDR[31:24] DATA DATA DATA DATA FB_R/W FB_TS FB_CSn, FB_OE, FB_BE/BWEn FB_TA Figure 17-30. Longword-Read Burst from 8-Bit Port 3-2-2-2 (One Wait State) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-27...
Page 360 The address hold time depends on the setting of CSCRn[AA]. See Section 17.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5)”, for more details. Figure 17-32. Longword-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold) MCF5329 Reference Manual, Rev 3 17-28 Freescale Semiconductor...
Page 361 ADDR + 1 ADDR + 2 ADDR + 3 FB_D[31:24] ADDR[31:24] DATA DATA DATA DATA FB_R/W FB_TS FB_CSn, FB_OE FB_BE/BWEn FB_TA Figure 17-33. Longword-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 17-29...
Page 362: Misaligned Operands
FB_TA or by using the software watchdog timer. If the processor must manage a bus error differently, asserting an interrupt to the core along with FB_TA when the bus error occurs can invoke an interrupt handler. MCF5329 Reference Manual, Rev 3 17-30 Freescale Semiconductor...
Page 363: Sdram Controller (Sdramc)
SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus. In this chapter, the SDRAM data bus signals are named SD_D[31:0]. However, because these signals share external pins with the FlexBus, the pin names on the device are D[31:0]. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-1...
Page 364: Block Diagram
24 in 32-bit bus mode or 25 in 16-bit bus mode. • Minimum memory configuration of 8 MByte — 11 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA), 32-bit bus, one chip select MCF5329 Reference Manual, Rev 3 18-2 Freescale Semiconductor...
Page 365: Terminology
The address outputs also provide the opcode during a MODE REGISTER SET command. SD_BA[1:0] signals define which mode register is loaded during the MODE REGISTER SET (MRS). A12 is used on device densities of 256 Mb and above. Timing Assertion/Negation — Occurs synchronously with SD_CLK MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-3...
Page 366 Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK. High Impedance - Depending on the OE_RULE bit in SDCFG1, the SD_DATA bus can be in high impedance until a write occurs or only when a read occurs. MCF5329 Reference Manual, Rev 3 18-4 Freescale Semiconductor...
Page 367: Interface Recommendations
Therefore, the greatest possible address space accessed using a single chip select is 2 x 32 bit (2 x 16 bit) or 256 MBytes. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-5...
Page 368 8M x 8 bit RA11-0 BA1-0 CA7-0 13 x 8 x 4 — — — RA12 12 x 10 x 4 — — 16M x 4 bit 13 x 9 x 4 — — RA12 MCF5329 Reference Manual, Rev 3 18-6 Freescale Semiconductor...
Page 369 14 x 9 x 4 — RA13 RA12 12 x 12 x 4 CA12 CA11 64M x 8 bit 13 x 11 x 4 CA11 RA12 14 x 10 x 4 RA13 RA12 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-7...
Page 370 12 x 9 x 4 — — — — 64 Mbits RA11-0 BA1-0 CA8-0 12 x 10 x 4 — — — 16M x 4 bit 13 x 9 x 4 — — — RA12 MCF5329 Reference Manual, Rev 3 18-8 Freescale Semiconductor...
Page 371 All memory devices of a single chip-select block must have the same configuration and row/column address width; however, this is not necessary between different blocks. If mixing different memory organizations in different blocks, the following guidelines ensure that every block is fully contiguous. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-9...
Page 372: Sdram Sdr Connections
This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound trace should be routed along the data path, which should synchronize the SD_DQS so that the data is latched in the middle of the data valid window. MCF5329 Reference Manual, Rev 3 18-10 Freescale Semiconductor...
Page 373 SD_CAS SDWE A10/AP SD_A10 SD_SDR_DQS Delay SD_DQS[3:2] SD_DQM[3:0] DQM[3:0] A[15:14] BA[1:0] SD_A[23:0] A[13:11,9:0] A[13:11,9:0] SD_D[31:0] D[31:0] 3.3V Flash A[23:2] A[21:0] D[31:0] FB_CS0 DRAMSEL 3.3V Figure 18-2. Example 3.3V, 32-bit SDR SDRAM System MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-11...
Page 374: Sdram Ddr Component Connections
Figure 18-3. Example 2.5V, 16-bit DDR SDRAM System 18.3.4 DDR SDRAM Layout Considerations Due to the critical timing for DDR SDRAM, a number of considerations should be taken into account during PCB layout: • Minimize overall trace lengths. MCF5329 Reference Manual, Rev 3 18-12 Freescale Semiconductor...
Page 375: Termination Example
Address, Data Address, Data and Control and Control SD_CLK 100 Ω Note: Place 100 Ω resistor as close as possible to the DDR’s clock receiver SD_CLK Figure 18-4. DDR SDRAM Termination Circuit MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-13...
Page 376: Memory Map/Register Definition
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-5. SDRAM-Mode/Extended-Mode Register (SDMR) MCF5329 Reference Manual, Rev 3 18-14 Freescale Semiconductor...
Page 377: Sdram Control Register (Sdcr)
Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in self-refresh or power-down mode. 0 SD_CKE is negated (low) 1 SD_CKE is asserted (high) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-15...
Page 378 1 Generate a refresh command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be set before attempting to generate a software refresh command. Note: A software requested refresh is completely independent of the periodic refresh interval counter. Software refresh is only possible when MODE_EN is set. MCF5329 Reference Manual, Rev 3 18-16 Freescale Semiconductor...
Page 379: Sdram Configuration Register 1 (Sdcfg1)
SD_CLK2—double frequency of SD_CLK—DDR uses both edges of the bus-frequency clock (SD_CLK) to read/write data NOTE In all calculations for setting the fields of this register, convert time units to clock units and round up to the nearest integer. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-17...
Page 380 = 20ns and f = 99 MHz SD_CLK Suggested value = (20ns × 99 MHz) - 1= 0.98; round to 1. Note: Count value is in SD_CLK periods for SDR and DDR modes. MCF5329 Reference Manual, Rev 3 18-18 Freescale Semiconductor...
Page 381: Sdram Configuration Register 2 (Sdcfg2)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-8. SDRAM Configuration Register 2 (SDCFG2) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 382: Sdram Chip Select Configuration Registers
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18-9. SRAM Chip Select Configuration Register (SDCSn) MCF5329 Reference Manual, Rev 3 18-20...
Page 383: Sdram Commands
Functional Description 18.5.1 SDRAM Commands When an internal bus master accesses SDRAM address space, the memory controller generates the corresponding SDRAM command. Table 18-12 lists SDRAM commands supported by the memory controller. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-21...
Page 384 ACTV followed by the read command. If the address is not within the active row of an active bank, the memory controller issues a pre command to close the active MCF5329 Reference Manual, Rev 3 18-22...
Page 385 The memory controller issues the precharge command only when necessary for one of these conditions: • Access to a new row • Refresh interval elapsed • Software commanded precharge during device initialization MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-23...
Page 386 Else Reserved A6–A4 CAS latency. Delay in clocks from issuing a to valid data out. Check the SDRAM manufacturer’s spec because READ the CL settings supported can vary from memory to memory. MCF5329 Reference Manual, Rev 3 18-24 Freescale Semiconductor...
Page 387 After REF command, the SDRAM is in an idle state and waits for an command. ACTV MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-25...
Page 388: Read Clock Recovery (Rcr) Block
DDR memories. Figure 18-12 displays a simple timing diagram that illustrates the end result of the RCR delay. Memory Clock Don’t Care SD_DQSn rd_clk (internal signal) MCF5329 Reference Manual, Rev 3 18-26 Freescale Semiconductor...
Page 389: Initialization/Application Information
The SDCR[REF and IREF] bits should remain cleared for this step. 7. Initialize the SDRAM’s extended mode register to enable the DLL. See Section 18.5.1.6, “Load Mode/Extended Mode Register Command (lmr, lemr),” for instructions on issuing a LEMR command. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-27...
Page 390: Page Management
ACTV A page is kept open until one of the following conditions occurs: • An access outside the open page. • A refresh cycle is started. MCF5329 Reference Manual, Rev 3 18-28 Freescale Semiconductor...
Page 391: Transfer Size
The burst size and transfer order must be programmed in the SDRAM mode registers during initialization; the burst size also must be programmed in the memory controller (SDCFG2 register). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 18-29...
Page 392 SDRAM Controller (SDRAMC) MCF5329 Reference Manual, Rev 3 18-30 Freescale Semiconductor...
Page 393: Fast Ethernet Controller (Fec)
Figure 19-1 shows the block diagram of the FEC. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-1...
Page 394 Initialization (those internal registers not initialized by you or hardware) • High level control of the DMA channels (initiating DMA transfers) • Interpreting buffer descriptors • Address recognition for receive frames • Random number generation for transmit collision backoff timer MCF5329 Reference Manual, Rev 3 19-2 Freescale Semiconductor...
Page 395: Features
50 MHz • Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate of 50 MHz • Retransmission from transmit FIFO following a collision (no processor bus utilization) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-3...
Page 396: Modes Of Operation
The FEC supports 7-wire interface used by many 10 Mbps Ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is cleared, MII mode is disabled and the 10 Mbps 7-wire mode is enabled. MCF5329 Reference Manual, Rev 3 19-4 Freescale Semiconductor...
Page 397: Address Recognition Options
— This pin contains the serial output Ethernet data and is valid only during assertion of FEC_TXEN. FEC_TXD[3:2] — These pins contain the serial output Ethernet data and are valid only during assertion of FEC_TXEN. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-5...
Page 398: Memory Map/Register Definition
MII Management Frame Register (MMFR) Undefined 19.4.7/19-13 0xFC03_0044 MII Speed Control Register (MSCR) 0x0000_0000 19.4.8/19-15 0xFC03_0064 MIB Control/Status Register (MIBC) 0x0000_0000 19.4.9/19-16 0xFC03_0084 Receive Control Register (RCR) 0x05EE_0001 19.4.10/19-16 0xFC03_00C4 Transmit Control Register (TCR) 0x0000_0000 19.4.11/19-17 MCF5329 Reference Manual, Rev 3 19-6 Freescale Semiconductor...
Page 399: Mib Block Counters Memory Map
Table 19-4. MIB Counters Memory Map Address Register 0xFC03_0200 Count of frames not counted correctly (RMON_T_DROP) 0xFC03_0204 RMON Tx packet count (RMON_T_PACKETS) 0xFC03_0208 RMON Tx broadcast packets (RMON_T_BC_PKT) 0xFC03_020C RMON Tx multicast packets (RMON_T_MC_PKT) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-7...
Page 400 RMON Rx multicast packets (RMON_R_MC_PKT) 0xFC03_0290 RMON Rx packets with CRC/Align error (RMON_R_CRC_ALIGN) 0xFC03_0294 RMON Rx packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) 0xFC03_0298 RMON Rx packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) MCF5329 Reference Manual, Rev 3 19-8 Freescale Semiconductor...
Page 401: Ethernet Interrupt Event Register (Eir)
HBERR - IEEE_T_SQE • BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC) • BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC) • LATE_COL - IEEE_T_LCOL • COL_RETRY_LIM - IEEE_T_EXCOL • XFIFO_UN - IEEE_T_MACERR MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-9...
Page 402 FIFO controller and DMA also soft reset. Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame truncates with a bad CRC and the remainder of the frame is discarded. MCF5329 Reference Manual, Rev 3 19-10 Freescale Semiconductor...
Page 403: Interrupt Mask Register (Eimr)
When the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC polls the receive descriptor ring and processes receive frames (provided MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 404: Transmit Descriptor Active Register (Tdar)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19-5. Transmit Descriptor Active Register (TDAR) Table 19-8. TDAR Field Descriptions Field Description 31–25 Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 19-12 Freescale Semiconductor...
Page 405: Ethernet Control Register (Ecr)
0. If MSCR is cleared while MMFR is written and then MSCR is written with a non-zero value, an MII frame is generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-13...
Page 406 After the read management frame operation completes, the MII interrupt is generated. At this time, the contents of the MMFR register match MCF5329 Reference Manual, Rev 3 19-14...
Page 407: Mii Speed Control Register (Mscr)
× ----------- - Eqn. 19-1 25 MHz 2.5 MHz × A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided below. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-15...
Page 408: Mib Control Register (Mibc)
A read-only status bit. If set the MIB block is not currently updating any MIB counters. MIB_IDLE 29–0 Reserved. 19.4.10 Receive Control Register (RCR) RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN] is cleared (initialization time). MCF5329 Reference Manual, Rev 3 19-16 Freescale Semiconductor...
Page 409: Transmit Control Register (Tcr)
19.4.11 Transmit Control Register (TCR) TCR is read/write and configures the transmit block. This register is cleared at system reset. Bits 2 and 1 must be modified only when ECR[ETHER_EN] is cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-17...
Page 410: Physical Address Lower Register (Palr)
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Figure 19-12. Physical Address Lower Register (PALR) MCF5329 Reference Manual, Rev 3 19-18...
Page 411: Physical Address Upper Register (Paur)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — — Figure 19-14. Opcode/Pause Duration Register (OPD) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 412: Descriptor Individual Upper Address Register (Iaur)
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast IADDR2 address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. MCF5329 Reference Manual, Rev 3 19-20 Freescale Semiconductor...
Page 413: Descriptor Group Upper Address Register (Gaur)
FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-21...
Page 414: Fifo Receive Bound Register (Frbr)
FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive. Hardware initializes the FRSR register at reset. FRSR only needs to be written to change the default value. MCF5329 Reference Manual, Rev 3 19-22 Freescale Semiconductor...
Page 415: Receive Descriptor Ring Start Register (Erdsr)
16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit positions. This register is undefined at reset and must be initialized prior to operation. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-23...
Page 416: Receive Buffer Size Register (Emrbr)
0x7F 2032 + 15 bytes. The FEC writes up to 2047 bytes in the receive buffer. If data larger than 2047 is received, the FEC truncates it and shows 0x7FF in the receive descriptor 3–0 Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 19-24 Freescale Semiconductor...
Page 417: Functional Description
The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so the driver must provide this in one of the transmit buffers. The MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 418 RDAR register. As frames are received, the FEC fills receive buffers and updates the associated BDs, then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit MCF5329 Reference Manual, Rev 3 19-26...
Page 419 L-bit is set and the PROM bit is set. 0 The frame was received because of an address recognition hit. 1 The frame was received because of promiscuous mode. Offset + 0 Set if the DA is broadcast (FFFF_FFFF_FFFF). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-27...
Page 420 Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 19.4.1, “MIB Block Counters Memory Map,” for more details. MCF5329 Reference Manual, Rev 3 19-28 Freescale Semiconductor...
Page 421 The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 422: Initialization Sequence
The sequence is not important. Table 19-32 defines Ethernet MAC registers requiring initialization. Table 19-32. User Initialization (Before ECR[ETHER_EN]) Description Initialize EIMR Clear EIR (write 0xFFFF_FFFF) TFWR (optional) IALR / IAUR GAUR / GALR MCF5329 Reference Manual, Rev 3 19-30 Freescale Semiconductor...
Page 423: Microcontroller Initialization
Table 19-34. Microcontroller Initialization Description Initialize BackOff Random Number Seed Activate Receiver Activate Transmitter Clear Transmit FIFO Clear Receive FIFO Initialize Transmit Ring Pointer Initialize Receive Ring Pointer Initialize FIFO Count Registers MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-31...
Page 424: Network Interface Options
7-wire mode connections to the external transceiver. Table 19-36. 7-Wire Mode Configuration Signal description EMAC Pin Transmit Clock FEC_TXCLK Transmit Enable FEC_TXEN Transmit Data FEC_TXD[0] Collision FEC_COL Receive Clock FEC_RXCLK MCF5329 Reference Manual, Rev 3 19-32 Freescale Semiconductor...
Page 425: Fec Frame Transmission
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-33...
Page 426: Fec Frame Reception
FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the M, BC, MC, LG, NO, CR, OV, and TR status bits, and the frame length. See Section 19.5.15.2, “Reception Errors,” for more details. MCF5329 Reference Manual, Rev 3 19-34 Freescale Semiconductor...
Page 427: Ethernet Address Recognition
Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, the frame is accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-35...
Page 428 Set BC bit in Rcv BD if broadcast BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid PAUSE frame received Figure 19-27. Ethernet Address Recognition—Receive Block Decisions MCF5329 Reference Manual, Rev 3 19-36 Freescale Semiconductor...
Page 429: 19.5.10 Hash Algorithm
The effectiveness of the hash table declines as the number of addresses increases. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-37...
Page 430 DBFF_FFFF_FFFF FBFF_FFFF_FFFF BBFF_FFFF_FFFF 8BFF_FFFF_FFFF 0BFF_FFFF_FFFF 3BFF_FFFF_FFFF 7BFF_FFFF_FFFF 5BFF_FFFF_FFFF 27FF_FFFF_FFFF 0x10 07FF_FFFF_FFFF 0x11 57FF_FFFF_FFFF 0x12 77FF_FFFF_FFFF 0x13 F7FF_FFFF_FFFF 0x14 C7FF_FFFF_FFFF 0x15 97FF_FFFF_FFFF 0x16 A7FF_FFFF_FFFF 0x17 99FF_FFFF_FFFF 0x18 B9FF_FFFF_FFFF 0x19 F9FF_FFFF_FFFF 0x1A C9FF_FFFF_FFFF 0x1B MCF5329 Reference Manual, Rev 3 19-38 Freescale Semiconductor...
Page 431 BFFF_FFFF_FFFF 0x2C 9FFF_FFFF_FFFF 0x2D DFFF_FFFF_FFFF 0x2E EFFF_FFFF_FFFF 0x2F 93FF_FFFF_FFFF 0x30 B3FF_FFFF_FFFF 0x31 F3FF_FFFF_FFFF 0x32 D3FF_FFFF_FFFF 0x33 53FF_FFFF_FFFF 0x34 73FF_FFFF_FFFF 0x35 23FF_FFFF_FFFF 0x36 13FF_FFFF_FFFF 0x37 3DFF_FFFF_FFFF 0x38 0DFF_FFFF_FFFF 0x39 5DFF_FFFF_FFFF 0x3A 7DFF_FFFF_FFFF 0x3B MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-39...
Page 432: 19.5.11 Full Duplex Flow Control
EIR[GRA] (graceful stop complete) interrupt asserts and the pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally. You must specify the desired pause duration in the OPD register. MCF5329 Reference Manual, Rev 3 19-40 Freescale Semiconductor...
Page 433: 19.5.12 Inter-Packet Gap (Ipg) Time
For external loopback, clear RCR[LOOP] and RCR[DRT], and configure the external transceiver for loopback. 19.5.15 Ethernet Error-Managing Procedure The Ethernet controller reports frame reception and transmission error conditions using the MIB block counters, the FEC RxBDs, and the EIR register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-41...
Page 434 Dribbling bits are not used in the CRC calculation. If there is a CRC error, the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, no error is reported. MCF5329 Reference Manual, Rev 3 19-42...
Page 435 When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBD[LG] is set. The frame is not truncated unless the frame length exceeds 2047 bytes. 19.5.15.2.5 Truncation When the receive frame length exceeds 2047 bytes, frame is truncated and RxBD[TR] is set. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 19-43...
Page 436 Fast Ethernet Controller (FEC) MCF5329 Reference Manual, Rev 3 19-44 Freescale Semiconductor...
Page 437: Universal Serial Bus Interface - Host Module
This USB host controller hides all direct interaction with the protocol, but some knowledge of the USB is required to properly configure the device for operation on the local bus and on the USB. This document covers programming requirements, and additional information may be found in the USB specification. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 20-1...
Page 438: Block Diagram
20.1.3 Features The USB host module includes the following features: • Complies with USB specification revision 2.0 • Supports operation as a standalone USB host controller MCF5329 Reference Manual, Rev 3 20-2 Freescale Semiconductor...
Page 439: Modes Of Operation
Doze — The processor stops the system clocks to the USB host module. However, the 60 Mhz transceiver clock remains active. Detection of resume signaling initiates a restart of the module clocks. 20.2 External Signal Description Table 20-1 describes the external signals of the USB host module. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 20-3...
Page 440: Usb Host Control And Status Signals
Table 20-2. Internal Control and Status Bits for USB Host Module Interrupt Signal Mnemonic Direction Access Trigger? Port Indicator LED Selects LED color for product PORTIND[1:0] Control package. Wake-up Event Reflects when a wake-up event has WKUP occurred on the USB bus. MCF5329 Reference Manual, Rev 3 20-4 Freescale Semiconductor...
Page 441: Memory Map/Register Definitions
USB Interrupt Enable (USBINTR) R/W 0x0000_0000 21.3.3.3/21-21 0xFC0B_414C USB Frame Index (FRINDEX) R/W 0x0000_0000 21.3.3.4/21-23 0xFC0B_4154 Periodic Frame List Base Address (PERIODICLISTBASE) R/W 0x0000_0000 21.3.3.5/21-24 0xFC0B_4158 Current Asynchronous List Address (ASYNCLISTADDR) R/W 0x0000_0000 21.3.3.7/21-25 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 20-5...
Page 442: Functional Description
The USB host module’s functional description is very similar to the USB OTG module in host mode. See Chapter 21, “Universal Serial Bus Interface – On-The-Go Module,” and the Enhanced Host Controller Interface (EHCI) Specification for Universal Serial Bus, Revision 1.0 for more information. MCF5329 Reference Manual, Rev 3 20-6 Freescale Semiconductor...
Page 443: Universal Serial Bus Interface - On-The-Go Module
USB OTG standard provides a minimum 8 mA VBUS supply requirement. Optionally, the OTG module may supply up to 500 mA to the USB-connected devices. If the connected device attempts MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-1...
Page 444: Block Diagram
12-pin digital interface. The board-level implementation of a ULPI based product is dependent on the PHY vendor. One possible implementation is shown in Figure 21-1. The ULPI PHY manages USB clocking, DP/DM bias resistors, MCF5329 Reference Manual, Rev 3 21-2 Freescale Semiconductor...
Page 445: Features
— Supports full-speed operation via the on-chip transceiver. — Supports full-speed/high-speed operation via an external ULPI transceiver. — Supports one upstream facing port. — Supports four programmable, bidirectional USB endpoints, including endpoint 0. See endpoint configurations: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-3...
Page 446: Modes Of Operation
• USB enabled. In this mode, the USB host’s datapath is enabled to accept transactions received on the USB interface. • USB enabled, low-power modes. See Section 21.1.4.1, “Low-Power Modes,” for details. MCF5329 Reference Manual, Rev 3 21-4 Freescale Semiconductor...
Page 447: External Signal Description
USBOTG_PU_EN O Enables an external pull-up on the USBOTG_DP line. This signal is controlled by the UOCSR[BVLD] bit. State Asserted—Pull-up enabled. UOCSR[BVLD] set. Meaning Negated—Pull-up disabled. UOCSR[BVLD] cleared. Timing Asynchronous ULPI Interface MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-5...
Page 448: Usb Otg Control And Status Signals
Writes to the UOCSR register from the firmware set the corresponding bits on the USB interface. • When the USB OTG module outputs change, the corresponding bits on the UOCSR register are updated, and a maskable interrupt is generated. MCF5329 Reference Manual, Rev 3 21-6 Freescale Semiconductor...
Page 449 When this bit is 0, the interrupt is masked. On-chip Transceiver XPDE Enables the on-chip 50 kΩ Pull-down Enable pull-downs on the OTG controller’s DM and DP pins when the on-chip transceiver is used. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-7...
Page 450: Memory Map/Register Definition
R/W 0x0000_0000 21.3.3.8/21-26 0xFC0B_015C Host TT Asynchronous Buffer Control (TTCTRL) R/W 0x0000_0000 21.3.3.9/21-26 0xFC0B_0160 Master Interface Data Burst Size (BURSTSIZE) R/W 0x0000_0404 21.3.3.10/21-27 0xFC0B_0164 Host Transmit FIFO Tuning Control (TXFILLTUNING) R/W 0x0000_0000 21.3.3.11/21-27 MCF5329 Reference Manual, Rev 3 21-8 Freescale Semiconductor...
Page 451: Module Identification Registers
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 Figure 21-3. Identification Register (ID) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 452 USB OTG module in UTMI mode. Always reads 00. 00 8-bit data bus (60 MHz) Reserved, always cleared. 2–1 Reserved. For the USB OTG module, always 10; for the USB host module, always 01. Reserved, always set. MCF5329 Reference Manual, Rev 3 21-10 Freescale Semiconductor...
Page 453 Figure 21-6. Device Hardware Parameters Register (HWDEVICE) Table 21-8. HWDEVICE Field Descriptions Field Description 31–6 Reserved, always cleared. 5–1 Device endpoints. The number of supported endpoints. Always 0x04. DEVEP Indicates the OTG module is device capable. Always set. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-11...
Page 454 Receive address. The number of address bits for the entire RX buffer. Always 0x04. RXADD 7–0 Receive burst. Indicates the number of data beats in a burst for receive DMA data transfers. Always 0x04. RXBURST MCF5329 Reference Manual, Rev 3 21-12 Freescale Semiconductor...
Page 455: Capability Registers
USBCMD register. Address: 0xFC0B_0103 (CAPLENGTH) Access: User read-only CAPLENGTH Reset: Figure 21-10. Capability Registers Length Register (CAPLENGTH) Table 21-12. CAPLENGTH Field Descriptions Field Description 7–0 Capability registers length. Always 0x40. CAPLENGTH MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-13...
Page 456 Number of ports. Indicates number of physical downstream ports implemented for host applications. Field value N_PORTS determines how many addressable port registers in the operational register. For the USB host and OTG modules, this is always 0x1. MCF5329 Reference Manual, Rev 3 21-14 Freescale Semiconductor...
Page 457 The most-significant byte of the register represents a major revision and the least-significant byte is the minor revision. Address: 0xFC0B_0120 (DCIVERSION) Access: User read-only DCIVERSION Reset Figure 21-13. Device Controller Interface Version Register (DCIVERSION) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-15...
Page 458: Operational Registers
4–0 Device endpoint number. This field indicates the number of endpoints built into the device controller. Always 0x04. 21.3.3 Operational Registers Comprised of dynamic control or status registers and are defined below. MCF5329 Reference Manual, Rev 3 21-16 Freescale Semiconductor...
Page 459 Reserved, must be cleared. Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode. ASPE 1 Park mode enabled 0 Park mode disabled Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-17...
Page 460 001 512 elements (2048 bytes) 010 256 elements (1024 bytes) 011 128 elements (512 bytes) 100 64 elements (256 bytes) 101 32 elements (128 bytes) 110 16 elements (64 bytes) 111 8 elements (32 bytes) MCF5329 Reference Manual, Rev 3 21-18 Freescale Semiconductor...
Page 461 Software clears certain bits in this register by writing a 1 to them. Address: 0xFC0B_0144 (USBSTS) Access: User read/write NAKI Reset ULPII Reset Figure 21-16. USB Status Register (USBSTS) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-19...
Page 462 FS mode and every 125 μsec in HS mode, and it is synchronized to the actual SOF received. Because the controller is initialized to FS before connect, this bit is set at an interval of 1 ms during the prelude to the connect and chirp. MCF5329 Reference Manual, Rev 3 21-20 Freescale Semiconductor...
Page 463 The interrupts to software are enabled with this register. An interrupt generates when a bit is set and the corresponding interrupt is active. The USB status register (USBSTS) continues to show interrupt sources (even if the USBINTR register disables them), allowing polling of interrupt events by the software. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-21...
Page 464 0 Disabled 1 Enabled System error enable. When this bit and the USBSTS[SEI] bit are set, controller issues an interrupt. Software clearing the USBSTS[SEI] bit acknowledges the interrupt. 0 Disabled 1 Enabled MCF5329 Reference Manual, Rev 3 21-22 Freescale Semiconductor...
Page 465 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-18. Frame Index Register (FRINDEX) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 466 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-19. Periodic Frame List Base Address Register (PERIODICLISTBASE) MCF5329 Reference Manual, Rev 3 21-24...
Page 467 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-21. Current Asynchronous List Address Register (ASYNCLISTADDR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 468 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-23. Host TT Asynchronous Buffer Control (TTCTRL) MCF5329 Reference Manual, Rev 3 21-26...
Page 469 = Time to send data payload = Total packet flight time (send-only) packet (T = Time to fetch packet into TX FIFO up to specified level = Total packet time (fetch and send) packet (T MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-27...
Page 470 This value is ignored if the USBMODE[SDIS] bit is set. When the USBMODE[SDIS] bit is set, the host controller behaves as if TXFIFOTHRES is set to its maximum value. 15–13 Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 21-28 Freescale Semiconductor...
Page 471 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-26. ULPI Register Access (ULPI VIEWPORT) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-29...
Page 472 The polling method above can be replaced with interrupts using the ULPI interrupt defined in the USBSTS and USBINTR registers. When a wake-up or read/write operation completes, the ULPI interrupt is set. MCF5329 Reference Manual, Rev 3 21-30 Freescale Semiconductor...
Page 473 PHY into low-power suspend mode and disable the PHY clock. Address: 0xFC0B_0184 (PORTSC1) Access: User read/write PSPD PFSC PHCD WKOC WKDS WLCN Reset SUSP Reset Figure 21-28. Port Status and Control Register (PORTSC1) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-31...
Page 474 WLCN This field is 0 if the PP bit is cleared or the module is in device mode (USB OTG-only). In host mode, this can work with an external power control circuit. MCF5329 Reference Manual, Rev 3 21-32 Freescale Semiconductor...
Page 475 Device mode (USB OTG only): This bit is a read-only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 0 Port is not in reset. 1 Port is in reset. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-33...
Page 476 USBn_PWRFAULT signal for this condition. For device-only implementations (USB OTG only), this bit must always be cleared. 0 Port not in over-current condition. 1 Port currently in over-current condition. MCF5329 Reference Manual, Rev 3 21-34 Freescale Semiconductor...
Page 477 The status inputs de-bounce using a 1 ms time constant. Values on the status inputs that do not persist for more than 1 ms do not cause an update of the status inputs or an OTG interrupt. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 478 1 millisecond timer interrupt status. This bit is set once every millisecond. Software must write a 1 to clear this bit. 1MSS B session end interrupt status. Indicates when VBUS falls below the B session end threshold. Software must write BSEIS a 1 to clear this bit. MCF5329 Reference Manual, Rev 3 21-36 Freescale Semiconductor...
Page 479 1 The pull-up on DP is asserted for data pulsing during SRP. OTG Termination. This bit must be set with the OTG module in device mode. 0 Disable pull-down on DM. 1 Enable pull-down on DM. Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-37...
Page 480 Setup lockout mode. For the module in device mode, this bit controls behavior of the setup lock mechanism. See SLOM Section 21.5.3.4.4, “Control Endpoint Operation.” 0 Setup lockouts on. 1 Setup lockouts off (software requires use of the USBCMD[SUTW] bit). MCF5329 Reference Manual, Rev 3 21-38 Freescale Semiconductor...
Page 481 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21-32. Endpoint Initialization Register (EPPRIME) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 482 FERB[3] corresponds to endpoint 3. 21.3.3.20 Endpoint Status Register (EPSR) This register is not defined in the EHCI specification. This register is only used by the USB OTG module in device mode. MCF5329 Reference Manual, Rev 3 21-40 Freescale Semiconductor...
Page 483 If the corresponding IOC bit is set in the transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this register. ETCE[3] (bit 19) corresponds to endpoint 3. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-41...
Page 484 Reserved, must be cleared. RX endpoint enable. Endpoint zero is always enabled. 1 Enabled. 6–4 Reserved, must be cleared. 3–2 RX endpoint type. Endpoint zero is always a control endpoint. 00 Control MCF5329 Reference Manual, Rev 3 21-42 Freescale Semiconductor...
Page 485 TX data toggle inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit causes this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. 0 PID sequencing enabled. 1 PID sequencing disabled. Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-43...
Page 486 Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues returning STALL until software clears this bit or automatically clears as above, 0 Endpoint OK 1 Endpoint stalled MCF5329 Reference Manual, Rev 3 21-44 Freescale Semiconductor...
Page 487: Functional Description
LS. The USB OTG module may interface to any ULPI compatible PHY as well. Due to pin-count limitations the USB modules only support certain combinations of PHY interfaces and USB functionality. Refer to the Table 21-41 for more information. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-45...
Page 488: Initialization/Application Information
Host Controller Initialization After initial power-on or module reset (via the USBCMD[RST] bit), all of the operational registers are at default values, as illustrated in the register memory map in Table 21-4. MCF5329 Reference Manual, Rev 3 21-46 Freescale Semiconductor...
Page 489: Device Data Structures
21-38, there are two endpoint queue heads in the array for each device endpoint—one for IN and one for OUT. The EPLISTADDR provides a pointer to the first entry in the array. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-47...
Page 490 While a packet is in progress, the overlay area of the dQH acts as a staging area for the dTD so the device controller can access needed information with minimal latency. Figure 21-39 shows the endpoint queue head structure. MCF5329 Reference Manual, Rev 3 21-48 Freescale Semiconductor...
Page 491 01 Execute 1 Transaction. 10 Execute 2 Transactions. 11 Execute 3 Transactions. Note: Non-ISO endpoints must set Mult equal to 00. ISO endpoints must set Mult equal to 01, 10, or 11 as needed. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-49...
Page 492 Until a transfer expires, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller writes the results back to the original transfer descriptor and advance the queue. MCF5329 Reference Manual, Rev 3 21-50 Freescale Semiconductor...
Page 493 Figure 21-40. Endpoint Transfer Descriptor (dTD) 21.5.2.2.1 Next dTD Pointer (Offset = 0x0) The next dTD pointer is used to point the device controller to the next dTD in the linked list. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-51...
Page 494 For OUT transfers the total bytes must be evenly divisible by the maximum packet length. Interrupt on complete. Indicates if USBSTS[UI] is set in response to device controller finished with this dTD. 14–12 Reserved. Reserved for future use and must be cleared. MCF5329 Reference Manual, Rev 3 21-52 Freescale Semiconductor...
Page 495 Current Offset 1;10–0 Frame Number. Written by the device controller to indicate the frame number a packet finishes in. Typically Frame Number correlates relative completion times of packets on an ISO endpoint. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-53...
Page 496: Device Operation
It is not necessary to initially prime endpoint 0 because the first packet received is always a setup packet. The contents of the first setup packet requires a response in accordance with USB device framework command set. MCF5329 Reference Manual, Rev 3 21-54 Freescale Semiconductor...
Page 497 Bus Activity Software-only state Figure 21-41. USB 2.0 Device States States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB OTG, and they are communicated to the DCD using these status bits: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-55...
Page 498 DCD processes a USB reset event, it is likely w3a4no dTDs have been allocated. 6. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a port change detect is indicated. MCF5329 Reference Manual, Rev 3 21-56 Freescale Semiconductor...
Page 499 (one more devices) back to the active condition. NOTE Before use of resume signaling, the host must enable it by using the set feature command defined in chapter 9 Device Framework of the USB 2.0 specification. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-57...
Page 500 1 Synchronize the data PIDs Data Toggle Inhibit (TXI, RXI) 0 PID sequencing disabled Endpoint Type (TXT, RXT) 00 Control 01 Isochronous 10 Bulk 11 Interrupt Endpoint Stall (TXS, RXS) 0 Not stalled MCF5329 Reference Manual, Rev 3 21-58 Freescale Semiconductor...
Page 501 The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by setting the data toggle reset bit in the EPCRn register. This should only happen when configuring/initializing an endpoint or returning from a STALL condition. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-59...
Page 502 After a priming request is complete, an endpoint state of primed is indicated in the EPSR register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of high-speed USB. MCF5329 Reference Manual, Rev 3 21-60 Freescale Semiconductor...
Page 503 Table 21-52. Variable Length Transfer Protocol Example (ZLT=1) Bytes Max. Packet (dTD) Length (dQH) — — — — NOTE The MULT field in the dQH must be set to 00 for bulk, interrupt, and control endpoints. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-61...
Page 504 Table 21-53. Interrupt/Bulk Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed Ignore Ignore Ignore Setup STALL Transmit BS Error STALL Receive + NYET/ACK STALL Ping Ignore Ignore Ignore Ignore Ignore Invalid Force bit stuff error MCF5329 Reference Manual, Rev 3 21-62 Freescale Semiconductor...
Page 505 If a new setup packet is indicated after the EPPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must re-interpret the setup packet. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-63...
Page 506 Isochronous endpoints used for real-time scheduled delivery of data, and their operational model is significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by the USB OTG is accomplished by: • Exactly MULT packets per (micro)frame are transmitted/received. MCF5329 Reference Manual, Rev 3 21-64 Freescale Semiconductor...
Page 507 • TX packet retired: — MULT counter reaches zero. — Fulfillment error (transaction error bit is set): – # packets occurred > 0 AND # packets occurred < MULT MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-65...
Page 508 SOF for packet N is received. Isochronous Endpoint Bus Response Matrix Table 21-55. Isochronous Endpoint Bus Response Matrix Token Stall Primed Underflow Overflow Type Primed STALL STALL STALL Setup NULL NULL Transmit BS Error Packet Packet MCF5329 Reference Manual, Rev 3 21-66 Freescale Semiconductor...
Page 509 The next section includes demonstration of complete initialization of the dQH including these fields. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-67...
Page 510 4. Decoding setup packet and prepare data phase (optional) and status phase transfer as required by the USB specification chapter 9 or application specific protocol. MCF5329 Reference Manual, Rev 3 21-68 Freescale Semiconductor...
Page 511 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointers. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-69...
Page 512 Active = 0, Halted = 0, Transaction error = 0, Data buffer error = 0 Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in Section 21.5.3.6.6, “Device Error Matrix.” MCF5329 Reference Manual, Rev 3 21-70 Freescale Semiconductor...
Page 513 ISO Fulfillment Error Both The device controller manages all errors on bulk/control/interrupt endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-71...
Page 514: Servicing Interrupts
Table 21-59. Low Frequency Interrupt Events Interrupt Action Port Change Change software state information. Sleep Enable (Suspend) Change software state information. Low power managing as necessary. Reset Received Change software state information. Abort pending transfers. MCF5329 Reference Manual, Rev 3 21-72 Freescale Semiconductor...
Page 515: Deviations From The Ehci Specifications
These additions to the capability registers support the embedded Transaction translator function: • N_TT added to HSCPARAMS - Host Controller Structural Parameters • N_PTT added to HSCPARAMS - Host Controller Structural Parameters MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-73...
Page 516 It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS/LS devices and hubs: 1. QH (for direct attach FS/LS) – asynchronous (bulk/control endpoints) periodic (interrupt) • Hub address equals 0 • Transactions to direct attached device/hub. MCF5329 Reference Manual, Rev 3 21-74 Freescale Semiconductor...
Page 517 H-frame and B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start of B-frame 0.) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-75...
Page 518 – Idle for more than 4 microframes — Abort of pending complete-splits – EOF – Idle for more than 4 microframes • USB 2.0 - 11.18.[7-8] — Transaction tracking for up to 4 data pipes. MCF5329 Reference Manual, Rev 3 21-76 Freescale Semiconductor...
Page 519 Starts of microframes are timed precisely to 125 µs using the transceiver clock as a reference clock or a 60 Mhz transceiver clock for 8-bit physical interfaces and full-speed serial interfaces. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 21-77...
Page 520 A 1-bit high-speed indicator bit has been added to PORTSCn to signify that the port is in HS vs. FS/LS. — This information is redundant with the 2-bit port speed indicator field above. MCF5329 Reference Manual, Rev 3 21-78 Freescale Semiconductor...
Page 521: Introduction
CSTN To Panel Figure 22-1. LCDC Block Diagram 22.1.2 Features The LCDC provides the following features: • Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-1...
Page 522 Logical operation between color hardware cursor and background • Hardware panning (soft horizontal scrolling) • 8-bit pulse-width modulator for software contrast control • Graphic window support for viewfinder function in color display MCF5329 Reference Manual, Rev 3 22-2 Freescale Semiconductor...
Page 523: External Signal Description
0xFC0A_C000 Screen Start Address Register (LCD_SSAR) 0x0000_0000 22.3.1/22-5 0xFC0A_C004 LCD Size Register (LCD_SR) 0x0000_0000 22.3.2/22-5 0xFC0A_C008 LCD Virtual Page Width Register (LCD_VPW) 0x0000_0000 22.3.3/22-5 0xFC0A_C00C LCD Cursor Position Register (LCD_CPR) 0x0000_0000 22.3.4/22-6 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-3...
Page 524 0xFC0A_C064 LCD Graphic Window Control Register (LCD_GWCR) 0x0000_0000 22.3.23/22-24 0xFC0A_C068 LCD Graphic Window DMA Control Register 0x8010_0004 22.3.24/22-26 (LCD_GWDCR) 0xFC0A_C800 Background Look-up Table (BGLUT) — 22.3.25/22-26 0xFC0A_CBFC 0xFC0A_CC00 Graphic Window Look-up Table (GWLUT) — 22.3.25/22-26 0xFC0A_CFFC MCF5329 Reference Manual, Rev 3 22-4 Freescale Semiconductor...
Page 525: Lcdc Screen Start Address Register (Lcd_Ssar)
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x258. 22.3.3 LCDC Virtual Page Width Register (LCD_VPW) The virtual page width register defines the width of the virtual page for the LCD panel. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-5...
Page 526: Lcdc Cursor Position Register (Lcd_Cpr)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-5. LCD Cursor Position Register (LCD_CPR) MCF5329 Reference Manual, Rev 3 22-6...
Page 527: Lcdc Cursor Width Height And Blink Register (Lcd_Cwhb)
0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Figure 22-6. LCD Cursor Width Height and Blink Register (LCD_CWHB) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 528: Lcdc Color Cursor Mapping Register (Lcd_Ccmr)
Table 22-9. LCD_CCMR Field Descriptions Field Description 30–18 Reserved, must be cleared. 17–12 Cursor red field. Defines the red component of the cursor color in color mode. CUR_COL_R 0x00 No red. 0x3F Full red. MCF5329 Reference Manual, Rev 3 22-8 Freescale Semiconductor...
Page 529: Lcdc Panel Configuration Register (Lcd_Pcr)
The panel configuration register defines all of the properties of the LCD screen. Address: 0xFC0A_C018 (LCD_PCR) Access: User read/write SCLK END_ SWAP_ REV_ PBSIZ BPIX IDLE Reset R ACD SCLK SHARP Reset Figure 22-8. LCD Panel Configuration Register (LCD_PCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-9...
Page 530 SWAP_SEL = 1. Pixel polarity. PIXPOL 0 Active high 1 Active low First line marker polarity. FLMPOL 0 Active high 1 Active low Line pulse polarity. LPPOL 0 Active high 1 Active low MCF5329 Reference Manual, Rev 3 22-10 Freescale Semiconductor...
Page 531 Note: Set PCD so that the LCD_LSCLK frequency is less than one-third (TFT mode) or one-fourth (CSTN mode) of the system bus clock (f ) frequency. Otherwise, the line data (LCD_D) is incorrect. sys/3 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-11...
Page 532: Lcdc Horizontal Configuration Register (Lcd_Hcr)
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-10. LCD Vertical Configuration Register (LCD_VCR) MCF5329 Reference Manual, Rev 3 22-12...
Page 533: Lcdc Panning Offset Register (Lcd_Por)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-11. LCD Panning Offset Register (LCD_POR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 534: Lcdc Sharp Configuration Register (Lcd_Scr)
LCD_PS rise delay. Controls the delay of the rising edge of LCD_PS relative to the falling edge of LCD_CLS. PS_RISE_ Total delay time is equal to PS_RISE_DELAY LCD_LSCLK periods. DELAY 0x00 Zero LCD_LSCLK periods 0x3F 63 LCD_LSCLK periods 25–24 Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 22-14 Freescale Semiconductor...
Page 535 The rising edge delay of LCD_PS is programmed by PS_RISE_DELAY CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of LCD_LSCLK. LCD_SPL_SPR pulse width is fixed and aligned to the first data of the line. Figure 22-13. Horizontal Timing MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-15...
Page 536: Lcdc Pwm Contrast Control Register (Lcd_Pccr)
There is a 32 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA control register controls the DMA burst length and when to trigger a DMA burst in terms of the number of data bytes left in the pixel buffer. MCF5329 Reference Manual, Rev 3 22-16 Freescale Semiconductor...
Page 537: Lcdc Refresh Mode Control Register (Lcd_Rmcr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-16. LCD Refresh Mode Control Register (LCD_RMCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 538: Lcdc Interrupt Configuration Register (Lcd_Icr)
0 Interrupt flag is set when the end of a graphic window is reached 1 Interrupt flag is set when the beginning of a graphic window is reached Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 22-18 Freescale Semiconductor...
Page 539: Lcdc Interrupt Enable Register (Lcd_Ier)
When the interrupt is masked, the LCDC does not generate the interrupt request, but its status can be observed in the interrupt status register. Address: 0xFC0A_C03C (LCD_IER) Access: User read/write Reset Reset Figure 22-18. LCD Interrupt Endable Register (LCD_IER) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-19...
Page 540: Lcdc Interrupt Status Register (Lcd_Isr)
If any bit in this register is set and the corresponding bit in the LCD_IER register is set, an LCD interrupt is asserted to the interrupt controller. The status bit is cleared by reading the register. MCF5329 Reference Manual, Rev 3 22-20 Freescale Semiconductor...
Page 541 Error response interrupt. Indicates whether the LCDC has issued a read data request and has received a bus error. It is cleared by reading the status register, at power on reset, or when the LCDC is disabled. 0 Interrupt has not occurred. 1 Interrupt has occurred. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-21...
Page 542: Lcdc Graphic Window Start Address Register (Lcd_Gwsar)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-21. LCD Graphic Window Size Register (LCD_GWSR) MCF5329 Reference Manual, Rev 3 22-22...
Page 543: Lcdc Graphic Window Virtual Page Width Register (Lcd_Gwvpw)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22-23. LCD Graphic Window Panning Offset Register (LCD_GWPOR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 544: Lcdc Graphic Window Position Register (Lcd_Gwpr)
Graphic window Y-position. Represents the graphic window’s vertical starting position in lines (from 0 to YMAX). GWYP 22.3.23 LCDC Graphic Window Control Register (LCD_GWCR) The LCD graphic window control register defines various aspects of the graphic window. MCF5329 Reference Manual, Rev 3 22-24 Freescale Semiconductor...
Page 545 GWCKG 0x00 No green … 0x3F Full green 5–0 Graphic window color keying blue component. Defines the blue component of graphic window color keying. GWCKB 0x00 No blue … 0x3F Full blue MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-25...
Page 546: Lcdc Graphic Window Dma Control Register (Lcd_Gwdcr)
Unimplemented bits are read as 0. All read and write data use the least significant 12 or 18 bits. NOTE Byte or word access to the RAM corrupts its contents. MCF5329 Reference Manual, Rev 3 22-26 Freescale Semiconductor...
Page 547 Red level (color display). Represents the red component level in the color. 7–4 Green level (color display). Represents the green component level in the color. 3–0 Blue level (color display). Represents the blue component level in the color. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-27...
Page 548 256 colors can be selected out of a palette of 256K. All 256 mapping RAM entries must be written to define the codes for the 256 available combinations. MCF5329 Reference Manual, Rev 3 22-28...
Page 549: Functional Description
The maximum page width is specified by the virtual page width (VPW) parameter. Virtual page height (VPH) does not affect the LCDC and is limited only by memory size. By changing the SSA register, a MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 550: Graphic Window On Screen
One of the applications can be a graphical hardware cursor. NOTE The graphic window and background images must have the same bpp setting. MCF5329 Reference Manual, Rev 3 22-30 Freescale Semiconductor...
Page 551: Panning
4 bits unused. In 18 bpp mode, 32 bits of memory are used for each pixel, leaving 14 bits unused. Refer to Figure 22-30 Figure 22-31. LCD Screen Figure 22-29. Pixel Location on Display Screen MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-31...
Page 552 Bit 26 Bit 25 Bit 24 Red1 [4] Red1 [3] Red1 [2] Red1 [1] Red1 [0] Green1 [5] Green1 [4] Green1 [3] Figure 22-30. Display Data Mapping 1 bpp Through 16 bpp Modes MCF5329 Reference Manual, Rev 3 22-32 Freescale Semiconductor...
Page 553: Black-And-White Operation
0, 5/16, 11/16 and 1 for certain graphics. Figure 22-32 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to optimize the visual effect for a specific panel or application. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-33...
Page 554: Color Generation
For 12-, 16- and 18-bit active matrix color display, pixel data is simply moved from display memory to the LCDC output bus. Figure 22-33 Figure 22-34 illustrate passive matrix and active matrix color pixel generation. MCF5329 Reference Manual, Rev 3 22-34 Freescale Semiconductor...
Page 555 1 1 0 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 12 bpp Data Color Inside LCDC 256 rows To panel Figure 22-33. Passive Matrix Color Pixel Generation MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-35...
Page 556: Frame Rate Modulation Control (Frc)
The LCDC can generate 16 simultaneous gray-scale levels. Table 22-33. Gray Palette Density Gray Code Density Density (Hexadecimal) (Decimal) 0.125 0.25 0.333 0.444 0.555 0.666 0.75 MCF5329 Reference Manual, Rev 3 22-36 Freescale Semiconductor...
Page 557: Panel Interface Signals And Timing
(LCD_PCR). The data bus timing for passive panels is determined by the shift clock (LCD_LSCLK), line pulse (LCD_LP), first line marker (LCD_FLM), alternate crystal direction (LCD_ACD), and line data (LCD_D) signals. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-37...
Page 558 [0,9] [0,233] [0,237] [0,m-7] [0,m-3] LCD_D2 [0,2] [0,6] [0,10] [0,234] [0,238] [0,m-6] [0,m-2] LCD_D3 [0,7] [0,11] [0,235] [0,239] [0,m-5] [0,m-1] [0,3] Figure 22-36. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels MCF5329 Reference Manual, Rev 3 22-38 Freescale Semiconductor...
Page 559 H_WAIT_2 defines the delay from the end of LCD_LP to the beginning of data output. NOTE ⎛ ⎞ LCD_PCR[PCD] All parameters are defined in unit of pixel clock period -------------------------------------------------- - ⎝ ⎠ sys/3 unless stated otherwise. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-39...
Page 560: Bpp Mode Color Stn Panel
1. LCD_LSCLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, LCD_LSCLK runs continuously. 2. LCD_HSYNC causes the panel to start a new line. MCF5329 Reference Manual, Rev 3 22-40 Freescale Semiconductor...
Page 561 22-34. The unused bits are fixed at 0. Table 22-34. TFT Color Channel Assignments LCD_D[17:0] 4 bpp 8 bpp – – – – – – 12 bpp – – 16 bpp 18 bpp MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-41...
Page 562 H_WAIT_2 defines the delay from the end of LCD_HSYNC to the beginning of the LCD_OE pulse. • H_WAIT_1 defines the delay from end of LCD_OE to the beginning of the LCD_HSYNC pulse. • XMAX defines the (total) number of pixels per line. MCF5329 Reference Manual, Rev 3 22-42 Freescale Semiconductor...
Page 563 (time = one line period) after LCD_VSYNC. The LCD_HSYNC pulse is output during the V_WAIT_2 delay. End of frame V_WIDTH Beginning of frame (lines) YMAX LCD_VSYNC LCD_HSYNC LCD_OE V_WAIT_1 V_WAIT_2 Figure 22-42. Vertical Sync Pulse Timing TFT Mode MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 22-43...
Page 564 Liquid Crystal Display Controller (LCDC) MCF5329 Reference Manual, Rev 3 22-44 Freescale Semiconductor...
Page 565: Introduction
• • CANRX [0:15] • • • • • • • • Bus Interface Unit Clocks, Address and Data Buses, Interrupt and Test Signals Internal Bus Interface Figure 23-1. FlexCAN Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-1...
Page 566: The Can System
FlexCAN caused by a defective CAN bus or defective stations. CAN Station 1 CAN Station 2 CAN Station n ColdFire Processor FlexCAN CANTX CANRX Transceiver CAN Bus Figure 23-3. Typical CAN System MCF5329 Reference Manual, Rev 3 23-2 Freescale Semiconductor...
Page 567: Features
CAN bus, or until the FlexCAN enters the error passive or bus off state. After one of these conditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration, matching, move-in, and move-out. When this happens, the following events occur: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-3...
Page 568 In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Transmit and receive interrupts are generated. MCF5329 Reference Manual, Rev 3 23-4 Freescale Semiconductor...
Page 569: External Signal Description
0x0000_0000 23.3.6/23-13 0xFC02_0020 Error and Status Register 0x0000_0000 23.3.6/23-13 (ERRSTAT) 0xFC02_0028 Interrupt Mask Register (IMASK) 0x0000_0000 23.3.7/23-15 0xFC02_0030 Interrupt Flag Register (IFLAG) 0x0000_0000 23.3.8/23-16 0xFC02_0080 Message Buffers 0–15 (MB0–15) 2048 — 23.3.9/23-16 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-5...
Page 570: Flexcan Configuration Register (Canmcr)
Clearing this bit causes the FlexCAN to exit freeze mode. Refer to Section 23.1.3.2, “Freeze Mode,” more information. 0 FlexCAN ignores the BKPT signal and the CANMCR[HALT] bit. 1 FlexCAN module enabled to enter debug mode. Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 23-6 Freescale Semiconductor...
Page 571 The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode. Note: Maximum MBs in Use = MAXMB + 1 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-7...
Page 572: Flexcan Control Register (Canctrl)
Phase buffer segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable PSEG2 values are 1–7. Eqn. 23-4 Phase buffer segment 2 (PSEG2 + 1) time quanta Bus off interrupt mask. BOFFMSK 0 Bus off interrupt disabled 1 Bus off interrupt enabled MCF5329 Reference Manual, Rev 3 23-8 Freescale Semiconductor...
Page 573 Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission. LBUF 0 Message buffer with lowest ID is transmitted first 1 Lowest numbered buffer is transmitted first MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-9...
Page 574: Flexcan Free Running Timer Register (Timer)
Free running timer. Captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured TIMER value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message. MCF5329 Reference Manual, Rev 3 23-10 Freescale Semiconductor...
Page 575: Rx Mask Registers (Rxgmask, Rx14Mask, Rx15Mask)
Mismatch for MB3 because of ID0. Mismatch for MB2 because of ID28. Mismatch for MB3 because of ID28, Match for MB14 (Uses RX14MASK). Mismatch for MB14 because of ID27 (Uses RX14MASK). Match for MB14 (Uses RX14MASK). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-11...
Page 576: Flexcan Error Counter Register (Errcnt)
128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the MCF5329 Reference Manual, Rev 3 23-12 Freescale Semiconductor...
Page 577: Flexcan Error And Status Register (Errstat)
Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to Section 23.4.1, “Interrupts.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-13...
Page 578 0 Receive error counter < 96 RXWRN 1 RxErrCounter ≥ 96 Idle status. Indicates when there is activity on the CAN bus. IDLE 0 The CAN bus is not idle. 1 The CAN bus is idle. MCF5329 Reference Manual, Rev 3 23-14 Freescale Semiconductor...
Page 579: Interrupt Mask Register (Imask)
0 The interrupt for the corresponding buffer is disabled. 1 The interrupt for the corresponding buffer is enabled. Note: Setting or clearing an IMASK bit can assert or negate an interrupt request, if the corresponding IFLAG bit it is set. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-15...
Page 580: Interrupt Flag Register (Iflag)
(0xFC02_0000). The 256-byte message buffer space is fully used by the16 message buffer structures. Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data. MCF5329 Reference Manual, Rev 3 23-16 Freescale Semiconductor...
Page 581 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 23-13. Message Buffer Structure for Extended and Standard Frames MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-17...
Page 582 Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from 23–16, the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame. 15–8, 7–0 DATA MCF5329 Reference Manual, Rev 3 23-18 Freescale Semiconductor...
Page 583 MB automatically returns to the INACTIVE state. 1100 0100 Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same ID for data frames. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-19...
Page 584: Functional Overview
The CPU prepares or changes an MB for transmission by writing the following: 1. Control/status word to hold Tx MB inactive (CODE = 1000) 2. ID word 3. Data bytes 4. Control/status word (active CODE, LENGTH) MCF5329 Reference Manual, Rev 3 23-20 Freescale Semiconductor...
Page 585: Arbitration Process
23.3.13 Receive Process The CPU prepares or changes an MB for frame reception by writing the following: 1. Control/status word to hold Rx MB inactive (CODE = 0000) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-21...
Page 586 FlexCAN MB, the frame is received by the FlexCAN. Such a frame is a self-received frame. FlexCAN does not receive frames transmitted by itself if another device on the CAN bus has an ID that matches the FlexCAN Rx MB ID. MCF5329 Reference Manual, Rev 3 23-22 Freescale Semiconductor...
Page 587: Matching Process
Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit or receive processes during the current matching or arbitration round. This mechanism is called MB deactivation. It is temporary, affecting only for the current match/arbitration round. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-23...
Page 588 ID arrives, then the new message overwrites the one on the SMB and there is no indication of lost messages in the code field of the MB or in the error and status register. MCF5329 Reference Manual, Rev 3 23-24 Freescale Semiconductor...
Page 589: Can Protocol Related Frames
• First or second bit of intermission • Seventh (last) bit of the end-of-frame (EOF) field in receive frames • Eighth (last) bit of the error frame delimiter or overload frame delimiter MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-25...
Page 590: Time Stamp
(number of Time Quanta) 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MCF5329 Reference Manual, Rev 3 23-26 Freescale Semiconductor...
Page 591 Jump Width 5 .. 10 1 .. 2 4 .. 11 1 .. 3 5 .. 12 1 .. 4 6 .. 13 1 .. 4 7 .. 14 1 .. 4 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 23-27...
Page 592: Initialization/Application Information
The control/status word of all message buffers must be written as an active or inactive message buffer. b) All other entries in each message buffer should be initialized as required. 3. Initialize RXGMASK, RX14MASK, and RX15MASK registers for acceptance mask as needed. MCF5329 Reference Manual, Rev 3 23-28 Freescale Semiconductor...
Page 593: Interrupts
(bus off and error) act in the same manner, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located in the CANCTRL register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 594 FlexCAN MCF5329 Reference Manual, Rev 3 23-30 Freescale Semiconductor...
Page 595: Introduction
This device contains SSI bits to control the clock rate and the SSI DMA request sources within the chip configuration module (CCM). See Chapter 9, “Chip Configuration Module (CCM),” for detailed information on these bit fields. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-1...
Page 596: Overview
Such serial devices are: • Standard codecs • Digital signal processors (DSPs) • Microprocessors • Peripherals ® • Audio codecs that implement the inter-IC sound bus (I S) and the Intel AC97 standards MCF5329 Reference Manual, Rev 3 24-2 Freescale Semiconductor...
Page 597: Features
• Gated clock mode These modes can be programmed via the SSI control registers. Table 24-1 lists these operating modes and some of the typical applications in which they can be used: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-3...
Page 598 In slave modes, the SSI’s programmed frame length setting (DC bits) can be lesser than or equal to the frame length setting of the master (external codec). Section 24.4.1, “Detailed Operating Mode Descriptions,” for more details on the above modes. MCF5329 Reference Manual, Rev 3 24-4 Freescale Semiconductor...
Page 599: External Signal Description
SSI_FS during rising edge of SSI_BCLK. 24.2.5 SSI_RXD — Serial Receive Data The SSI_RXD port is an input and brings serial data into the receive data shift register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-5...
Page 600: Ssi_Txd — Serial Transmit Data
The shift direction can be defined as msb first or lsb first, and there are other options on the clock and frame sync. MCF5329 Reference Manual, Rev 3 24-6 Freescale Semiconductor...
Page 601: Memory Map/Register Definition
0xFC0B_C008 SSI Receive Data Register 0 (SSI_RX0) 0x0000_0000 24.3.4/24-10 0xFC0B_C00C SSI Receive Data Register 1 (SSI_RX1) 0x0000_0000 24.3.4/24-10 0xFC0B_C010 SSI Control Register (SSI_CR) 0x0000_0000 24.3.7/24-13 0xFC0B_C014 SSI Interrupt Status Register (SSI_ISR) 0x0000_3003 24.3.8/24-15 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-7...
Page 602: Ssi Transmit Data Registers 0 And 1 (Ssi_Tx0/1)
Example: If Tx FIFO0 is not in use and you write Data1, Data2 to SSI_TX0, Data2 does not overwrite Data1 and is discarded. Note: Enable SSI (SSI_CR[SSI_EN] = 1) before writing to the SSI transmit data registers MCF5329 Reference Manual, Rev 3 24-8 Freescale Semiconductor...
Page 603: Ssi Transmit Fifo 0 And 1 Registers
They illustrate some possible values for WL, which can be extended for the other values. SSI_TX 12 bits 16 bits 20 bits 24 bits TXSR 16 bits 12 bits SSI_TXD Figure 24-5. Transmit Data Path (TXBIT0=0, TSHFD=0) (msb Alignment) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-9...
Page 604: Ssi Receive Data Registers 0 And 1 (Ssi_Rx0/1)
24.3.4 SSI Receive Data Registers 0 and 1 (SSI_RX0/1) The SSI_RX0/1 registers store the data received by the SSI. For details on data alignment see Section 24.3.6, “SSI Receive Shift Register (RXSR).” MCF5329 Reference Manual, Rev 3 24-10 Freescale Semiconductor...
Page 605: Ssi Receive Fifo 0 And 1 Registers
0. The following figures show the receiver loading and shifting operation. They illustrate some possible values for WL, which can be extended for the other values. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-11...
Page 606 SSI_RXD Figure 24-11. Receive Data Path (RXBIT0=0, RSHFD=1) (msb Alignment) SSI_RX 12 bits 16 bits 20 bits 24 bits 24 bits SSI_RXD RXSR Figure 24-12. Receive Data Path (RXBIT0=1, RSHFD=0) (lsb Alignment) MCF5329 Reference Manual, Rev 3 24-12 Freescale Semiconductor...
Page 607: Ssi Control Register (Ssi_Cr)
Two channel operation can be enabled for an even number of slots larger than two to optimize usage of both FIFOs. However, TCH should be cleared for an odd number of time slots. 0 Two channel mode disabled 1 Two channel mode enabled MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-13...
Page 608 Tx and Rx FIFOs are cleared. When SSI is disabled, all internal clocks are disabled (except the register access clock). 0 SSI module is disabled 1 SSI module is enabled MCF5329 Reference Manual, Rev 3 24-14 Freescale Semiconductor...
Page 609: Ssi Interrupt Status Register (Ssi_Isr)
It causes the receive tag interrupt if the SSI_IER[RXT] bit is set. This bit is cleared upon reading the SSI_ATAG register. 0 No change in SSI_ATAG register 1 SSI_ATAG register updated with different value MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-15...
Page 610 • At least one empty slot in Tx • Tx FIFO1 is full FIFO1 • SSI reset • POR reset Disabled • SSI_TX1 data transferred to • SSI_TX1 is written TXSR • SSI reset • POR reset MCF5329 Reference Manual, Rev 3 24-16 Freescale Semiconductor...
Page 611 Enabled • TXSR is empty • Reading SSI_ISR when TUE1 is • SSI_ISR[TDE1] set Disabled • Transmit time slot occurs • SSI reset • POR reset MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-17...
Page 612 Normal • RFS is always set • SSI reset • POR reset Network • First time slot received • Starts receiving next time slot • SSI reset • POR reset MCF5329 Reference Manual, Rev 3 24-18 Freescale Semiconductor...
Page 613 Receive FIFO full 0. Similar to description of RFF1, but pertains to Rx FIFO 0 and is not necessary to be in RFF0 two-channel mode for this bit to be set. 0 Space available in receive FIFO 0 1 Receive FIFO 0 is full MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-19...
Page 614: Ssi Interrupt Enable Register (Ssi_Ier)
Address: 0xFC0B_C018 (SSI_IER) Access: User read/write RDMAE RIE TDMAE CMDU Reset RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFF1 RFF0 TFE1 TFE0 Reset Figure 24-16. SSI Interrupt Enable Register (SSI_IER) MCF5329 Reference Manual, Rev 3 24-20 Freescale Semiconductor...
Page 615: Ssi Transmit Configuration Register (Ssi_Tcr)
SSI_TCR bits. However, an SSI reset does not affect the SSI_TCR bits. Address: 0xFC0B_C01C (SSI_TCR) Access: User read/write Reset TFEN1 TFEN0 TFDIR TXDIR TSHFD TSCKP TFSI TFSL TEFS BIT0 Reset Figure 24-17. SSI Transmit Configuration Register (SSI_TCR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-21...
Page 616 (TFSL = 0). The frame sync can also be initiated upon receiving the first bit of data. 0 Transmit frame sync initiated as first bit of data transmits 1 Transmit frame sync is initiated one bit before the data transmits MCF5329 Reference Manual, Rev 3 24-22 Freescale Semiconductor...
Page 617: Ssi Receive Configuration Register (Ssi_Rcr)
0 Gated clock mode disabled 1 Gated clock mode enabled Receive shift direction. Controls whether the msb or lsb is received first in a sample. RSHFD 0 Data received msb first 1 Data received lsb first MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-23...
Page 618: Ssi Clock Control Register (Ssi_Ccr)
Prescaler range. Controls a fixed divide-by-eight prescaler in series with the variable prescaler. It extends the range of the prescaler for those cases where a slower bit clock is required. 0 Prescaler bypassed 1 Prescaler enabled to divide the clock by 8 MCF5329 Reference Manual, Rev 3 24-24 Freescale Semiconductor...
Page 619: Ssi Fifo Control/Status Register (Ssi_Fcsr)
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Figure 24-20. SSI FIFO Control/Status Register (SSI_FCSR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 620 Transmit FIFO empty watermark 0. Controls the threshold for when the SSI_ISR[TFE0] flag is set. TFE0 is set when TFWM0 the data level in Tx FIFO 0 falls below the selected threshold. See TFWM1 for bit settings. MCF5329 Reference Manual, Rev 3 24-26 Freescale Semiconductor...
Page 621: Ssi Ac97 Control Register (Ssi_Acr)
The SSI automatically clears this bit after completing transmission of a frame. 0 Next frame does not have a write command 1 Next frame does have a write command Note: Do not set WR and RD at the same time. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-27...
Page 622: Ssi Ac97 Command Address Register (Ssi_Acadd)
SSI_ACR[WR and RD] bits). A direct write from the core or the information received in the incoming command address slot can update these bits. If contents of these bits change due to an update, the SSI_ISR[CMDAU] bit is set. MCF5329 Reference Manual, Rev 3 24-28...
Page 623: Ssi Ac97 Command Data Register (Ssi_Acdat)
If the SSI_ACR[TIF] bit is set, the TAG value is also stored in Rx FIFO. Note: Bits 1–0 convey the codec-ID. Because only primary codecs are supported, these bits must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-29...
Page 624: Ssi Transmit Time Slot Mask Register (Ssi_Tmask)
1 Time slot masked (no data received in this time slot) 24.4 Functional Description 24.4.1 Detailed Operating Mode Descriptions The following sections describe in detail the main operating modes of the SSI module: normal, network, gated clock, I S, and AC97. MCF5329 Reference Manual, Rev 3 24-30 Freescale Semiconductor...
Page 625 1. SSI enabled (SSI_CR[SSI_EN] = 1) 2. Enable receive FIFO (optional) 3. Receiver enabled (RE = 1) 4. Frame sync active (for continuous clock case) 5. Bit clock begins (for gated clock case) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-31...
Page 626 SSI_RXD input, and at the end of the time slot, this data transfers to the Rx data register. In internal gated clock mode, the Tx data line and clock output port are MCF5329 Reference Manual, Rev 3 24-32...
Page 627 The period of the serial bit clock (PSR, PM bits for internal clock, or the frequency of the external clock on the SSI_BCLK pin) • The number of bits per sample (WL bits) • The number of time slots per frame (DC bits) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-33...
Page 628 TE bit enables transmission from the next frame. During that time the SSI_TXD port is disabled. The TE bit should be cleared after the TDE bit is set to ensure that all pending data is transmitted. MCF5329 Reference Manual, Rev 3 24-34...
Page 629 8-bit word with continuous clock, FIFO disabled, three words per frame sync in network mode. NOTE The transmitter repeats the value 0x5E because of an underrun condition. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-35...
Page 630 (ROE) flag is set on reception of the next data (0x5E). The ROE flag is cleared by reading the SSI status register followed by reading the Rx data register. MCF5329 Reference Manual, Rev 3 24-36...
Page 631 SSI_RXD signals. For this reason, no frame sync is needed in this mode. After transmission of data completes, the clock is pulled to the inactive state. Gated clocks are allowed for the transmit and receive MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 632 SSI_RXD TSCKP=1, RSCKP=1 Figure 24-32. Internal Gated Mode Timing - Falling Edge Clocking/Rising Edge Latching SSI_BCLK SSI_TXD SSI_RXD TSCKP=0, RSCKP=0 Figure 24-33. External Gated Mode Timing - Rising Edge Clocking/Falling Edge Latching MCF5329 Reference Manual, Rev 3 24-38 Freescale Semiconductor...
Page 633 S slave mode Normal mode In normal (non-I S) mode operation, no register bits are forced to any particular state internally, and the user can program the SSI to work in any operating condition. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-39...
Page 634 S Slave Mode In I S slave mode (SSI_CR[I2S] = 10), the following additional settings are recommended: • External generated bit clock (SSI_TCR[TXDIR] = 0) • External generated frame sync (SSI_TCR[TFDIR] = 0) MCF5329 Reference Manual, Rev 3 24-40 Freescale Semiconductor...
Page 635 Tx frame sync length is one-word-long-frame (SSI_TCR[TFSL] = 0) • Rx frame sync length is one-word-long-frame (SSI_RCR[RFSL] = 0) • Tx frame sync initiated one bit before data is transmitted (SSI_TCR[TEFS] = 1) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-41...
Page 636 SSI should be idle, after operating for one frame. The following shows the slot assignments in a valid transmit frame: • Slot 0: The tag value (written by the user program) • Slot 1: If RD/WR command, command address MCF5329 Reference Manual, Rev 3 24-42 Freescale Semiconductor...
Page 637: Ssi Clocking
SSI_CR[MCE] bit. This serial master clock is an oversampling clock of the frame sync clock (SSI_FS). In this mode, the word length (WL), prescaler range MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 638 When internally generated, receive and transmit frame sync generate from the word clock and are defined by the frame rate divider (DC) bits and the word length (WL) bits of the SSI_CCR. MCF5329 Reference Manual, Rev 3 24-44 Freescale Semiconductor...
Page 639 Table 24-22. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2 SSI_CLKIN SSI_CCR Bit Clk (kHz) Frame rate freq (MHz) SSI_BCLK (kHz) (SSI_MCLK) DIV2 PSR 12.288 12.288 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-45...
Page 640: External Frame And Clock Operation
SSI_TX0/1 and SSI_RX0/1 based on the data format and the number of bits per word. Independent data formats are supported for the transmitter and receiver (i.e. the transmitter and receiver can use different data formats). MCF5329 Reference Manual, Rev 3 24-46 Freescale Semiconductor...
Page 641 In sign-extension, all bits above the most significant bit are equal to the most significant bit. This format is useful when data is stored in a fixed-point integer format (which implies fractional values). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-47...
Page 642: Receive Interrupt Enable Bit Description
Tx FIFO 1). If not enabled, then one value can be written to the SSI_TX0 register (one per channel in two-channel mode using SSI_TX1). When the TIE bit is cleared, all transmit interrupts are disabled. However, the TDE0/1 bits always indicate the corresponding SSI_TX register MCF5329 Reference Manual, Rev 3 24-48 Freescale Semiconductor...
Page 643: Initialization/Application Information
To ensure proper operation of the SSI, use the power-on or SSI reset before changing any of the control bits listed in Table 24-27. NOTE These control bits should not be changed when the SSI module is enabled. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 24-49...
Page 644 [8]=RFEN1 and TFEN1 [7]=RFEN0 and TFEN0 [6]=TFDIR SSI_RCR [5]=RXDIR and TXDIR SSI_TCR [4]=RSHFD and TSHFD [3]=RSCKP and TSCKP [2]=RFSI and TFSI [1]=RFSL and TFSL [0]=REFS and TEFS SSI_CCR [16:13]=WL [1]=FV SSI_ACR [10:5]=FRDIV MCF5329 Reference Manual, Rev 3 24-50 Freescale Semiconductor...
Page 645: Introduction
Figure 25-1. Real Time Clock Block Diagram 25.1.1 Overview This section discusses how to operate and program the real-time clock (RTC) module that maintains a time-of-day clock, provides stopwatch, alarm, and interrupt functions, and supports the following features. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 25-1...
Page 646: Features
• Minute Stopwatch — The minute stopwatch performs a countdown with a one minute resolution. It generates an interrupt on a minute boundary. MCF5329 Reference Manual, Rev 3 25-2 Freescale Semiconductor...
Page 647: External Signal Description
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 – – – – – 0 0 – – – – – – Figure 25-2. RTC Hours and Minutes Counter Register (RTC_HOURMIN) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 648: Rtc Seconds Counter Register (Rtc_Seconds)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-4. RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) MCF5329 Reference Manual, Rev 3 25-4...
Page 649: Rtc Seconds Alarm Register (Rtc_Alrm_Sec)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-6. RTC Control Register (RTC_CR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 25-5...
Page 650: Rtc Interrupt Status Register (Rtc_Isr)
Sampling timer 7–0 interrupt flags. Indicates an interrupt has occurred at the corresponding sampling rate. See SAMn Section 25.4.3, “Sampling Timer,” for more details. 0 No SAM7–0 interrupt has occurred 1 A SAM7–0 interrupt has occurred MCF5329 Reference Manual, Rev 3 25-6 Freescale Semiconductor...
Page 651: Rtc Interrupt Enable Register (Rtc_Ier)
The RTC_IER register enables/disables the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit. Address: 0xFC0A_8018 (RTC_IER) Access: User read/write Reset SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 2HZ Reset Figure 25-8. RTC Interrupt Enable Register (RTC_IER) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 25-7...
Page 652: Rtc Stopwatch Minutes Register (Rtc_Stpwch)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Figure 25-9. RTC Stopwatch Minutes Register (RTC_STPWCH) MCF5329 Reference Manual, Rev 3 25-8...
Page 653: Rtc Days Counter Register (Rtc_Days)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25-11. RTC Day Alarm Register (RTC_ALRM_DAY) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 654: Functional Description
RTC_IER register during the alarm interrupt service routine. Section 25.5, “Initialization/Application Information,” for the correct procedure to follow when changing the alarm or time-of-day (day, hour, minute, or second) registers. MCF5329 Reference Manual, Rev 3 25-10 Freescale Semiconductor...
Page 655: Sampling Timer
-1, interrupt occurs. The value of the register does not change until it is reprogrammed. The actual delay includes the seconds from setting the stopwatch to the next minute tick. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 656: Initialization/Application Information
Program the alarm or time-of-day registers Clear any incidental alarm interrupt during programming (write 1 to RTC_ISR[ALM]) Enable the alarm interrupt (set RTC_IER[ALM] Figure 25-13. Flow Chart of Alarm and Time-of-Day Programming MCF5329 Reference Manual, Rev 3 25-12 Freescale Semiconductor...
Page 657: Introduction
Channel 3 PWMOUT3 Alignment Period and Duty Counter Channel 2 Period and Duty Counter Channel 1 PWMOUT1 Period and Duty Counter Channel 0 Period and Duty Counter Figure 26-1. PWM Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-1...
Page 658: Memory Map/Register Definition
PWM Channel n Period Register (PWMPERn) 0xFF 26.2.10/26-10 n = 0–7 0xFC09_003C + n PWM Channel n Duty Register (PWMDTYn) 0xFF 26.2.11/26-10 n = 0–7 0xFC09_0044 PWM Shutdown Register (PWMSDN) 0x00 26.2.12/26-11 MCF5329 Reference Manual, Rev 3 26-2 Freescale Semiconductor...
Page 659: Pwm Enable Register (Pwme)
PWM Channel 1 Output Enable. If enabled, the PWM signal becomes available at PWMOUT1 when its PWME1 corresponding clock source begins its next cycle. 0 PWM output disabled 1 PWM output enabled Reserved, must be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-3...
Page 660: Pwm Polarity Register (Pwmpol)
PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Address: 0xFC09_0022 (PWMCLK) Access: User Read/Write PCLK7 PCLK5 PCLK3 PCLK1 Reset: Figure 26-4. PWM Clock Select Register (PWMCLK) MCF5329 Reference Manual, Rev 3 26-4 Freescale Semiconductor...
Page 661: Pwm Prescale Clock Select Register (Pwmprclk)
Clock B prescaler select. These three bits control the rate of Clock B, which can be used for PWM channels 3 and 7. PCKB PCKB Clock B Rate Internal bus clock ÷ 2 Internal bus clock ÷ 2 Internal bus clock ÷ 2 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-5...
Page 662: Pwm Center Align Enable Register (Pwmcae)
The PWMCTL register provides various control of the PWM module. Change the CONn(n+1) bits only when both corresponding channels are disabled. See Section 26.3.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation function. MCF5329 Reference Manual, Rev 3 26-6 Freescale Semiconductor...
Page 663: Pwm Scale A Register (Pwmscla)
Clock A ---------------------------------------- - Eqn. 26-1 Clock SA × PWMSCLA Any value written to this register causes the scale counter to load the new scale value (PWMSCLA). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-7...
Page 664: Pwm Scale B Register (Pwmsclb)
Any value written to this register causes the scale counter to load the new scale value (PWMSCLB). Address: 0xFC09_0029 (PWMSCLB) Access: User Read/Write SCALEB Reset: Figure 26-9. PWM Scale B Register (PWMSCLB) MCF5329 Reference Manual, Rev 3 26-8 Freescale Semiconductor...
Page 665: Pwm Channel Counter Registers (Pwmcnt N )
Section 26.3.2.4, “PWM Timer Counters.” Address: 0xFC09_002C (PWMCNT0) Access: User Read/Write 0xFC09_002D (PWMCNT1) 0xFC09_002E (PWMCNT2) 0xFC09_002F (PWMCNT3) 0xFC09_0030 (PWMCNT4) 0xFC09_0031 (PWMCNT5) 0xFC09_0032 (PWMCNT6) 0xFC09_0033 (PWMCNT7) COUNT Reset: Figure 26-10. PWM Counter Registers (PWMCNTn) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-9...
Page 666: Pwm Channel Period Registers (Pwmper N )
(high time as a percentage of period) for a particular channel: ⎛ ⎞ PWMDTYn × ----------------------------- - Eqn. 26-4 Duty Cycle 1 PWMPOL PPOLn – – 100% ⎝ ⎠ PWMPERn MCF5329 Reference Manual, Rev 3 26-10 Freescale Semiconductor...
Page 667: Pwm Shutdown Register (Pwmsdn)
The PWM shutdown register provides emergency shutdown functionality of the PWM module. The PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared. : 0xFC09_0044 (PWMSDN) Access: Read/Write PWM7IN PWM7IL SDNEN RESTART Reset: Figure 26-13. PWM Shutdown Register (PWMSDN) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-11...
Page 668: Functional Description
PWM channel has the capability of selecting one of two clocks, the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 26-14 shows the four different clocks and how the scaled clocks are created. MCF5329 Reference Manual, Rev 3 26-12 Freescale Semiconductor...
Page 669 Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-13...
Page 670: Pwm Channel Timers
The starting polarity of the output is also selectable on a per channel basis. Figure 26-15 shows a block diagram for a PWM timer. MCF5329 Reference Manual, Rev 3 26-14 Freescale Semiconductor...
Page 671 A change in duty or period can be forced into effect immediately by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 672 When PWMCNTn register written to any When PWM channel is enabled When PWM channel is disabled value (PWMEn = 1). Counts from last value (PWMEn = 0) in PWMCNTn. Effective period ends MCF5329 Reference Manual, Rev 3 26-16 Freescale Semiconductor...
Page 673 PWMn frequency = 80 MHz ÷ 4 = 20 MHz PWMn period = 50 ns ⎛ ⎞ × -- - PWMn Duty Cycle – 100% ⎝ ⎠ The output waveform generated is below: MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-17...
Page 674 Clock (A, B, SA, or SB) --------------------------------------------------------- - Eqn. 26-9 PWMn frequency × WMPERn The PWMn duty cycle (high time as a percentage of period) is expressed as: MCF5329 Reference Manual, Rev 3 26-18 Freescale Semiconductor...
Page 675 In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-19...
Page 676 PPOL1 PCLK1 CAE1 PWMOUT1 26.3.2.8 PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (left- or center-aligned) and 8-bit (normal) or 16-bit (concatenation): MCF5329 Reference Manual, Rev 3 26-20 Freescale Semiconductor...
Page 677 Always High (indicates no duty) 0x00 Always High (indicates no period) 0x00 Always Low (indicates no period) ≥ PWMPERn Always High ≥ PWMPERn Always Low Counter = 0x00 and does not count. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 26-21...
Page 678 Pulse-Width Modulation (PWM) Module MCF5329 Reference Manual, Rev 3 26-22 Freescale Semiconductor...
Page 679: Introduction
If the WCR[HALTED] bit is cleared, the watchdog timer continues to operate normally after executing a HALT instruction. This is a debug feature available for the user MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 27-1...
Page 680: Block Diagram
0xFC09_8006 Watchdog Service Register (WSR) 0x0000 27.2.4/27-5 Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. MCF5329 Reference Manual, Rev 3 27-2 Freescale Semiconductor...
Page 681: Watchdog Control Register (Wcr)
When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. After disabled, the watchdog cannot be re-enabled. 0 Watchdog timer disabled 1 Watchdog timer enabled MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 27-3...
Page 682: Watchdog Modulus Register (Wmr)
Watchdog count field. Reflects the current value in the watchdog counter. Reading the 16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to WCNTR has no effect, and write cycles are terminated normally. MCF5329 Reference Manual, Rev 3 27-4 Freescale Semiconductor...
Page 683: Watchdog Service Register (Wsr)
However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset. Address: 0xFC09_8006 Access: User read/write Reset Figure 27-5. Watchdog Service Register (WSR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 27-5...
Page 684 Watchdog Timer Module MCF5329 Reference Manual, Rev 3 27-6 Freescale Semiconductor...
Page 685 Low-power modes are described in the power management module, Chapter 8, “Power Management.” Table 28-1 shows the PIT module operation in low-power modes and how it can exit from each mode. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 28-1...
Page 686 Address PIT 0 Width Register Access Reset Value Section/Page PIT 1 (bits) PIT 2 PIT 3 Supervisor Access Only Registers 0xFC08_0000 PIT Control and Status Register (PCSRn) 0x0000 28.2.1/28-3 0xFC08_4000 0xFC08_8000 0xFC08_C000 MCF5329 Reference Manual, Rev 3 28-2 Freescale Semiconductor...
Page 687 PIT Control and Status Register (PCSRn) The PCSRn registers configure the corresponding timer’s operation. Address: 0xFC08_0000 (PCSR0) Access: Supervisor 0xFC08_4000 (PCSR1) read/write 0xFC08_8000 (PCSR2) 0xFC08_C000 (PCSR3) DOZE DBG OVW Reset Figure 28-2. PCSRn Register MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 28-3...
Page 688 PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF. 0 PIT count has not reached 0x0000. 1 PIT count has reached 0x0000. MCF5329 Reference Manual, Rev 3 28-4 Freescale Semiconductor...
Page 689 The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 28-5...
Page 690: Set-And-Forget Timer Operation
0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement. When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag issues an interrupt request to the CPU. MCF5329 Reference Manual, Rev 3 28-6 Freescale Semiconductor...
Page 691: Timeout Specifications
The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 692 Programmable Interrupt Timers (PIT0–PIT3) MCF5329 Reference Manual, Rev 3 28-8 Freescale Semiconductor...
Page 693: Introduction
DMA transfer on a particular event. NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”) prior to configuring the DMA Timers. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-1...
Page 694: Features
Input-capture capability with programmable trigger edge on input pin • Programmable mode for the output pin on reference compare • Free run and restart modes • Programmable interrupt or DMA request on input capture or reference-compare MCF5329 Reference Manual, Rev 3 29-2 Freescale Semiconductor...
Page 695: Memory Map/Register Definition
DMA Timer Mode Registers (DTMRn) DTMRs, shown in Figure 29-2, program the prescaler and various timer modes. Address: 0xFC07_0000 (DTMR0) Access: User read/write 0xFC07_4000 (DTMR1) 0xFC07_8000 (DTMR2) 0xFC07_C000 (DTMR3) ORRI FRR Reset Figure 29-2. DTMRn Registers MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-3...
Page 696: Dma Timer Extended Mode Registers (Dtxmr N )
DMA Timer Extended Mode Registers (DTXMRn) The DTXMRn register programs DMA request and increment modes for the timers. Address: 0xFC07_0002 (DTXMR0) Access: User read/write 0xFC07_4002 (DTXMR1) 0xFC07_8002 (DTXMR2) 0xFC07_C002 (DTXMR3) DMAEN MODE16 Figure 29-3. DTXMRn Registers MCF5329 Reference Manual, Rev 3 29-4 Freescale Semiconductor...
Page 697: Dma Timer Event Registers (Dter N )
If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal. Address: 0xFC07_0003 (DTER0) Access: User read/write 0xFC07_4003 (DTER1) 0xFC07_8003 (DTER2) 0xFC07_C003 (DTER3) Reset: Figure 29-4. DTERn Registers MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-5...
Page 698: Dma Timer Reference Registers (Dtrr N )
(DTCNn). The reference value is matched when DTCNn equals DTRRn. The prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals. MCF5329 Reference Manual, Rev 3 29-6 Freescale Semiconductor...
Page 699: Dma Timer Capture Registers (Dtcr N )
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-6. DTCRn Registers Table 29-6. DTCRn Field Descriptions Field Description 31–0 Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTnIN, as programmed in DTMRn. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-7...
Page 700: Dma Timer Counters (Dtcn N )
If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted. If the free run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running. MCF5329 Reference Manual, Rev 3 29-8 Freescale Semiconductor...
Page 701: Output Mode
DTMR1 EQU 0xFC07_4000 ;Timer1 mode register DTRR0 EQU 0xFC07_0004 ;Timer0 reference register DTRR1 EQU 0xFC07_4004 ;Timer1 reference register DTCR0 EQU 0xFC07_0008 ;Timer0 capture register DTCR1 EQU 0xFC07_4008 ;Timer1 capture register DTCN0 EQU 0xFC07_000C ;Timer0 counter register MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-9...
Page 702: Calculating Time-Out Values
Eqn. 29-1 When calculating time-out periods, add 1 to the prescaler to simplify calculating, because DTMRn[PS] equals 0x00 yields a prescaler of 1, and DTMRn[PS] equals 0xFF yields a prescaler of 256. MCF5329 Reference Manual, Rev 3 29-10 Freescale Semiconductor...
Page 703 For example, if a 80-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x1312C (78,124 decimal), the time-out period is: × × × ------------------- - Eqn. 29-2 Timeout period 78124 2.00 s × MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 29-11...
Page 704 DMA Timers (DTIM0–DTIM3) MCF5329 Reference Manual, Rev 3 29-12 Freescale Semiconductor...
Page 705: Introduction
Regs Rx/Tx Data Reg. Logic Array Control QSPI_DOUT Regs Command QSPI_CS[2:0] Delay Counter Internal Bus Internal Bus Baud Rate Divide by 2 QSPI_CLK Generator Clock (f sys/3 Figure 30-1. QSPI Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-1...
Page 706: Overview
Although QSPI_CSn signals function as simple chip selects in most applications, up to 7 devices can be selected by decoding them with an external 3-to-8 decoder. MCF5329 Reference Manual, Rev 3 30-2 Freescale Semiconductor...
Page 707: Memory Map/Register Definition
Because the QSPI does not operate in slave mode, the master mode enable bit (QMR[MSTR]) must be set for the QSPI module to operate correctly. Address: 0xFC05_C000 (QMR) Access: User read/write MSTR BITS CPOL CPHA BAUD Reset Figure 30-2. QSPI Mode Register (QMR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-3...
Page 708 A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression: / (2 × [desired QSPI_CLK baud rate]) QMR[BAUD] = f sys/3 MCF5329 Reference Manual, Rev 3 30-4 Freescale Semiconductor...
Page 709: Qspi Delay Register (Qdlyr)
7–0 Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-5...
Page 710: Qspi Wrap Register (Qwr)
QSPI Interrupt Register (QIR) The QIR contains QSPI interrupt enables and status flags. Address: 0xFC05_C00C (QIR) Access: User read/write WCEF ABRT SPIF WCEFB ABRTB ABRTL WCEFE ABRTE SPIFE Reset Figure 30-6. QSPI Interrupt Register (QIR) MCF5329 Reference Manual, Rev 3 30-6 Freescale Semiconductor...
Page 711: Qspi Address Register (Qar)
A read or write to the QSPI RAM causes QAR to increment. However, the QAR does not wrap after the last queue entry within each section of the RAM. The application software must manage address range errors. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-7...
Page 712: Qspi Data Register (Qdr)
RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations. MCF5329 Reference Manual, Rev 3 30-8 Freescale Semiconductor...
Page 713: Functional Description
The QSPI uses a dedicated 80-byte block of static RAM accessible to the module and CPU to perform queued operations. The RAM is divided into three segments: • 16 command control bytes (command RAM) • 32 transmit data bytes (transmit data RAM) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-9...
Page 714 The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]). MCF5329 Reference Manual, Rev 3 30-10 Freescale Semiconductor...
Page 715: Qspi Ram
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. Read this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 716: Baud Rate Selection
QSPI_CLK rate from the internal bus clock divided by two. Table 30-10 shows the QSPI_CLK frequency as a function of internal bus clock and baud rate. A baud rate value of zero turns off the QSPI_CLK. MCF5329 Reference Manual, Rev 3 30-12 Freescale Semiconductor...
Page 717: Transfer Delays
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1: × QDLYR[DTL] ----------------------------------------------- - Eqn. 30-3 Delay after transfer (DT = 1) sys/3 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-13...
Page 718: Transfer Length
QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, MCF5329 Reference Manual, Rev 3 30-14...
Page 719: Initialization/Application Information
11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 30-15...
Page 720 Queued Serial Peripheral Interface (QSPI) MCF5329 Reference Manual, Rev 3 30-16 Freescale Semiconductor...
Page 721: Introduction
(to Interrupt Controller) Logic Programmable Internal Bus Clock (f Clock Transmit DMA Request sys/3 DMA Request Generation or External Clock (DTnIN) Logic Receive DMA Request (To DMA Controller) Figure 31-1. UART Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-1...
Page 722: Features
All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character MCF5329 Reference Manual, Rev 3 31-2 Freescale Semiconductor...
Page 723: External Signal Description
Writing control bytes into the appropriate registers controls the operation of the UART module. NOTE UART registers are accessible only as bytes. NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-3...
Page 724 UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur. Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. MCF5329 Reference Manual, Rev 3 31-4 Freescale Semiconductor...
Page 725 Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 726 Address: 0xFC06_0000 (UMR20) Access: User read/write 0xFC06_4000 (UMR21) 0xFC06_8000 (UMR22) TXRTS TXCTS Reset: After UMR1n is read or written, the pointer points to UMR2n Figure 31-4. UART Mode Registers 2 (UMR2n) MCF5329 Reference Manual, Rev 3 31-6 Freescale Semiconductor...
Page 727 1001 1.625 0010 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-7...
Page 728 1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. MCF5329 Reference Manual, Rev 3 31-8 Freescale Semiconductor...
Page 729 The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, cannot be RESET TRANSMITTER ENABLE TRANSMITTER specified in one command. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-9...
Page 730 Transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS. Causes UnTXD to go high (mark) within two bit times. Any characters in the STOP BREAK transmit buffer are sent. MCF5329 Reference Manual, Rev 3 31-10 Freescale Semiconductor...
Page 731 FIFO. UnRXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 31-18). RB contains the character in the receiver. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-11...
Page 732 UART Input Port Change Registers (UIPCRn) The UIPCRs hold the current state and the change-of-state for UnCTS. Address: 0xFC06_0010 (UIPCR0) Access: User read-only 0xFC06_4010 (UIPCR1) 0xFC06_8010 (UIPCR2) Reset: UnCTS Figure 31-10. UART Input Port Changed Registers (UIPCRn) MCF5329 Reference Manual, Rev 3 31-12 Freescale Semiconductor...
Page 733 UISRn bit has no effect on the output. The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-13...
Page 734 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. MCF5329 Reference Manual, Rev 3 31-14 Freescale Semiconductor...
Page 735 31.3.12 UART Input Port Register (UIPn) The UIPn registers show the current state of the UnCTS input. Address: 0xFC06_0034 (UIP0) Access: User read-only 0xFC06_4034 (UIP1) 0xFC06_8034 (UIP2) Reset: Figure 31-15. UART Input Port Registers (UIPn) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-15...
Page 736: Transmitter/Receiver Clock Source
The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. MCF5329 Reference Manual, Rev 3 31-16 Freescale Semiconductor...
Page 737 When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: sys/3 Eqn. 31-1 ---------------------------------- - Baudrate 32 x divider MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-17...
Page 738: Transmitter And Receiver Operating Modes
UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on UnTXD. It automatically sends a start bit followed by the programmed number of data bits, an MCF5329 Reference Manual, Rev 3 31-18...
Page 739 The transmitter must be manually reenabled by reasserting UnRTS before the next message is sent. Figure 31-19 shows the functional timing information for the transmitter. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-19...
Page 740 (framing error) and UnRXD remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error, MCF5329 Reference Manual, Rev 3 31-20...
Page 741 In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break (RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 742: Looping Modes
Section 31.3, “Memory Map/Register Definition.” The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. MCF5329 Reference Manual, Rev 3 31-22 Freescale Semiconductor...
Page 743 Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until next valid start bit is detected. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 744: Multidrop Mode
Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in Figure 31-24. MCF5329 Reference Manual, Rev 3 31-24 Freescale Semiconductor...
Page 745 If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 746: Bus Operation
Section 14.2.9.1, “Interrupt Sources,” for details on interrupt assignments for the UART modules. 1. Initialize the appropriate ICRx register in the interrupt controller. 2. Unmask appropriate bits in IMR in the interrupt controller. MCF5329 Reference Manual, Rev 3 31-26 Freescale Semiconductor...
Page 747 The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing. Table 31-14 shows the DMA requests. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-27...
Page 748: Uart Module Initialization Sequence
Select the mode of operation (CM bits). b) If preferred, program operation of transmitter ready-to-send (TXRTS). c) If preferred, program operation of clear-to-send (TXCTS bit). d) Select stop-bit length (SB bits). 7. UCRn: Enable transmitter and/or receiver. MCF5329 Reference Manual, Rev 3 31-28 Freescale Semiconductor...
Page 749 Enable Serial Module Errors? SINIT Initiate: Channel Enable Receiver Interrupts CHK1 Assert Request To Send Call CHCHK SINITR Return Save Channel Status Figure 31-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-29...
Page 750 Transmitter Never-ready Flag Too Long? Ready? SNDCHR Send Character To Transmitter RxCHK Waited Set Receiver- Character Been Too Long? Never-ready Flag Received? Figure 31-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF5329 Reference Manual, Rev 3 31-30 Freescale Semiconductor...
Page 751 PRCHK Have Return Parity Error? Set Parity Error Flag CHRCHK Get Character From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 31-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-31...
Page 752 Clear Change-in- Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack And Monitor Warm Start Address SIRQR Figure 31-25. UART Mode Programming Flowchart (Sheet 4 of 5) MCF5329 Reference Manual, Rev 3 31-32 Freescale Semiconductor...
Page 753 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 31-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 31-33...
Page 754 UART Modules MCF5329 Reference Manual, Rev 3 31-34 Freescale Semiconductor...
Page 755: Introduction
Register I/O Register Register (I2FDR) (I2CR) (I2SR) (I2DR) (I2ADR) In/Out Clock Data Control Shift Register Start, Stop, Arbitration Control Input Address Sync Compare I2C_SCL I2C_SDA Figure 32-1. I C Module Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-1...
Page 756: Overview
Arbitration-lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • START and STOP signal generation/detection • Repeated START signal generation • Acknowledge bit generation/detection • Bus-busy detection MCF5329 Reference Manual, Rev 3 32-2 Freescale Semiconductor...
Page 757: Memory Map/Register Definition
The I2FDR, shown in Figure 32-3, provides a programmable prescaler to configure the I C clock for bit-rate selection. Address: 0xFC05_8004 (I2FDR) Access: User read/write Reset: Figure 32-3. I C Frequency Divider Register (I2FDR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-3...
Page 758 C interrupt. It also contains bits that govern operation as a slave or a master. Address: 0xFC05_8008 (I2CR) Access: User read/write IIEN MSTA TXAK RSTA Reset: Figure 32-4. I C Control Register (I2CR) MCF5329 Reference Manual, Rev 3 32-4 Freescale Semiconductor...
Page 759 Reserved, must be cleared. 32.2.4 C Status Register (I2SR) I2SR contains bits that indicate transaction direction and status. Address: 0xFC05_800C (I2SR) Access: User read/write IAAS RXAK Reset: Figure 32-5. I C Status Register (I2SR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-5...
Page 760 In master-receive mode, reading I2DR allows a read to occur and for the next data byte to be received. In slave mode, the same function is available after the I C has received its slave address. MCF5329 Reference Manual, Rev 3 32-6 Freescale Semiconductor...
Page 761: Functional Description
32-7). A START signal is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-7...
Page 762: Slave Address Transmission
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Slave Address Data Byte STOP ACK from START ACK Bit Signal Receiver Signal Figure 32-8. Data Transfer MCF5329 Reference Manual, Rev 3 32-8 Freescale Semiconductor...
Page 763: Acknowledge
Figure 32-10. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-9...
Page 764 Note: No acknowledge on the last byte Example 3: 7-bit Slave Rept 7-bit Slave Data Data Data Address Address Master Writes to Slave Master Reads from Slave Figure 32-11. Data Transfer, Combined Format MCF5329 Reference Manual, Rev 3 32-10 Freescale Semiconductor...
Page 765: Clock Synchronization And Arbitration
STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. I2C_SCL I2C_SDA by Master1 I2C_SDA by Master 2 Loses Arbitration, Master2 and becomes slave-receiver I2C_SDA Figure 32-13. Arbitration Procedure MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-11...
Page 766: Handshaking And Clock Stretching
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the MCF5329 Reference Manual, Rev 3 32-12...
Page 767: Post-Transfer Software Response
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-13...
Page 768: Generation Of Repeated Start
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. MCF5329 Reference Manual, Rev 3 32-14 Freescale Semiconductor...
Page 769 Rx Mode Mode Read Data Generate Dummy Read Dummy Read Dummy Read from I2DR from I2DR STOP Signal from I2DR from I2DR And Store Figure 32-14. Flow-Chart of Typical I C Interrupt Routine MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 32-15...
Page 770 C Interface MCF5329 Reference Manual, Rev 3 32-16 Freescale Semiconductor...
Page 771: Introduction
The security of the hash function is based on the difficulty of locating collisions. That is, it is computationally infeasible to construct two distinct but similar messages that produce the same hash output. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-1...
Page 772: Modes Of Operation
— MD5: Message Digest 5 algorithm defined by Ron Rivest of MIT Laboratory for Computer Science and RSA Data Security, INC. • MAC: A Message authentication code is a one-way function performed on a message with two user defined keys: MCF5329 Reference Manual, Rev 3 33-2 Freescale Semiconductor...
Page 773: Memory Map/Register Definition
The MDMR stores the current processing mode. It can be written before a hashing operation begins. After the hashing operation has begun, an error is generated if the register is written. This register is reset only via a hardware or software reset. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-3...
Page 774 SHA-1 Inner padding of message. Exclusive OR the message with 0x3636_3636. Hash used with HMAC. Requires key to IPAD be loaded into the FIFO 0 Do not perform padding 1 Perform padding MCF5329 Reference Manual, Rev 3 33-4 Freescale Semiconductor...
Page 775 MDHA requires that the IPAD step be performed as a separate (HMAC) hash operation than message authentication. MAC=01 OPAD MDHA requires that the OPAD step be performed as a separate (HMAC) hash operation than message authentication. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-5...
Page 776: Mdha Control Register (Mdcr)
1 Big endian mode DMA enable. Enables/disables DMA requests from the MDHA module. 0 Disable DMA requests 1 Enable DMA requests Interrupt enable. Enables/disables interrupts from the MDHA module. 0 Disable interrupts 1 Enable interrupts MCF5329 Reference Manual, Rev 3 33-6 Freescale Semiconductor...
Page 777: Mdha Command Register (Mdcmr)
1 Re-initialize the MDHA module Software reset. Resets all registers and re-initialize memory of the MDHA. Functionally equivalent to hardware reset. This bit is self clearing. 0 No reset 1 Software reset MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-7...
Page 778: Mdha Status Register (Mdsr)
Busy. Read-only. Indicates that the module is busy processing data. BUSY 0 Idle or done 1 Busy processing data Reset interrupt. Read-only. Indicates the MDHA module has completed resetting. 0 Reset in progress 1 Completed reset sequence MCF5329 Reference Manual, Rev 3 33-8 Freescale Semiconductor...
Page 779: Mdha Interrupt Status & Mask Registers (Mdisr And Mdimr)
Masking errors should only be used for debug purposes. A masked error most likely causes invalid data. Address: 0xEC08_0010 (MDISR) Access: User read-only Reset DRL GTDS ERE RMDP NEIF Reset Figure 33-6. MDHA Interrupt Status Registers (MDISR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-9...
Page 780 1 Illegal value in MDMR Reserved, should be cleared. Non-empty input FIFO upon done. Read only. The Input FIFO contained data when processing was completed NEIF 0 No error 1 FIFO contained data when finished processing MCF5329 Reference Manual, Rev 3 33-10 Freescale Semiconductor...
Page 781: Mdha Data Size Register (Mddsr)
(digest/context) of the hashing process. Message digest data may only be read if the MDSR[DONE] bit is set. Any reads prior to this result is an early read error (MDISR[ERE]). The message MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 782: Mdha Message Data Size Register (Mdmds)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-12. MDHA Message Digest Registers 1 (MDx1) MCF5329 Reference Manual, Rev 3 33-12...
Page 783: Functional Description
The FIFO block contains a 16×32-bit FIFO that is used for temporary storage of the data to be hashed. 33.3.3 MDHA Logic The MDHA logic block consists of 7 sub-blocks: the address decoder, interface control, auto-padder, algorithm engine, algorithm engine control, and status interrupt as shown in Figure 33-13. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-13...
Page 784: Initialization/Application Information
MDIMR)”). If an error occurs, the MDHA core engine is halted. This prevents the core from continuing operation with invalid data. 33.4 Initialization/Application Information 33.4.1 Performing a Standard HASH Operation 1. Reset the MDHA using the MDCMR[SWR] bit. 2. MDCR register write. Enable the interrupts. (optional) MCF5329 Reference Manual, Rev 3 33-14 Freescale Semiconductor...
Page 785: Performing A Standard Hash Operation With Dma
33.4.3 Performing a HMAC Operation Without the MACFULL Bit The HMAC is done in three separate steps without the MACFULL bit. Each step requires the reinitialization of the MDHA. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-15...
Page 786 MDDSR write is not received or auto-padding is disabled and a partial message block is provided. 10. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest and the message digest count from the message digest registers. MCF5329 Reference Manual, Rev 3 33-16 Freescale Semiconductor...
Page 787: Performing A Sha-1 Ehmac
7. Direct context load of MDMDS register from the IPAD step (this should be 64 bytes). 8. Fill data FIFO with message to be hashed. 9. MDDSR register write. Load this register with the length of the message data (without padding) in bits. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-17...
Page 788: Performing A Mac Operation With The Macfull Bit
11. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers. 33.4.6 Performing an NMAC An NMAC consists of one Hash operation. 1. Reset the MDHA using the MDCMR[SWR] bit. 2. MDCR register write. Enable the interrupts. (optional) MCF5329 Reference Manual, Rev 3 33-18 Freescale Semiconductor...
Page 789 MDDSR write is not received or auto-padding is disabled and a partial message block is provided. 13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 33-19...
Page 790 Message Digest Hardware Accelerator (MDHA) MCF5329 Reference Manual, Rev 3 33-20 Freescale Semiconductor...
Page 791: Introduction
– Current time using highest precision possible – Mouse and keyboard motions (or equivalent if being used on a cell phone or PDA) – Other entropy supplied directly by the user MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 34-1...
Page 792: Memory Map/Register Definition
1 RNGA is in sleep mode. Clear interrupt. Writing a 1 to this bit clears the error interrupt and RNGSR[EI]. This bit is self-clearing, 0 Do not clear error interrupt. 1 Clear error interrupt. MCF5329 Reference Manual, Rev 3 34-2 Freescale Semiconductor...
Page 793: Rng Status Register (Rngsr)
1 FIFO read while empty. FIFO underflow. Signals FIFO underflow. Reset by reading RNGSR. 0 FIFO not read while empty since last read of RNGSR. 1 FIFO read while empty since last read of RNGSR. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 34-3...
Page 794: Rng Entropy Register (Rnger)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34-4. RNGOUT MCF5329 Reference Manual, Rev 3 34-4...
Page 795: Functional Description
The core engine block contains the logic that generates random data. The logic within the core engine contains the internal shift registers, as well as the logic that generates the two oscillator based clocks. This MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 796: Initialization/Application Information
3. Write to the RNG control register and set the interrupt mask, high assurance, and GO bits. 4. Poll RNGSR[OFL] to check for random data in the FIFO. 5. Read available random data from RNGOUT. 6. Repeat steps 3 and 4 as needed. MCF5329 Reference Manual, Rev 3 34-6 Freescale Semiconductor...
Page 797: Introduction
The processor supplies data to the SKHA, and the data is encrypted and subsequently made available to the processor via an output FIFO. The session key is input to the block prior to encryption. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 798 AES is a symmetric key algorithm, the sender and receiver use the same key for encryption and decryption. The session key and initialization vector (CBC mode) are supplied to the SKHA module prior to MCF5329 Reference Manual, Rev 3 35-2...
Page 799 Figure 35-6. A 128-bit random initialization vector (IV) must be loaded prior to processing a message. The context registers are updated internally and must be read and restored during a context switch. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-3...
Page 800 , by powers of 8 (SKMR[CTRM]). The running counter is encrypted and XOR’d with the plaintext to derive the ciphertext, or with the ciphertext to recover the plaintext as shown in Figure 35-7. MCF5329 Reference Manual, Rev 3 35-4 Freescale Semiconductor...
Page 801: Memory Map/Register Definition
0xEC08_4024 SKHA Output FIFO (SKOUT) 0x0000_0000 35.2.9/35-13 0xEC08_4030 SKHA Key Data Register 1 (SKKDR1) 0x0000_0000 35.2.10/35-13 0xEC08_4034 SKHA Key Data Register 2 (SKKDR2) 0x0000_0000 35.2.10/35-13 0xEC08_4038 SKHA Key Data Register 3 (SKKDR3) 0x0000_0000 35.2.10/35-13 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-5...
Page 802: Skha Mode Register (Skmr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 35-8. SKHA Mode Register (SKMR) MCF5329 Reference Manual, Rev 3 35-6 Freescale Semiconductor...
Page 803: Skha Control Register (Skcr)
Algorithm. Selects which algorithm the SKHA module uses. 00 AES 01 DES 10 3DES 11 Reserved 35.2.2 SKHA Control Register (SKCR) The SKCR contains bits that should be set after a hardware reset. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-7...
Page 804: Skha Command Register (Skcmr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 35-10. SKHA Command Register (SKCMR) MCF5329 Reference Manual, Rev 3 35-8...
Page 805: Skha Status Register (Sksr)
Output FIFO level. This 8-bit value indicates the number of data words in the Output FIFO. 23–16 Input FIFO level. This 8-bit value indicates the number data words in the Input FIFO. 15–5 Reserved, should be cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-9...
Page 806: Skha Error Status And Mask Registers (Skesr, Skesmr)
SKESR but the interrupt is not generated. Additional errors are flagged in the SKESR until an unmasked error is generated. NOTE Masking errors should only be used for debug purposes. A masked error most likely causes invalid data. MCF5329 Reference Manual, Rev 3 35-10 Freescale Semiconductor...
Page 807 1 Illegal data size was written into the SKHA data size register Illegal mode error 0 No error 1 Illegal mode specified Non-empty output FIFO upon start. NEOF 0 No error 1 Output FIFO contains data upon start of processing MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-11...
Page 808: Skha Key Size Register (Skksr)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 35-15. SKHA Key Size Register (SKKSR) MCF5329 Reference Manual, Rev 3 35-12...
Page 809: Skha Input Fifo (Skin)
For AES, which uses a 128-bit key, SKKDR1–SKKDR4 must be written. For single DES, SKKDR1–SKKDR2 must be written (56-bit key & 8-bit parity). For 2-key 3DES, SKKDR1–4 must be written. For 3-key 3DES, SKKDR1–6 must be written. The SKKDRn registers are summarized in Table 35-7. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-13...
Page 810: Skha Context Registers (Skc N )
SKHA Context Register n (32-bits each) Algorithm /Mode DES-ECB — — — — — — — — — — — — DES-CBC — — — — — — — — — — MCF5329 Reference Manual, Rev 3 35-14 Freescale Semiconductor...
Page 811: Functional Description
At the top level, the SKHA consists of seven functional blocks: The input FIFO, the output FIFO, transmit FIFO interface, receive FIFO interface, internal bus interface, top control and the SKHA logic. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-15...
Page 812: Transmit Fifo Interface Block
After the last word is pushed to the output FIFO, the done interrupt is asserted. 35.3.3 Top Control Block This block generates the input and output FIFO transmit, receive and request signals and translates other internal signals at the top level. MCF5329 Reference Manual, Rev 3 35-16 Freescale Semiconductor...
Page 813: Skha Logic Block
This block is the control for the input and output DMA request signals. It monitors the input and output FIFO levels and DMA request levels (SKCR[ODMAL & IDMAL]) to determine when a DMA request should be triggered to the DMA controller. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-17...
Page 814: Security Assurance Features
In this case, the SKHA must be reset to resume operation, SKCMR[SWR]. Readable registers may be accessed to determine the nature of the error. MCF5329 Reference Manual, Rev 3 35-18 Freescale Semiconductor...
Page 815: Initialization/Application Information
10. Wait for interrupt, SKSR[INT]. 11. Unload processed message data from the output FIFO. 12. Read contents of context registers, if necessary. 13. Set the SKCMR[CI] bit, to clear the done interrupt. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 35-19...
Page 816: Operation With Context Switch
20. Set number of bits in remaining part of message 1 to SKDSR. 21. Load the input FIFO with the remaining portion of message 1. 22. Set the SKCMR[GO] bit. 23. Wait for interrupt, SKSR[INT]. 24. Unload processed message data from the output FIFO. MCF5329 Reference Manual, Rev 3 35-20 Freescale Semiconductor...
Page 817: Introduction
External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See Section 36.4.2, “Real-Time Debug Support”. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-1...
Page 818: Signal Descriptions
Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. MCF5329 Reference Manual, Rev 3 36-2 Freescale Semiconductor...
Page 819: Memory Map/Register Definition
These registers are also accessed through the BDM port by the commands, WDMREG , described in Section 36.4.1.5, “BDM Command Set”. These commands contain a 5-bit field, RDMREG DRc, that specifies the register, as shown in Table 36-3. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-3...
Page 820: Shared Debug Resources
Shared Debug Resources The debug module revision A implementation provides a common hardware structure for BDM and breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown Table 36-4. MCF5329 Reference Manual, Rev 3 36-4 Freescale Semiconductor...
Page 821: Configuration/Status Register (Csr)
0x00 using the WDEBUG instruction and through the BDM port using the RDMREG WDMREG commands. DRc[4:0]: 0x00 (CSR) Access: Supervisor write-only BDM read/write BSTAT TRG HALT BKPT Reset SPD FDBG DBGH Reset Figure 36-2. Configuration/Status Register (CSR) MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-5...
Page 822 Note: When PCD is set, do not execute a wddata instruction or perform any debug captures. Doing so, hangs the device. Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. Only commands from the external development system can modify IPW. MCF5329 Reference Manual, Rev 3 36-6 Freescale Semiconductor...
Page 823 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-7...
Page 824: Bdm Address Attribute Register (Baar)
BDM write-only Reset: Figure 36-3. BDM Address Attribute Register (BAAR) Table 36-6. BAAR Field Descriptions Field Description Read/Write. 0 Write 1 Read 6–5 Size. 00 Longword 01 Byte 10 Word 11 Reserved MCF5329 Reference Manual, Rev 3 36-8 Freescale Semiconductor...
Page 825: Address Attribute Trigger Register (Aatr)
Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons. Read/Write. R is compared with the R/W signal of the processor’s local bus. 6–5 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-9...
Page 826: Trigger Definition Register (Tdr)
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. MCF5329 Reference Manual, Rev 3 36-10 Freescale Semiconductor...
Page 827 Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a L2DI trigger based on the occurrence of a data value other than the DBR contents. 0 No inversion 1 Invert data breakpoint comparators. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-11...
Page 828 Note: Debug Rev A only had the AND condition available for the triggers. Enable Level 1 Breakpoint. Global enable for the breakpoint trigger. L1EBL 0 Disables all level 1 breakpoints 1 Enables all level 1 breakpoint triggers MCF5329 Reference Manual, Rev 3 36-12 Freescale Semiconductor...
Page 829: Program Counter Breakpoint/Mask Registers (Pbr0–3, Pbmr)
PBR1–3) and TDR is configured appropriately. PBR0 bits are masked by setting corresponding PBMR bits (PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-13...
Page 830 0 PBR is disabled. 1 PBR is enabled. Figure 36-8 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the command. PBMR only masks PBR0. WDMREG MCF5329 Reference Manual, Rev 3 36-14 Freescale Semiconductor...
Page 831: Address Breakpoint Registers (Ablr, Abhr)
Address specific single addresses are programmed into ABLR. Table 36-13. ABHR Field Description Field Description 31–0 High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-15...
Page 832: Data Breakpoint And Mask Registers (Dbr, Dbmr)
DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit causes that bit to be ignored. The DBR supports aligned and misaligned references. Table 36-16 shows relationships between processor address, access size, and location within the 32-bit data bus. MCF5329 Reference Manual, Rev 3 36-16 Freescale Semiconductor...
Page 833: Functional Description
BKPT. This type of halt is always first marked as pending in the pocessor, which samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 36.4.2.1, “Theory of Operation”. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-17...
Page 834 17-bit packets composed of a status/control bit and a 16-bit data word. As shown Figure 36-12, all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is high; DSI is sampled and DSO is driven. MCF5329 Reference Manual, Rev 3 36-18 Freescale Semiconductor...
Page 835: Receive Packet Format
Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 36.4.1.3 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit Data Figure 36-13. Receive BDM Packet MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-19...
Page 836: Transmit Packet Format
All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words. Operation Op Size Register Extension Word(s) Figure 36-15. BDM Command Format MCF5329 Reference Manual, Rev 3 36-20 Freescale Semiconductor...
Page 837: Command Sequence Diagrams
17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-21...
Page 838 If a bus error terminates a memory or register access, error status (S = 1, DATA = 0x0001) returns instead of result data. MCF5329 Reference Manual, Rev 3 36-22 Freescale Semiconductor...
Page 839: Bdm Command Set
- Halted: The CPU must be halted to perform this command. - Steal: Command generates bus cycles that can be interleaved with bus accesses. - Parallel: Command is executed in parallel with CPU activity. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-23...
Page 840 The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: MCF5329 Reference Manual, Rev 3 36-24 Freescale Semiconductor...
Page 841 Command/Result Formats: Byte Command A[31:16] A[15:0] Result D[7:0] Word Command A[31:16] A[15:0] Result D[15:0] Longword Command A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 36-21. Command/Result Formats READ MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-25...
Page 842 Write data to the memory location specified by the longword address. BAAR[TT,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. MCF5329 Reference Manual, Rev 3 36-26 Freescale Semiconductor...
Page 843 Debug Module Command Formats: Byte A[31:16] A[15:0] D[7:0] Word A[31:16] A[15:0] D[15:0] Longword A[31:16] A[15:0] D[31:16] D[15:0] Figure 36-23. Command Format WRITE MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-27...
Page 844 The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the current DUMP operand size, and store the updated address in the temporary register. MCF5329 Reference Manual, Rev 3 36-28 Freescale Semiconductor...
Page 845 DUMP (LONG) MEMORY ’NOT READY’ LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD ’ILLEGAL’ ’NOT READY’ BERR ’NOT READY’ Figure 36-26. Command Sequence DUMP Operand Data: None MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-29...
Page 846 The size field is examined each time a command is processed, allowing the operand size to be altered FILL dynamically. Command Formats: Byte D[7:0] Word D[15:0] Longword D[31:16] D[15:0] Figure 36-27. Command Format FILL MCF5329 Reference Manual, Rev 3 36-30 Freescale Semiconductor...
Page 847 BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Figure 36-29. Command Format Command Sequence: NEXT CMD ’CMD COMPLETE’ Figure 36-30. Command Sequence MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-31...
Page 848 PC for performance monitoring. The SYNC execution of this command is considerably less obtrusive to the real-time operation of an application than command sequence. HALT READ RESUME Command Formats: MCF5329 Reference Manual, Rev 3 36-32 Freescale Semiconductor...
Page 849 REGISTER NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Figure 36-36. Command Sequence RCREG Operand Data: The only operand is the 32-bit Rc control register select field. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-33...
Page 850 SR[S] = 1 then A7 = Supervisor Stack Pointer OTHER_A7 = User Stack Pointer else A7 = User Stack Pointer OTHER_A7 = Supervisor Stack Pointer MCF5329 Reference Manual, Rev 3 36-34 Freescale Semiconductor...
Page 851 See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 36-37. Command/Result Formats WCREG MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-35...
Page 852 Command/Result Formats: Command Result D[31:16] D[15:0] Figure 36-39. Command/Result Formats RDMREG Table 36-22 shows the definition of DRc encoding. Table 36-22. Definition of DRc Encoding—Read DRc[4:0] Debug Register Definition Mnemonic 0x00 Configuration/Status MCF5329 Reference Manual, Rev 3 36-36 Freescale Semiconductor...
Page 853 WDMREG Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Result Data: Command complete status (0xFFFF) is returned when register write is complete. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-37...
Page 854: Real-Time Debug Support
(PST = 0xF). If the processor core cannot be halted, the debug interrupt can be used. With this configuration, TDR[TRC] equals 10, breakpoint trigger becomes a debug interrupt to the processor, which is treated MCF5329 Reference Manual, Rev 3 36-38 Freescale Semiconductor...
Page 855 TT equals 0x2, TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that forced entry into this mode. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-39...
Page 856: Concurrent Bdm And Processor Operation
This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to MCF5329 Reference Manual, Rev 3 36-40...
Page 857 PST port one PSTCLK cycle before the data is displayed on DDATA. 0x8 Begin 1-byte transfer on DDATA. 0x9 Begin 2-byte transfer on DDATA. 0xA Begin 3-byte transfer on DDATA. 0xB Begin 4-byte transfer on DDATA. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-41...
Page 858 Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 36-43 shows the PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to display the lower 2 bytes of an address. MCF5329 Reference Manual, Rev 3 36-42 Freescale Semiconductor...
Page 859: Debug Translate Block
For example, two PST = 0xC values can be compressed into a single PST = 0xC. Debug Translate Disabled: PSTCLK PST/DDATA Debug Translate Enabled: Internal Core Clock PSTCLK PST/DDATA Figure 36-44. Debug Translate Timing MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-43...
Page 860: Processor Status, Debug Data Definition
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bclr.{b,l} Dy,<ea>x PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bitrev.l PST = 0x1 MCF5329 Reference Manual, Rev 3 36-44 Freescale Semiconductor...
Page 861 PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} move.w <ea>y,<ea>x PST = 0x1, {PST = 0x9, DD = source}, {PST = 0x9, DD = destination} MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-45...
Page 862 PST = 0x1 subq.l #<data>,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} subx.l Dy,Dx PST = 0x1 swap.w PST = 0x1 PST = 0x1 MCF5329 Reference Manual, Rev 3 36-46 Freescale Semiconductor...
Page 863 PST/DDATA specification for multiply-accumulate instructions. Table 36-26. PST/DDATA Values for User-Mode Multiply-Accumulate Instructions Instruction Operand Syntax PST/DDATA mac.l Ry,Rx,ACCx PST = 0x1 mac.l Ry,Rx,<ea>y,Rw,ACCx PST = 0x1, {PST = 0xB, DD = source operand} MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-47...
Page 864: Supervisor Instruction Set
PST = 0x1, PST = 0xF move.l Ay,USP PST = 0x1 move.l USP,Ax PST = 0x1 move.w SR,Dx PST = 0x1 move.w {Dy,#<data>},SR PST = 0x1, {PST = 0x3} movec.l Ry,Rc PST = 0x1 MCF5329 Reference Manual, Rev 3 36-48 Freescale Semiconductor...
Page 865: Freescale-Recommended Bdm Pinout
Developer reserved RESET EVDD PST3 PST2 PST1 PST0 DDATA3 DDATA1 DDATA2 DDATA0 Freescale reserved Freescale reserved PSTCLK IVDD Pins reserved for BDM developer use. Supplied by target Figure 36-45. Recommended BDM Connector MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 36-49...
Page 866 Debug Module MCF5329 Reference Manual, Rev 3 36-50 Freescale Semiconductor...
Page 867: Introduction
1-bit TEST_CTRL Register 5-bit TAP Instruction Decoder 5-bit TAP Instruction Register JTAG_EN TCLK Disable DSCLK TMS/BKPT Force BKPT = 1 TRST/DSCLK JTAG Module to Debug Module BKPT DSCLK Figure 37-1. JTAG Block Diagram MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 37-1...
Page 868: Features
The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is selected; if it is high, the JTAG is selected. Table 37-2 summarizes the pin function selected depending on JTAG_EN logic state. MCF5329 Reference Manual, Rev 3 37-2 Freescale Semiconductor...
Page 869: Test Clock Input (Tclk)
The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 37-3...
Page 870: Test Reset/Development Serial Clock (Trst/Dsclk)
TDO pin. See Section 37.4.3, “JTAG Instructions” for a list of possible instruction codes. TAP state: Update-IR Access: User read/write Instruction Code Reset Figure 37-2. 5-Bit Instruction Register (IR) MCF5329 Reference Manual, Rev 3 37-4 Freescale Semiconductor...
Page 871: Idcode Register
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state. The DSE bit selects the drive strength used in JTAG mode. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 37-5...
Page 872: Boundary Scan Register
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As Figure 37-5 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MCF5329 Reference Manual, Rev 3 37-6 Freescale Semiconductor...
Page 873: Jtag Instructions
Selects IDCODE register for shift SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing functional operation MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 37-7...
Page 874: Idcode Instruction
IR contains the 0x2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. The data capture and the shift operation are transparent to system operation. MCF5329 Reference Manual, Rev 3 37-8 Freescale Semiconductor...
Page 875 Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor 37-9...
Page 876: Initialization/Application Information
However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. MCF5329 Reference Manual, Rev 3 37-10 Freescale Semiconductor...
Page 877: A.1 Register Memory Map
(e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-chacheable, and one ACR is then used to identify cacheable addresses, e.g., ADDR[31]=0 identifies the cacheable space. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 878 Table A-21, 0xFC0A_0000 CCM, Reset Controller, Power Management Table A-22, Table A-23 0xFC0A_4000 GPIO Module Table A-24 0xFC0A_8000 Real Time Clock Table A-25 0xFC0A_C000 LCD Controller Table A-26 0xFC0B_0000 USB On-the-Go Table A-27 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 879 MAC Accumulators 0–3 (ACC0–3) Undefined 4.2.3/4-6 0x80A, 0x80B 0x807 MAC Accumulator 0,1 Extension Bytes Undefined 4.2.4/4-7 (ACCext01) 0x808 MAC Accumulator 2,3 Extension Bytes Undefined 4.2.4/4-7 (ACCext23) 0x80E Condition Code Register (CCR) Undefined 3.2.4/3-7 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 880 PC breakpoint register 2 (PBR2) See Section 36.3.6/36-13 0x1B PC breakpoint register 3 (PBR3) See Section 36.3.6/36-13 Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care). MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 881 Undefined 11.2.11/11-12 0xFC04_0077 Core Fault Attributes Register (CFATR) Undefined 11.2.12/11-12 0xFC04_007C Core Fault Data Register (CFDTR) Undefined 11.2.13/11-13 Take note of register location. The WCR register is described in Chapter 8, “Power Management.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 882 0xFC02_0008 Free Running Timer (TIMER) 0x0000_0000 23.3.3/23-10 0xFC02_0010 Rx Global Mask (RXGMASK) 0x1FFF_FFFF 23.3.4/23-11 0xFC02_0014 Rx Buffer 14 Mask (RX14MASk) 0x1FFF_FFFF 23.3.4/23-11 0xFC02_0018 Rx Buffer 15 Mask (RX15MASK) 0x1FFF_FFFF 23.3.4/23-11 0xFC02_001C Error Counter Register (ERRCNT) 0x0000_0000 23.3.5/23-12 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 883 FIFO Receive FIFO Start Register (FRSR) 0x0000_0500 19.4.21/19-22 0xFC03_0180 Pointer to Receive Descriptor Ring (ERDSR) Undefined 19.4.22/19-23 0xFC03_0184 Pointer to Transmit Descriptor Ring (ETDSR) Undefined 19.4.23/19-23 0xFC03_0188 Maximum Receive Buffer Size (EMRBR) Undefined 19.4.24/19-24 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 884 Interrupt Force Register Low (INTFRCL0) 0x0000_0000 14.2.3/14-6 0xFC04_801A Interrupt Configuration Register (ICONFIG) 0x0000 14.2.4/14-7 0xFC04_801C Set Interrupt Mask (SIMR0) 0x00 14.2.5/14-8 0xFC04_801D Clear Interrupt Mask (CIMR0) 0x00 14.2.6/14-9 0xFC04_801E Current Level Mask (CLMASK) 0x0F 14.2.7/14-9 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 885 0xFC05_8004 I C Frequency Divider Register (I2FDR) 0x00 32.2.2/32-3 0xFC05_8008 I C Control Register (I2CR) 0x00 32.2.3/32-4 0xFC05_800C I C Status Register (I2SR) 0x81 32.2.4/32-5 0xFC05_8010 I C Data I/O Register (I2DR) 0x00 32.2.5/32-6 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 886 31.3.10/31-13 0xFC06_4014 UART Interrupt Mask Register (UIMRn) 0x00 31.3.10/31-13 0xFC06_8014 0xFC06_0018 UART Baud Rate Generator Register (UBG1n) 0x00 31.3.11/31-15 0xFC06_4018 0xFC06_8018 0xFC06_001C UART Baud Rate Generator Register (UBG2n) 0x00 31.3.11/31-15 0xFC06_401C 0xFC06_801C MCF5329 Reference Manual, Rev 3 A-10 Freescale Semiconductor...
Page 887 DMA Timer n Extended Mode Register (DTXMRn) 0x00 29.2.2/29-4 0xFC07_4002 0xFC07_8002 0xFC07_C002 0xFC07_0003 DMA Timer n Event Register (DTERn) 0x00 29.2.3/29-5 0xFC07_4003 0xFC07_8003 0xFC07_C003 0xFC07_0004 DMA Timer n Reference Register (DTRRn) 0xFFFF_FFFF 29.2.4/29-6 0xFC07_4004 0xFC07_8004 0xFC07_C004 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-11...
Page 888 User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. Table A-18. PWM Memory Map Width Address Register Access Reset Value Section/Page (bits) 0xFC09_0020 PWM Enable Register (PWME) 0x00 26.2.1/26-3 0xFC09_0021 PWM Polarity Register (PWMPOL) 0x00 26.2.2/26-4 MCF5329 Reference Manual, Rev 3 A-12 Freescale Semiconductor...
Page 889 15.4.4/15-5 0xFC09_4005 EPORT Pin Data Register (EPPDR) See Section 15.4.5/15-5 0xFC09_4006 EPORT Flag Register (EPFR) 0x00 15.4.6/15-6 User access to supervisor-only address locations have no effect and result in a bus error. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-13...
Page 890 0xFC0A_0001 Reset Status Register (RSR) See Section 10.3.2/10-3 Table A-23. Power Management Memory Map Width Address Register Access Reset Value Section/Page (bits) Supervisor Access Only Registers 0xFC04_0013 Wakeup Control Register (WCR) 0x00 8.2.1/8-2 MCF5329 Reference Manual, Rev 3 A-14 Freescale Semiconductor...
Page 891 0xFC0A_4009 PODR_UART 0xFF 13.3.1/13-14 0xFC0A_400A PODR_QSPI 0x3F 13.3.1/13-14 0xFC0A_400B PODR_TIMER 0x0F 13.3.1/13-14 0xFC0A_400D PODR_LCDDATAH 0x03 13.3.1/13-14 0xFC0A_400E PODR_LCDDATAM 0xFF 13.3.1/13-14 0xFC0A_400F PODR_LCDDATAL 0xFF 13.3.1/13-14 0xFC0A_4010 PODR_LCDCTLH 0x01 13.3.1/13-14 0xFC0A_4011 PODR_LCDCTLL 0xFF 13.3.1/13-14 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-15...
Page 892 See Section 13.3.3/13-19 0xFC0A_4031 PPDSDR_UART See Section 13.3.3/13-19 0xFC0A_4032 PPDSDR_QSPI See Section 13.3.3/13-19 0xFC0A_4033 PPDSDR_TIMER See Section 13.3.3/13-19 0xFC0A_4035 PPDSDR_LCDDATAH See Section 13.3.3/13-19 0xFC0A_4036 PPDSDR_LCDDATAM See Section 13.3.3/13-19 0xFC0A_4037 PPDSDR_LCDDATAL See Section 13.3.3/13-19 MCF5329 Reference Manual, Rev 3 A-16 Freescale Semiconductor...
Page 893 0xFC0A_4054 PAR_BE 0x0F 13.3.5.2/13-24 0xFC0A_4055 PAR_CS 0x3E 13.3.5.3/13-25 0xFC0A_4056 PAR_SSI 0x0000 13.3.5.10/13-30 0xFC0A_4058 PAR_UART 0x0000 13.3.5.7/13-28 0xFC0A_405A PAR_QSPI 0x0000 13.3.5.5/13-26 0xFC0A_405C PAR_TIMER 0x00 13.3.5.6/13-27 0xFC0A_405D PAR_LCDDATA 0x00 13.3.5.12/13-32 0xFC0A_405E PAR_LCDCTL 0x0000 13.3.5.13/13-33 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-17...
Page 894 25.3.6/25-6 0xFC0A_8018 RTC Interrupt Enable Register (RTC_IER) 0x0000_0000 25.3.7/25-7 0xFC0A_801C Stopwatch Minutes Register (RTC_STPWCH) 0x0000_003F 25.3.8/25-8 0xFC0A_8020 RTC Days Counter Register (RTC_DAYS) 0x0000_0000 25.3.9/25-9 0xFC0A_8024 RTC Days Alarm Register (RTC_ALRM_DAY) 0x0000_0000 25.3.10/25-9 MCF5329 Reference Manual, Rev 3 A-18 Freescale Semiconductor...
Page 895 0xFC0A_C064 LCD Graphic Window Control Register (LCD_GWCR) 0x0000_0000 22.3.23/22-24 0xFC0A_C068 LCD Graphic Window DMA Control Register 0x8010_0004 22.3.24/22-26 (LCD_GWDCR) 0xFC0A_C800 Background Look-up Table (BGLUT) — 22.3.25/22-26 0xFC0A_CBFC 0xFC0A_CC00 Graphic Window Look-up Table (GWLUT) — 22.3.25/22-26 0xFC0A_CFFC MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-19...
Page 896 21.3.3.12/21-29 0xFC0B_0180 Configure Flag Register (CONFIGFLAG) 0x0000_0001 21.3.3.13/21-31 0xFC0B_0184 Port Status/Control (PORTSC1) R/W 0xEC00_0004 21.3.3.14/21-31 0xFC0B_01A4 On-The-Go Status and Control (OTGSC) R/W 0x0000_1020 21.3.3.15/21-35 0xFC0B_01A8 USB Mode Register (MODE) R/W 0x0000_0000 21.3.3.16/21-38 MCF5329 Reference Manual, Rev 3 A-20 Freescale Semiconductor...
Page 897 USB Status (USBSTS) R/W 0x0000_1000 21.3.3.2/21-19 0xFC0B_4148 USB Interrupt Enable (USBINTR) R/W 0x0000_0000 21.3.3.3/21-21 0xFC0B_414C USB Frame Index (FRINDEX) R/W 0x0000_0000 21.3.3.4/21-23 0xFC0B_4154 Periodic Frame List Base Address (PERIODICLISTBASE) R/W 0x0000_0000 21.3.3.5/21-24 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-21...
Page 898 0xFC0B_C01C SSI Transmit Configuration Register (SSI_TCR) 0x0000_0200 24.3.10/24-21 0xFC0B_C020 SSI Receive Configuration Register (SSI_RCR) 0x0000_0200 24.3.11/24-23 0xFC0B_C024 SSI Clock Control Register (SSI_CCR) 0x0004_0000 24.3.12/24-24 0xFC0B_C02C SSI FIFO Control/Status Register (SSI_FCSR) 0x0081_0081 24.3.13/24-25 MCF5329 Reference Manual, Rev 3 A-22 Freescale Semiconductor...
Page 899 0xEC08_0038 MDHA Message Digest C0 Register (MDC0) 0xFEDC_BA98 33.2.8/33-11 0xEC08_003C MDHA Message Digest D0 Register (MDD0) 0x7654_3210 33.2.8/33-11 0xEC08_0040 MDHA Message Digest E0 Register (MDE0) 0xF0E1_D2C3 33.2.8/33-11 0xEC08_0044 MDHA Message Data Size Register (MDMDS) 0x0000_0000 33.2.9/33-12 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-23...
Page 900 0xEC08_4078 SKHA Context 3 (SKC3) 0x0000_0000 35.2.11/35-14 0xEC08_407C SKHA Context 4 (SKC4) 0x0000_0000 35.2.11/35-14 0xEC08_4080 SKHA Context 5 (SKC5) 0x0000_0000 35.2.11/35-14 0xEC08_4084 SKHA Context 6 (SKC6) 0x0000_0000 35.2.11/35-14 0xEC08_4088 SKHA Context 7 (SKC7) 0x0000_0000 35.2.11/35-14 MCF5329 Reference Manual, Rev 3 A-24 Freescale Semiconductor...
Page 901 Access Reset Value Section/Page (bits) 0xEC08_8000 RNG Control Register (RNGCR) 0x0000_0000 34.2.1/34-2 0xEC08_8004 RNG Status Register (RNGSR) 0x0010_0000 34.2.2/34-3 0xEC08_8008 RNG Entropy Register (RNGER) 0x0000_0000 34.2.3/34-4 0xEC08_800C RNG Output FIFO (RNGOUT) 0x0000_0000 34.2.4/34-4 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor A-25...
Page 902 Register Memory Map Quick Reference MCF5329 Reference Manual, Rev 3 A-26 Freescale Semiconductor...
Page 903: B.1 Changes Between Rev. 2 And Rev. 3
Corrected MCF53281 column in features list table. This device contains FlexCAN but does not have cryptography accelerators. Signal In Signal Information and Muxing table, moved MCF53281 label from the MCF5328 column to the MCF5329 Descriptions column, because this device contains CAN output signals.
Page 904 Corrected reset values of the PDDR_x registers to 0x00. Corrected stem sentence in PAR_UART section. In Signal Information and Muxing Table, moved MCF53281 label from the MCF5328 column to the MCF5329 column, because this device contains CAN output signals. Corrected pinouts in Signal Information and Muxing Table for 196 MAPBGA device: Changed D[15:1] entry from “F4–F1, G4–G2...”...
Page 905 Added note in Interrupt/Bulk Endpoint Operation section, in third bullet under “RX-dTD is complete when:” Added second note to Software Link Pointers section. Added the following dTD Token[Total Bytes] field description: “For OUT transfers the total bytes must be evenly divisible by the maximum packet length.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 906 Reworded note below UART block diagram. Corrected note in UIPn[CTS] bit description from “...and value as UIPCRn[RTS].” to “...and value as UIPCRn[CTS].” Added note in overview section. Added link to NIST SP800-90 in the overview section. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 907: B.2 Changes Between Rev. 1 And Rev. 2
Table 2-10/Page 2-13: Change LCD_SCLK to LCD_LSCLK to be consistent with the rest of the reference manual. Table 2-16/Page 2-17: Change USBOTG_PU_EN to an output and change the description to the following: Enables an external pull-up on the USBOTG_DP line. This signal is controlled by the UOCSR[BVLD] bit. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 908 0x00 and 0xFF. All other values are reserved. Added last sentence to first paragraph in PACRx section, “At reset the SCM (PACR0) does not allow access from untrusted masters, while the other peripherals do.” MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 909 Added ICR000, ICR100, ICR200 to register addresses and section heading in ICRn section. Added verb “exists” to notes in CLMASK and SLMASK sections. DMA Controller Added second paragraph to Modes of Operation, Normal Mode section. Added note to TCDn_CSR[BWC] field description. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 910 SD_DQS2, and so on.” to ““The DSQ_OE[1] bit enables SD_DQS3 and the DSQ_OE[0] bit enables SD_DQS2.” Consequently, the reserved bit field currently at location 7–3 should be extended to bits 9–3. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 911 (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is programmable. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor...
Page 912 On those cases we recommend to disable the ZLT feature, and use software to generate the zero length termination.” MCF5329 Reference Manual, Rev 3 B-10 Freescale Semiconductor...
Page 913 Figure 28-4/Page 28-5: Remove “IPSBAR Offset” from PCNTRn register diagram. DMA Timers Corrected DTRRn reset value in timer memory map from 0x1111_1111 to 0xFFFF_FFFF. QSPI Removed mention of QSPI_CS3 throughout as it is not available on this device. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor B-11...
Page 914: B.3 Changes Between Rev. 0.1 And Rev. 1
Remove FEC signals as alternate 1 function of the LCD pins. The FEC signals are available as primary functions on other pins. Table 2-1/Page 2-7 Change USBHOST_VSS entry to USB_VSS and USBOTG_VDD entry to USB_VDD. MCF5329 Reference Manual, Rev 3 B-12 Freescale Semiconductor...
Page 915 Section 11.2.8/Page 11-10 Change last sentence in first paragraph from “There is a enable bit...” to “There is an enable bit...” Figure 11-22/Page 11-14 Change CFDTR register address from 0xFC04_0078 to 0xFC04_007C. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor B-13...
Page 916 (e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-chacheable, and one ACR is then used to identify cacheable addresses, e.g., ADDR[31]=0 identifies the cacheable space. MCF5329 Reference Manual, Rev 3 B-14 Freescale Semiconductor...
Page 917 5 and 9 of Section 18.6, “Initialization/Application Information.” This is not recommended or necessary. Table 19-2/Page 19-5 Change reset value of ECR register from 0x0000_0000 to 0xF000_0002. MCF5329 Reference Manual, Rev 3 Freescale Semiconductor B-15...
Page 918 Clarify in CSR field descriptions that the read-only bits can only be accessed via the BDM port and not read via the processor. The CSR is supervisor write-only from the processor. Appendix A Added memory map appendix. MCF5329 Reference Manual, Rev 3 B-16 Freescale Semiconductor...
Page 919: B.4 Changes Between Rev. 0 And Rev. 0.1
SSI mode only. Configured by the MISCCR register in the CCM SSI_TXD SSI mode only. Configured by the MISCCR register in the CCM JTAG_EN JTAG mode only JTAG mode only TRST JTAG mode only TCLK JTAG mode only MCF5329 Reference Manual, Rev 3 Freescale Semiconductor B-17...
Page 920 Remove “All Processor Status Outputs” entry row because the ALLPST signal is not present. Table 2-19/Page 2-15 Remove “ALLPST” column in table as well as “(MCF5372 & MCF5373)” in the PST[3:0] column heading. MCF5329 Reference Manual, Rev 3 B-18 Freescale Semiconductor...
Page 921 “...if a longword is transferred for three port sizes when not in split bus mode.” Figure 19-24/Page 19-23 Correct EMRBR register address from 0xFC03_01B8 to 0xFC03_0188 MCF5329 Reference Manual, Rev 3 Freescale Semiconductor B-19...
Page 922 Section 26.2/Page 26-2 Add a 0x20 offset to all PWM register addresses throughout section. Register addresses should be from 0xFC09_0020 to 0xFC09_0044. Table 36-21/Page 36-35 Remove 1 from RAMBAR register name and mnemonic. MCF5329 Reference Manual, Rev 3 B-20 Freescale Semiconductor...
Page 923 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) Crossbar Switch (XBS) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) Enhanced Direct Memory Access (eDMA) FlexBus SDRAM Controller (SDRAMC)
Page 924 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) Crossbar Switch (XBS) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) Enhanced Direct Memory Access (eDMA) FlexBus SDRAM Controller (SDRAMC)