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14.2.11 Core Fault Data Register (CFDTR)
The CFDTR is a read-only register for capturing the data associated with the last faulted processor write
data access from the device's internal bus. The CFDTR is valid only for faulted internal bus-write accesses,
CFLOC[LOC] is cleared.
Address: 0xFC04_007C (CFDTR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Field
31–0
Contains data associated with the faulting access of the last internal bus write access. Contains the data value taken
CFDTR
directly from the write data bus.
14.3
Functional Description
14.3.1
Access Control
The SCM supports the traditional model of two privilege levels: supervisor and user. Typically, memory
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
The SCM further partitions the access-control functions into two parts: one control register defines the
privilege level associated with each bus master (MPR), and another set of control registers define the
access levels associated with the peripheral modules (PACRx).
Each bus transaction targeted for the peripheral space is first checked to see if its privilege rights allow
access to the given memory space. If the privilege rights are correct, the access proceeds on the internal
bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately
aborted and terminated with an exception, and the targeted module not accessed.
14.3.2
Core Watchdog Timer
The core watchdog timer (CWT) prevents system lockup if the software becomes trapped in a loop with
no controlled exit or if a bus transaction becomes hung. The core watchdog timer can be enabled through
CWCR[CWE]; it is disabled at reset. If enabled, the CWT requires the periodic execution of a core
watchdog servicing sequence. If this periodic servicing action does not occur, the timer expires and,
depending on the setting of CWCR[CWRI], different events may occur:
•
An interrupt may be generated to the core.
•
An immediate system reset.
Freescale Semiconductor
Figure 14-19. Core Fault Data Register (CFDTR)
Table 14-13. CFDTR Field Descriptions
Description
8
CFDTR
System Control Module (SCM)
Access: User read-only
7
6
5
4
3
2
1
0
14-13
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