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DMA Serial Peripheral Interface (DSPI)
Field
7–1
Reserved, must be cleared.
0
Halt. Starts and stops DSPI transfers. See
HALT
operation of this bit.
0 Start transfers
1 Stop transfers
31.3.2
DSPI Transfer Count Register (DSPI_TCR)
The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. Do not write to the DSPI_TCR while the DSPI is running.
Address: 0xFC05_C008 (DSPI_TCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
Reset 0
0
0
0
0
Field
31–16
SPI transfer counter. Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field increments every
SPI_TCNT
time the last bit of an SPI frame transmits. A value written to SPI_TCNT presets the counter to that value.
SPI_TCNT is reset to 0 at the beginning of the frame when the CTCNT field is set in the executing SPI command.
The transfer counter wraps around. Incrementing the counter past 65535 resets the counter to 0.
15–0
Reserved, must be cleared
31.3.3
DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn)
DSPI modules each contain eight clock and transfer attribute registers (DSPI_CTARn) used to define
different transfer attribute configurations. Each DSPI_CTAR controls:
•
Frame size
•
Baud rate and transfer delay values
•
Clock phase
•
Clock polarity
•
MSB/LSB first
DSPI_CTARs support compatibility with the QSPI module in the ColdFire family of MCUs. At the
initiation of an SPI transfer, control logic selects the DSPI_CTAR that contains the transfer's attributes.
Do not write to the DSPI_CTARs while the DSPI is running.
31-8
Table 31-3. DSPI_MCR Field Descriptions (continued)
Section 31.4.1, "Start and Stop of DSPI
SPI_TCNT
0
0
0
0
0
0
0
0
Figure 31-3. DSPI Transfer Count Register (DSPI_TCR)
Table 31-4. DSPI_TCR Field Descriptions
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Transfers," for details on the
Access: User read/write
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Freescale Semiconductor
2
1
0
0
0
0
0
0
0
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