Page 1: Mpc5200B Users Guide
MPC5200B Users Guide Document Number: MPC5200BUG Rev. 1 05/2005...
Page 2: Table Of Contents
Chapter 4 Resets and Reset Configuration Overview ...4-1 Hard and Soft Reset Pins ...4-1 4.2.1 Power-On Reset—PORESET ...4-1 Freescale Semiconductor Table of Contents Chapter 1 Introduction C) ...1-7 Chapter 2 Signal Descriptions Chapter 3 Memory Map MPC5200B Users Guide, Rev. 1 Page Number TOC-1...
Page 3 MPC5200 G2_LE Processor Core Functional Overview ...6-1 G2_LE Core Reference Manual ...6-2 Not supported G2_LE Core Feature ...6-2 6.4.1 Not supported instruction ...6-2 6.4.2 Not supported XLB parity feature ...6-2 TOC-2 Chapter 6 G2_LE Processor Core MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 4 GPS GPIO Simple Interrupt Interrupt Enable Register —MBAR + 0x0B30 ...7-42 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register —MBAR + 0x0B34 ...7-43 7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 ...7-44 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-3...
Page 5 External Signals (SDRAM Side) ...8-11 8.4.2 Block Diagram ...8-12 8.4.3 Transfer Size ...8-12 8.4.4 Commands ...8-13 8.4.4.1 Load Mode/Extended Mode Register Command ...8-13 8.4.4.2 Precharge All Banks Command ...8-14 TOC-4 Chapter 8 SDRAM Memory Controller MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 6 LPC Rx/Tx FIFO Data Word Register—MBAR + 0x3C40 ...9-28 9.7.4.2 LPC Rx/Tx FIFO Status Register—MBAR + 0x3C44 ...9-28 9.7.4.3 LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48 ...9-29 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-5...
Page 7 Tx Packet Size PCITPSR(RW) —MBAR + 0x3800 ...10-22 10.3.3.1.2 Tx Start Address PCITSAR(RW) —MBAR + 0x3804 ...10-22 10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 ...10-22 TOC-6 Chapter 10 PCI Controller MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 8 10.4.5.2 Local Memory Writes ...10-55 10.4.5.3 Data Translation ...10-55 10.4.5.4 Target Abort ...10-56 10.4.5.5 Latrule Disable ...10-56 10.4.6 Communication Sub-System Initiator Interface ...10-56 10.4.6.1 Access Width ...10-57 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-7...
Page 9 ATA Drive Device Control Register—MBAR + 0x3A5C ...11-12 11.3.3.2 ATA Drive Alternate Status Register—MBAR + 0x3A5C ...11-13 11.3.3.3 ATA Drive Data Register—MBAR + 0x3A60 ...11-13 11.3.3.4 ATA Drive Features Register—MBAR + 0x3A64 ...11-14 TOC-8 Chapter 11 ATA Controller MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 10 USB HC Interrupt Disable Register—MBAR + 0x1014 ...12-11 12.4.3 Memory Pointer Partition—MBAR + 0x1018 ...12-12 12.4.3.1 USB HC HCCA Register—MBAR + 0x1018 ...12-13 Freescale Semiconductor Chapter 12 Universal Serial Bus (USB) MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-9...
Page 11 13.12.19 SDMA Initiator Priority 12 Register—MBAR + 0x1248 ...13-15 13.12.20 SDMA Initiator Priority 16 Register—MBAR + 0x124C ...13-16 13.12.21 SDMA Initiator Priority 20 Register—MBAR + 0x1250 ...13-17 TOC-10 chapter 13 BestComm MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 12 14.5.14 FEC Physical Address High Register—MBAR + 0x30E8 ...14-23 14.5.15 FEC Opcode/Pause Duration Register—MBAR + 0x30EC ...14-23 14.5.16 FEC Descriptor Individual Address 1 Registe—MBAR + 0x3118 ...14-24 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-11...
Page 13 Auxiliary Control Register (0x10) — ACR ...15-17 15.2.10 Interrupt Status Register (0x14) — ISR ...15-18 15.2.11 Interrupt Mask Register (0x14)—IMR ...15-18 15.2.12 Counter Timer Upper Register (0x18)—CTUR ...15-19 15.2.13 Counter Timer Lower Register (0x1C)—CTLR ...15-20 TOC-12 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 14 PSC in AC97 Mode ...15-55 15.3.3.1 Block Diagram and Signal Definition for AC97 Mode ...15-56 15.3.3.2 Transmitting and Receiving in AC97 Mode ...15-57 15.3.3.3 AC97 Low-Power Mode ...15-57 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-13...
Page 15 16.2.11 Arbiter Master Priority Register (R/W)—MBAR + 0x1F68 ...16-11 16.2.12 Arbiter Snoop Window Register (RW)—MBAR + 0x1F70 ...16-11 16.2.13 Arbiter Reserved Registers—MBAR + 0x1F00-1F3C, 0x1F74-1FFF ...16-13 TOC-14 Chapter 16 XLB Arbiter MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 16 CAN System ...19-2 19.5 Memory Map / Register Definition ...19-3 19.5.1 Module Memory Map ...19-3 19.5.2 Register Descriptions ...19-5 19.5.3 MSCAN Control Register 0 (CANCTL0)—MBAR + 0x0900 ...19-5 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-15...
Page 17 Description of Interrupt Operation ...19-36 19.7.9.1 Transmit Interrupt ...19-36 19.7.9.2 Receive Interrupt ...19-36 19.7.9.3 Wake-Up Interrupt ...19-36 19.7.9.4 Error Interrupt ...19-37 19.7.10 Interrupt Acknowledge ...19-37 19.7.11 Recovery from STOP or WAIT ...19-37 TOC-16 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 18 20.8.7 Receiving An In-Frame Response (IFR) ...20-43 20.8.7.1 Receiving an IFR with the BDLC module ...20-44 20.8.7.2 Receiving IFR Exceptions ...20-45 20.8.8 Special BDLC Module Operations ...20-45 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Table of Contents Page Number TOC-17...
Page 19 21.8.2 BYPASS ...21-8 21.8.3 SAMPLE/PRELOAD ...21-8 21.8.4 EXTEST ...21-9 21.8.5 CLAMP ...21-9 21.8.6 HIGHZ ...21-9 21.9 G2_LE COP/BDM Interface ...21-9 TOC-18 Appendix A Acronyms and Terms Appendix B List of Registers MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 20 Timing Diagram—Non-Data Command (Class 3) ...11-32 11-8 Flow Diagram—DMA Command Protocol ...11-34 11-9 Timing Diagram—DMA Command (Class 4) ...11-35 11-10 Timing Diagram—Reset Timing ...11-37 12-1 USB Focus Areas ...12-1 Freescale Semiconductor List of Figures Cs) ...2-67 MPC5200B Users Guide, Rev. 1 Page Number LOF-1...
Page 21 MSCAN Clocking Scheme ...19-31 19-8 Segments within the Bit Time ...19-32 19-9 Sleep Request / Acknowledge Cycle ...19-34 19-10 Simplified State Transitions for Entering/Leaving Sleep Mode ...19-35 LOF-2 C Module ...18-2 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 22 Generic TAP Link Module (TLM) Diagram ...21-3 21-3 Generic Slave TAP ...21-4 21-4 State Diagram—TAP Controller ...21-6 21-5 G2_LE Core JTAG/COP Serial Interface ...21-7 21-6 COP Connector Diagram ...21-11 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 List of Figures Page Number LOF-3...
Page 23: Freescale Semiconductor
List of Figures Notes MPC5200B Users Guide, Rev. 1 LOF-4 Freescale Semiconductor...
Page 24: List Of Tables
5-15 CDM Clock Control Sequencer Configuration Register ...5-18 5-16 CDM Soft Reset Register ...5-19 5-17 CDM System PLL Status Register ...5-19 5-18 CDM PSC1 Mclock Config ...5-20 Freescale Semiconductor List of Tables MPC5200B Users Guide, Rev. 1 Page Number LOT-1...
Page 25: Freescale Semiconductor
GPW WakeUp GPIO Status Register ...7-53 7-47 GPT 0 Enable and Mode Select Register ...7-55 7-48 GPT 0 Counter Input Register ...7-58 7-49 GPT 0 PWM Configuration Register ...7-59 7-50 GPT 0 Status Register ...7-60 LOT-2 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 26 PCI I/O space byte decoding ...10-46 10-7 XLB bus to PCI Byte Lanes for Memory Transactions ...10-49 10-8 Type 0 Configuration Device Number to IDSEL Translation ...10-52 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 List of Tables Page Number LOT-3...
Page 27: Features
USB HC Command Status Register ...12-8 12-4 USB HC Interrupt Status Register ...12-9 12-5 USB HC Interrupt Enable Register ...12-10 12-6 USB HC Interrupt Disable Register ...12-11 12-7 USB HC HCCA Register ...12-13 LOT-4 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 28 Comparator 2 Type Bit Encoding ...13-25 13-35 EU Breakpoint encoding ...13-25 13-36 SDMA Debug Module Status Register ...13-25 13-37 Behavior of Task Table Control Bits ...13-28 13-38 Variable Table per Task ...13-29 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 List of Tables Page Number LOT-5...
Page 29: Overview
Mode Register 1 (0x00) for other Modes ...15-5 15-6 Parity Mode/Parity Type Definitions ...15-6 15-7 Mode Register 2 (0x00) for UART / SIR Mode ...15-6 15-8 Mode Register 2 (0x00) for other Modes ...15-6 LOT-6 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 30 Rx FIFO Write Pointer (0x76) ...15-35 15-60 Rx FIFO Last Read Frame (0x7A) ...15-35 15-61 Rx FIFO Last Write Frame PTR (0x7C) ...15-36 15-62 Tx FIFO STAT (0x84) ...15-36 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 List of Tables Page Number LOT-7...
Page 31: Freescale Semiconductor
SPI Port Data Register ...17-7 17-11 SPI Data Direction Register ...17-7 18-1 C Terminology ...18-2 18-2 C Address Register ...18-5 18-3 C Frequency Divider Register ...18-6 18-4 C Tap and Prescale Values ...18-6 LOT-8 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 32 BDLC Transmitter VPW Symbol Timing for Integer Frequencies ...20-19 20-14 BDLC Transmitter VPW Symbol Timing for Binary Frequencies ...20-20 20-15 BDLC Receiver VPW Symbol Timing for Integer Frequencies ...20-20 Freescale Semiconductor MPC5200B Users Guide, Rev. 1 List of Tables Page Number LOT-9...
Page 33: Freescale Semiconductor
IFR Control Bit Priority Encoding ...20-38 21-1 TLM Link-DR Instructions ...21-7 21-2 TLM Test Instruction Encoding ...21-8 21-3 Device ID Register = 0001101D hex ...21-8 21-4 COP/BDM Interface Signals ...21-9 LOT-10 MPC5200B Users Guide, Rev. 1 Page Number Freescale Semiconductor...
Page 34: Revision History
26MAR2005 03MAY2005 12AUG2005 Freescale Semiconductor Author Initial Version AS, TB, PL Updated PCI, PSC, BestComm, I2C, GPIO, CDM chapters. Cross refs, hyperlinks, TOC, Verso, and fonts. AE, TB, PL, CM, Minor updates. MPC5200B Users Guide, Rev. 1 Summary of Changes...
Page 35: Freescale Semiconductor
MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 36: Overview
The MPC5200B supports a dual external bus architecture. It has a high speed SDRAM Bus interface that connects directly to the e300 core. In addition, the MPC5200B has a LocalPlus Bus used as a generalized interface to system level peripheral devices and debug environments.
Page 37: Architecture
• Software — QNX — VXWorks — Linux — Software Modem capable — JAVA Architecture The following areas comprise the MPC5200B system architecture: • Embedded e300 Core • BestComm I/O Subsystem • Controller Area Network (CAN) • Byte Data Link Controller - Digital BDLC-D •...
Page 38: Simplified Block Diagram—Mpc5200
A dynamically managed external pin multiplexing scheme minimizes overall pin count. The result is low cost packaging and board assembly costs. Figure 1-1 shows a simplified MPC5200B block diagram. Figure 1-1. Simplified Block Diagram—MPC5200B Freescale Semiconductor BestComm DMA SRAM 16K MPC5200B Users Guide, Rev.
Page 39: Freescale Semiconductor
The LocalPlus Bus provides for connection of external peripheral devices, disk storage, and slower speed memory. The LocalPlus Bus also supports an external Boot ROM/FLASH/SRAM interface. The MPC5200B integrates a high performance e300 core with an I/O subsystem containing an intelligent Direct Memory Access (DMA) unit, BestComm. The BestComm unit is capable of: •...
Page 40: Embedded G2_Le Core
1.2.1 Embedded e300 Core The MPC5200B embedded e300 core is derived from Freescale’s (formerly Motorola) MPC603e family of Reduced Instruction Set Computer (RISC) microprocessors. The e300 core is a high-performance, low-power implementation of the PowerPC superscalar architecture. The MPC5200B e300 core contains: •...
Page 41: Bestcomm I/O Subsystem
USB transceiver. The Host Controller supports the Open Host Controller Interface (OHCI) standard. 1.2.2.4 Infrared Support The MPC5200B supports the IrDA format. All three IrDA modes are supported (SIR, MIR, FIR) to 4.0Mbps. The required 48MHz clock can be generated internally or supplied externally on an input pin. 1.2.2.5...
Page 42: Byte Data Link Controller - Digital Bdlc-D
Chip Selects The MPC5200B integrates the most common system integration interfaces and signals. There are 8 fully programmable external chip selects, which are independent of the SDRAM interface. LP_CS0 has special features to support a Boot ROM. Two of the chip selects may be used by the IDE disk drive interface, when enabled.
Page 43: Functional Pin Multiplexing
If a 7-wire Ethernet connection is adequate, the additional 11 Ethernet I/Os can be used as GPIOs. 1.2.5.6 Real-Time Clock (RTC) An RTC is included on the MPC5200B. The RTC provides a 2-pin interface to an external 32.768KHz crystal. This allows internal time-of-day/calendar tracking, as well as clock based periodic interrupts. 1.2.6 SDRAM Controller and Interface The MPC5200B high speed SDRAM Controller supports both standard SDRAM and Double Data Rate (DDR) SDRAM devices.
Page 44: Systems Debug And Test
A Wake Up capability is supported by CAN, RTC, several GPIOs and the interrupt lines. Therefore, the MPC5200B can be shut down to a low-power standby mode, then re-enabled by one of the Wake Up inputs without resetting the MPC5200B.
Page 45 Architecture MPC5200B Users Guide, Rev. 1 1-10 Freescale Semiconductor...
Page 46: Chapter 2 Signal Descriptions
The MPC5200B contains a e300 core, an internal DMA engine, BestComm, multiple functional blocks and associated I/O ports. There are two external data/address bus structures, the LocalPlus bus and SDRAM bus. A block diagram of the MPC5200B structure is shown in Figure 1-1.
Page 47: Pin Pbga Pin Detail
Table 2-1 Note: Table 2-1 gives a list of MPC5200B I/O signals sorted by package ball name. Many signal pins can have multiple functions depending on internal register settings. These additional functions are described in through Table 2-31. View Looking at Pins (Balls)
Page 48: Pin Pbga — Top View
TEST_MODE_1 JTAG_TDO JTAG_TDI JTAG_TMS PSC3_8 PSC3_5 TEST_SEL_0 TEST_MODE_0 JTAG_TRST JTAG_TCK PSC3_7 PSC3_4 RTC_XTAL_OUT RTC_XTAL_IN TEST_SEL_1 PSC3_9 PSC3_6 PSC3_3 TIMER_4 TIMER_3 TIMER_2 VDD_CORE VDD_IO VDD_CORE TIMER_7 TIMER_6 TIMER_5 VDD_IO USB_7 USB_8 USB_9 VDD_IO USB_3 USB_4 USB_5 USB_6 USB_0 USB_1 USB_2 VDD_IO ETH_3 ETH_4 ETH_10...
Page 49: Pinout Tables
Group Pinout Tables Ball/Pin System chip selects 5 pins 5 pins 10 pins PSC2 PSC3 Group Group Figure 2-3. MPC5200B Peripheral Muxing Table 2-1. Signals by Ball/Pin Pin Name Ball/Pin TEST_MODE_1 JTAG_TDO JTAG_TDI JTAG_TMS PSC3_8 PSC3_5 PSC3_2 PSC2_4 PSC2_2 PSC1_4 MPC5200B Users Guide, Rev.
Page 50 MEM_WE MEM_DQM_2 TEST_SEL_0 JTAG_TRST JTAG_TCK PSC3_7 PSC3_4 PSC3_1 PSC2_3 PSC2_1 PSC1_3 PSC1_0 PSC6_0 HRESET VDD_CORE MEM_MA_7 MEM_MA_8 MPC5200B Users Guide, Rev. 1 Pinout Tables Pin Name PSC3_3 PSC3_0 CORE_PLL_AVDD PSC2_0 PSC1_2 PSC6_1 GPIO_WKUP_7 PSC6_3 SYS_PLL_AVSS GPIO_WKUP_6 MEM_MA_3 MEM_MA_0 MEM_MBA_0 MEM_MA_5...
Page 51 USB_9 VDD_IO MEM_MA_12 USB_3 USB_4 USB_5 USB_6 MEM_CLK MEM_CLK USB_0 USB_1 USB_2 MEM_DQM_3 ETH_13 ETH_12 ETH_8 VDD_CORE MPC5200B Users Guide, Rev. 1 Pin Name VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE MEM_MDQ_22 MEM_MDQ_21 MEM_MDQ_8 MEM_MDQ_9 ETH_0 ETH_1 ETH_2 VDD_CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VDD_MEM_IO...
Page 52 ETH_15 ETH_14 MEM_DQM_0 IRQ1 IRQ2 IRQ0 VDD_CORE IRQ3 PCI_RESET EXT_AD_30 PCI_GNT PCI_PAR EXT_AD_13 EXT_AD_11 EXT_AD_9 EXT_AD_4 EXT_AD_2 MPC5200B Users Guide, Rev. 1 Pinout Tables Pin Name MEM_MDQ_30 MEM_MDQ_3 MEM_MDQ_2 PCI_REQ PCI_IDSEL EXT_AD_24 VSS_IO/CORE VDD_IO VDD_IO VDD_CORE EXT_AD_15 VDD_IO VDD_IO EXT_AD_6...
Page 53 EXT_AD_23 EXT_AD_16 PCI_TRDY PCI_CBE_2 PCI_DEVSEL PCI_SERR EXT_AD_14 PCI_CBE_0 EXT_AD_8 EXT_AD_5 EXT_AD_1 LP_CS0 LP_CS3 LP_RW ATA_IOW I2C_1 I2C_3 EXT_AD_27 PCI_CBE_3 EXT_AD_21 MPC5200B Users Guide, Rev. 1 Pin Name EXT_AD_10 EXT_AD_7 EXT_AD_3 LP_TS LP_CS1 LP_CS4 ATA_ISOLATION ATA_IOR ATA_DACK ATA_INTRQ TIMER_0 Freescale Semiconductor...
Page 54 EXT_AD_12 EXT_AD_13 EXT_AD_14 EXT_AD_15 EXT_AD_16 EXT_AD_17 EXT_AD_18 EXT_AD_19 EXT_AD_20 EXT_AD_21 EXT_AD_22 EXT_AD_23 EXT_AD_24 EXT_AD_25 EXT_AD_26 EXT_AD_27 EXT_AD_28 EXT_AD_29 EXT_AD_30 EXT_AD_31 GPIO_WKUP_6 GPIO_WKUP_7 CORE_PLL_AVDD CORE_PLL_AVSS HRESET I2C_0 I2C_1 I2C_2 I2C_3 MPC5200B Users Guide, Rev. 1 Pinout Tables Ball/Pin NC (no connection)
Page 55 MEM_MDQ_0 MEM_MDQ_1 MEM_MDQ_2 MEM_MDQ_3 MEM_MDQ_4 MEM_MDQ_5 MEM_MDQ_6 MEM_MDQ_7 MEM_MDQ_8 MEM_MDQ_9 MEM_MDQ_10 MEM_MDQ_11 MEM_MDQ_12 MEM_MDQ_13 MEM_MDQ_14 MEM_MDQ_15 MEM_MDQ_16 MEM_MDQ_17 MEM_MDQ_18 MEM_MDQ_19 MEM_MDQ_20 MEM_MDQ_21 MEM_MDQ_22 MEM_MDQ_23 MEM_MDQ_24 MEM_MDQ_25 MEM_MDQ_26 MEM_MDQ_27 MEM_MDQ_28 MEM_MDQ_29 MEM_MDQ_30 MEM_MDQ_31 MPC5200B Users Guide, Rev. 1 Ball/Pin Freescale Semiconductor...
Page 56 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 RTC_XTAL_IN RTC_XTAL_OUT SRESET SYS_PLL_AVDD SYS_PLL_AVSS SYS_PLL_TPA SYS_XTAL_IN SYS_XTAL_OUT TEST_MODE_0 TEST_MODE_1 TEST_SEL_0 TEST_SEL_1 TIMER_0 TIMER_1 TIMER_2 TIMER_3 TIMER_4 TIMER_5 TIMER_6 TIMER_7 USB_0 USB_1 USB_2 USB_3 USB_4 USB_5 MPC5200B Users Guide, Rev. 1 Pinout Tables Ball/Pin 2-11...
Page 57 VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO 2-12 Ball/Pin Signal Name USB_6 USB_7 USB_8 USB_9 VDD_CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VSS_IO/CORE VDD_CORE MPC5200B Users Guide, Rev. 1 Ball/Pin Freescale Semiconductor...
Page 58 8 bit Data tenure 16 bit Data tenure 32 bit Data tenure Freescale Semiconductor Ball/Pin Signal Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPC5200B Users Guide, Rev. 1 Pinout Tables Ball/Pin 2-13...
Page 59 16-bit 8-bit 32-bit Data Data Data Address Data Phase Phase Phase Phase Phase PCI Dedicated Signals PCI_CBE_0 PCI_CBE_1 MPC5200B Users Guide, Rev. 1 PCI BUS Large MOST Flash 16-bit 8-bit Data Data Phase Phase SA_2 SA_1 SA_0 PCI_PAR Freescale Semiconductor...
Page 60 PCI_CBE_3 PCI_STOP PCI_DEVSEL PCI_FRAME PCI_SERR PCI_PERR PCI_IDSEL Same as PCI_CLOCK PCI_RESET ATA Dedicated Signals LocalPlus Dedicated Signals LP_RW LP_ALE LP_TS MPC5200B Users Guide, Rev. 1 Pinout Tables PCI BUS Large MOST Flash 16-bit 8-bit Data Data Phase Phase PCI_TRDY PCI_IRDY...
Page 61 MOST Graphics Data Bit D31 ----- ----- ----- hi - z PCI Address Bit A31 logic 0 logic 0 logic 0 logic 0 PCI Data Bit 31 MPC5200B Users Guide, Rev. 1 PCI BUS Large MOST Flash 16-bit 8-bit Data Data Phase Phase...
Page 62 Large Flash Data Bit D12 hi - z MOST Graphics Data Bit D28 ----- ----- ----- hi - z PCI Address Bit A28 logic 0 logic 0 logic 0 logic 0 PCI Data Bit 28 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-17...
Page 63 Large Flash Data Bit D9 hi - z MOST Graphics Data Bit D25 ----- ----- ----- hi - z PCI Address Bit A25 logic 0 logic 0 logic 0 logic 0 PCI Data Bit 25 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 64 Large Flash Data Bit D6 hi - z MOST Graphics Data Bit D22 ----- ----- ----- hi - z PCI Address Bit A22 logic 0 logic 0 logic 0 logic 0 PCI Data Bit D22 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-19...
Page 65 Large Flash Data Bit D3 hi - z MOST Graphics Data Bit D19 ----- ----- ----- hi - z PCI Address Bit A19 logic 0 logic 0 logic 0 logic 0 PCI Data Bit D19 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 66 - z MOST Graphics Data Bit D16 ATA_SA_0 hi - z ATA_SA_0 hi - z PCI Address Bit A16 logic 0 logic 0 logic 0 logic 0 PCI Data Bit D16 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-21...
Page 67 MOST Graphics Data Bit D13 ATA_DATA_1 hi - z ATA Data Bit D13 hi - z PCI Address Bit A13 logic 0 logic 0 PCI Data Bit D13 PCI Data Bit D13 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 68 - z MOST Graphics Data Bit D10 ATA_DATA_1 hi - z ATA_DATA_10 hi - z PCI Address Bit A10 logic 0 logic 0 PCI Data Bit D10 PCI Data Bit D10 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-23...
Page 69 - z MOST Graphics Data Bit D7 ATA_DATA_7 hi - z ATA_DATA_7 hi - z PCI Address Bit A7 PCI Data Bit D7 PCI Data Bit D7 PCI Data Bit D7 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 70 - z MOST Graphics Data Bit D4 ATA_DATA_4 hi - z ATA_DATA_4 hi - z PCI Address Bit A4 PCI Data Bit D4 PCI Data Bit D4 PCI Data Bit D4 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-25...
Page 71 - z MOST Graphics Data Bit D1 ATA_DATA_1 hi - z ATA_DATA_1 hi - z PCI Address Bit A1 PCI Data Bit D1 PCI Data Bit D1 PCI Data Bit D1 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 72 Large Flash Address Bit A19 logic 1 MOST Graphics Address Bit A3 PCI_CBE_3 logic 1 PCI Command Byte Enable 3 logic 1 Large Flash Address Bit A20 logic 1 MOST Graphics Address Bit A4 MPC5200B Users Guide, Rev. 1 Pinout Tables Description Description 2-27...
Page 73 MOST Graphics Address Bit A12 PCI_REQ logic 1 PCI Bus Request logic 1 MOST Graphics Address Bit A13 PCI_GNT logic 1 PCI Bus Grant logic 1 MOST Graphics Address Bit A14 PCI_CLOCK PCI Clock MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 74 MOST Graphics Address Bit A20 ATA_INTRQ logic 1 ATA Interrupt Request logic 1 MOST Graphics Address Bit A21 ATA_ISOLATION logic 1 ATA Levelshifter control signal logic 1 MOST Graphics Address Bit A22 MPC5200B Users Guide, Rev. 1 Pinout Tables Description Description 2-29...
Page 75 LocalPlus Transfer Start Start Bit 5 -- xlb_clk_sel RST_CFG5 logic 1 bit = 0: XLB_CLK = f bit = 1: XLB_CLK = f LP Output logic 1 LocalPlus Output Enable Enable MPC5200B Users Guide, Rev. 1 Description system system Freescale Semiconductor...
Page 76: Psc1 Port Map—5 Pins
Figure 2-4. PSC1 Port Map—5 Pins Table 2-9. PSC1 Pin Functions AC97_1 UART1 UART1e UART1_TXD UART1e_TXD UART1_RXD UART1e_RXD UART1_RTS UART1e_RTS UART1_CTS UART1e_CTS GPIO_W/WAKE_UP UART1e_DCD MPC5200B Users Guide, Rev. 1 Pinout Tables AC971 GPIO PSC_2 PSC_3 PSC_4 PSC_3 PSC_4 GPIO GPIO_W/WAKE_UP AC97_1_BITCLK AC97_1_RES UART2_CTS GPIO_W/WAKE_UP...
Page 77 - z AC97_1_SYNC AC97 Frame Sync hi - z UART1_RTS Ready To Send hi - z UART1e_RTS Ready To Send hi - z GPIO Simple General Purpose I/O hi - z CODEC1_w/MCLK _MCLK MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 78 - z GPIO Simple General Purpose I/O with WAKE UP hi - z UART1e_DCD UARTe Carrier Detect hi - z CODEC1_FRAME CODEC Frame Sync hi - z CODEC1_w/MCLK_FRAME CODEC Frame Sync MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-33...
Page 79: Psc2 Port Map—5 Pins
Figure 2-5. PSC2 Port Map—5 Pins Table 2-11. PSC2 Pin Functions AC97_2 UART2 AC97_2_SDATA_OUT UART2_TXD AC97_2_SDATA_IN UART2_RXD AC97_2_SYNC UART2_RTS AC97_2_BITCLK UART2_CTS AC97_2_RES GPIO_w/ WAKE_UP MPC5200B Users Guide, Rev. 1 GPIO PSC2_3 PSC2_4 PSC_3 PSC_4 GPIO GPIO_W/WAKE_UP CAN2_RX GPIO_W/WAKE_UP AC97_2_BITCLK AC97_2_RES UART2_CTS GPIO_W/WAKE_UP UART2e_CTS...
Page 80 CAN Transmit hi - z AC97_2_SYNC AC97 Frame Sync hi - z UART2_RTS Ready To Send hi - z UART2e_RTS Ready To Send hi - z GPIO Simple General Purpose I/O MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-35...
Page 81 Simple General Purpose I/O with WAKE UP hi - z AC97_2_RES AC97 Reset hi - z GPIO Simple General Purpose I/O with WAKE UP hi - z UART2e_DCD UARTe Carrier Detect hi - z CODEC2_FRAME CODEC Frame MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 82: Psc3 Port Map—10 Pins
UART3_RXD USB2_TXP UART3_RTS USB2_RXD UART3_CTS USB2_RXP LP_CS_6 USB2_RXN LP_CS_7 USB2_PRTPWR GPIO USB2_SPEED GPIO USB2_SUSPEND INTERRUPT USB2_OVRCNT GPIO_W/WAKE_UP MPC5200B Users Guide, Rev. 1 Pinout Tables GPIO PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_6 PSC3_7 PSC3_8 PSC3_9 GPIO GPIO INTERRUPT GPIO_W/WAKE-UP USB2_PRTPW USB2_SPEED USB2_SUSPE...
Page 83 Simple General Purpose I/O hi - z UART3_TXD Uart Transmit Data hi - z UART3e_TXD Uart Transmit Data hi - z CODEC3_TXD CODEC Transmit Data MPC5200B Users Guide, Rev. 1 UART3e / SPI CODEC3 / SPI UART3e_TXD CODEC3_TXD UART3e_RXD CODEC3_RXD UART3e_RTS CODEC3_CLK UART3e_CTS...
Page 84 CODEC Bit Clock hi - z GPIO Simple General Purpose I/O hi - z UART3_RTS Uart Ready to Send hi - z UART3_RTS Uart Ready To Send hi - z CODEC3_CLK CODEC Clock MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-39...
Page 85 - z UART3e_DCD UART3e Carrier Detect hi - z LP_CS_6 hi - z LP_CS_6 hi - z LP_CS_6 hi - z LP_CS_6 hi - z UART3e_DCD UART3e Carrier Detect hi - z LP_CS_6 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 86 - z SPI_MOSI SPI_Master Out Slave In hi - z SPI_MOSI SPI_Master Out Slave In hi - z SPI_MOSI SPI_Master Out Slave In hi - z SPI_MOSI SPI_Master Out Slave In MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-41...
Page 87 - z INTERRUPT hi - z SPI_SS SPI Slave Select hi - z SPI_SS SPI Slave Select hi - z SPI_SS SPI Slave Select hi - z SPI_SS SPI Slave Select MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 88: Usb Port Map—10 Pins
Pin Drivers and MUX Logic USB_1 USB_2 USB_3 USB_4 USB_5 USB_2 USB_3 USB_4 USB_5 UART4_TX UART4_RXD UART4_CTS UART5_RXD UART5_TXD Figure 2-7. USB Port Map—10 Pins MPC5200B Users Guide, Rev. 1 Pinout Tables Description GPIO USB_6 USB_7 USB_8 USB_9 USB_6 USB_7 USB_8 USB_9...
Page 89 - z ---- hi - z USB1_TXP USB1 Transmit Positive hi - z RST_CFG7 (Pull bit low) hi - z UART4_TXD Uart Transmit Data MPC5200B Users Guide, Rev. 1 2x UART4/5 GPIO UART4_RTS UART4_TXD UART4_RXD UART4_CTS UART5_RXD UART5_TXD UART5_RTS UART5_CTS...
Page 90 UART5_RTS Uart Ready To Send hi - z GPIO Simple General Purpose I/O hi - z USB1_SUSPEND USB Suspend hi - z ---- hi - z UART5_CTS Uart Clear To Send MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-45...
Page 91: Ethernet Output Port Map—8 Pins
XD_1 XD_2 XD_3 OUTPUT UART4e_TXD J1850_TX OUTPUT OUTPUT J1850_TX UART5e_RTS UART4_TXD J1850_TX OUTPUT J1850_TX OUTPUT OUTPUT J1850_TX MPC5200B Users Guide, Rev. 1 Description USB2 GPIO (output portion) ETH_4 ETH_5 ETH_6 ETH_7 ETH_5 ETH_6 ETH_7 RST_CFG13 RST_CFG14 ----- OUTPUT OUTPUT OUTPUT...
Page 92: Ethernet Input / Control Port Map—10 Pins
OUTPUT OUTPUT OUTPUT USB2_TXP OUTPUT USB2_PRTPWR OUTPUT USB2_SPEED OUTPUT USB2_SUSPEND OUTPUT USB2_OE OUTPUT USB2_TXN GPIO GPIO MPC5200B Users Guide, Rev. 1 Pinout Tables USB2 GPIO (I/O portion) ETH_14 ETH_15 ETH_16 ETH_17 E_UP USB2_RXN USB2_OVR GPIO_W/WAK E_UP E_UP USB2_RXN USB2_OVR GPIO_W/WAK...
Page 93 UART5e__DCD ETH7_RXCLK ETH7_RXCLK UART5e__CTS ETH7_COL ETH7_COL ETH7_TXCLK ETH7_TXCLK ETH7_RXD_O ETH7_RXD_O UART5e__RXD J1850_RX J1850_RX UART4e__RXD INTERRUPT UART4e__CTS INTERRUPT MPC5200B Users Guide, Rev. 1 ETH7 ETH7 / USB2 ETH7_RXCLK ETH7_RXCLK ETH7_COL ETH7_COL ETH7_TXCLK ETH7_TXCLK ETH7_RXD_0 ETH7_RXD_0 INTERRUPT USB2_RXD INTERRUPT USB2_RXP INTERRUPT USB2_RXN...
Page 94 - z GPIO Simple General Purpose Output bit 8 -- most_graphics_sel hi - z bit = 0: Most Graphics boot not enabled bit = 1: Most Graphics boot enabled. MPC5200B Users Guide, Rev. 1 Pinout Tables UART5e/J1850 J1850 INTERRUPT INTERRUPT GPIO_W/WAKE-...
Page 95 - z GPIO Simple General Purpose Output hi - z bit 15 -- large_flash_sel bit = 0: Large Flash boot not enabled bit = 1: Large Flash boot enabled. Note 3. MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 96 GPIO Simple General Purpose Output hi - z bit 10 -- ppc_msrip PPC Boot Address / Exception Table Loc. bit = 0: 0000 0100 (hex) bit = 1: fff0 0100 (hex) MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-51...
Page 97 Simple General Purpose Output hi - z GPIO Simple General Purpose Output hi - z bit 11 -- boot_rom_wait bit = 0: 4 IPbus clocks of waitstate* bit = 1: 48 IPbus clocks of waitstate* MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 98 J1850 Transmit Data hi - z bit 12 -- boot_rom_swap bit = 0: no byte lane swap - same endian ROM image bit = 1: byte lane swap - different endian ROM image MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-53...
Page 99 = 1: 32-bit ROM data bus For "large flash" boot case boot Flash addr is 25 bits. bit = 0: 8-bit Flash data bus bit = 1: 16-bit Flash data bus MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 100 14 -- boot_rom_type bit = 0: non-muxed boot ROM bus, single tenure transfer. bit = 1: muxed boot ROM bus, PPC like with address & data tenures, ALE_b & TS_b active. Note 3. MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-55...
Page 101 - z GPIO Simple General Purpose Output hi - z GPIO Simple General Purpose Output hi - z GPIO Simple General Purpose Output hi - z GPIO Simple General Purpose Output MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 102 Ethernet Receive Clock hi - z ETH_RXCLK Ethernet Receive Clock hi - z ETH_RXCLK Ethernet Receive Clock hi - z UART5e_CTS Uart Clear To Send hi - z UART5e_CTS Uart Clear To Send MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-57...
Page 103 - z ETH_TXCLK Ethernet Transmit Clock Input hi - z GPIO Simple General Purpose Output hi - z GPIO Simple General Purpose Output hi - z GPIO Simple General Purpose Output MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 104 J1850 Receive Data hi - z J1850_RX J1850 Receive Data hi - z J1850_RX J1850 Receive Data hi - z J1850_RX J1850 Receive Data hi - z J1850_RX J1850 Receive Data MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-59...
Page 105 Ethernet Receive Data Input hi - z UART4e_CTS Uart Clear To Send hi - z INTERRUPT hi - z UART4e_CTS Uart Clear To Send hi - z INTERRUPT hi - z INTERRUPT MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 106 - z GPIO Simple General Purpose Output with WAKE UP hi - z GPIO Simple General Purpose Output with WAKE UP hi - z GPIO Simple General Purpose Output with WAKE UP MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-61...
Page 107: Timer Port Map—8 Pins
SIMPLE GPIO SIMPLE GPIO TIMER 5 SIMPLE GPIO SIMPLE GPIO TIMER 6 SIMPLE GPIO SIMPLE GPIO SIMPLE GPIO SIMPLE GPIO TIMER 7 SIMPLE GPIO SIMPLE GPIO SIMPLE GPIO SIMPLE GPIO MPC5200B Users Guide, Rev. 1 CAN2 GPIO TMR_7 TMR_4 TMR_5 TMR_6...
Page 108 Simple General Purpose I/O hi - z GPIO Simple General Purpose I/O hi - z SPI _MOSI SPI Master Out Slave In hi - z SPI MOSI SPI Master Out Slave In MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-63...
Page 109 Simple General Purpose I/O hi - z GPIO Simple General Purpose I/O hi - z GPIO Simple General Purpose I/O hi - z SPI _CLK SPI Clock hi - z SPI CLK SPI Clock MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 110: Psc6 Port Map—4 Pins
PSC6_0 PSC6_1 PSC6_0 PSC6_1 GPIO_W/WAKE_ GPIO_W/WAKE_UP GPIO UART6_RXD/ UART6_CTS UART6_TXD/ IrDA_RX IrDA_TX CODEC6_RXD/ CODEC6_FRAME CODEC6_TXD/ IrDA_RX IrDA_TX Figure 2-11. PSC6 Port Map—4 Pins MPC5200B Users Guide, Rev. 1 Pinout Tables Description PSC6_2 PSC6_3 PSC6_2 PSC6_3 GPIO UART6_RTS CODEC6_CLK/ IR_USB_CLK 2-65...
Page 111 IrDA_TX Irda Transmit Data hi - z GPIO Simple General Purpose I/O hi - z UART6_RTS Uart Clear To Send hi - z CODEC6_CLK IR_USB_CLK MPC5200B Users Guide, Rev. 1 CODEC6 / IrDA CODEC6_RXD Irda_RX CODEC6_FRAME CODEC6_TXD IrDA_TX CODEC6_CLK/ IR_USB_CLK Description...
Page 112 I2C Clock I2C_2_CLK I2C Clock ATA_CS0 ATA Chip Select 0 I2C_2_I/O I2C I/O line I2C_2_I/O I2C I/O line ATA_CS1 ATA Chip Select 1 MPC5200B Users Guide, Rev. 1 Pinout Tables ATA Chip CAN1 Selects I2C_2 I2C_3 I2C_2 I2C_3 I2C2_CLK I2C2_IO...
Page 113 SDRAM Bus Bidirectional Data Bus Strobe 0 SDRAM Bus Data Mask 3 SDRAM Bus Data Mask 2 SDRAM Bus Data Mask 1 SDRAM Bus Data Mask 0 logic 0 SDRAM Bus Memory Address 12 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 114 SDRAM Bus Data 29 hi - z SDRAM Bus Data 28 hi - z SDRAM Bus Data 27 hi - z SDRAM Bus Data 26 hi - z SDRAM Bus Data 25 MPC5200B Users Guide, Rev. 1 Pinout Tables Description 2-69...
Page 115 SDRAM Bus Data 10 hi - z SDRAM Bus Data 9 hi - z SDRAM Bus Data 8 hi - z SDRAM Bus Data 7 hi - z SDRAM Bus Data 6 MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 116 NOTE: This pin requires a pull-down resistor. Scan Enable (for production test), PLL_BYPASS - input, CK_STOP - output ENID Input in Test Mode (for production test) NOTE: This pin requires a pull-down resistor. MPC5200B Users Guide, Rev. 1 Pinout Tables Description Description 2-71...
Page 117 Power On Reset logic 1 Hard Reset logic 1 Soft Reset APLL Chip clock crystal / external clock input APLL Chip Clock Crystal MPC5200B System Test Pll Output (analog output) Table 2-30. Dedicated GPIO Pin Function Reset Functions Value logic 0...
Page 118 1 LocalPlus Bus Output Enable External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Real Time Clock Crystal Input / External Clock Input Real Time Clock Crystal Ouput MPC5200B Users Guide, Rev. 1 Pinout Tables Descriptions 2-73...
Page 119 Signal Descriptions Notes MPC5200B Users Guide, Rev. 1 2-74 Freescale Semiconductor...
Page 120: Chapter 3 Memory Map
Chapter 3 Memory Map Overview The following sections are contained in this document: • MPC5200B Internal Register Memory Map • MPC5200B Memory Map • SDRAM Bus • LocalPlus Bus — Memory Cycles – Boot Chip Select – Chip Selects — ATA Cycles —...
Page 121: Internal Register Memory Map
Association registers. Ethernet registers. BestComm DMA PCI registers. Advanced Technology Attachment registers. BestComm DMA LocalPlus registers Inter-Integrated Circuit registers. On-chip Static RAM memory locations. MPC5200B Users Guide, Rev. 1 Reference Section 3.3.3 Section 8.7 Section 5.5 Section 9.7.1 Section 7.2.4 Section 7.4.4...
Page 122: Mpc5200 Memory Map
External Busses There are two external data / address bus structures on the MPC5200B. These are the LocalPlus Bus and the SDRAM Bus. The MPC5200B always begins execution from the release of RESET on the LocalPlus Bus and from the memory device connected to LP_CS0.
Page 123: Localplus Bus
DRAM’s. Program execution begins from the LocalPlus Bus memory device connected to LP_CS0. In actual practice, the only programs that are usually executed from LocalPlus Bus memory are those used to initialize the MPC5200B and to transfer data from LocalPlus Bus memory to SDRAM bus memory.
Page 124: Memory Map Space Register Description
Provides the offset to which all register space for MPC5200B is accessed. The reset value Register of this register is 0x8000, which provides for a MBAR of 0x8000 0000. All of MPC5200B registers are then accessible at MBAR+offset, where offset refers to the given value in Table 3-1 3.3.3.2...
Page 125: Sdram Chip Select Configuration Registers
Name offset 0x0034 SDRAM Chip Contains the Base Addresses and configurations for SDRAM’s connected to the Select 0 SDRAM controller. 0x0038 SDRAM Chip Select 1 Description Reserved Base Address Description Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 126 11000 10111 10110 10101 10100 10011 00001-10010 0000 Freescale Semiconductor Base XLB Address Reserved Description SDRAM size bit setting 512MB 256MB 128MB 64MB 32MB 16MB Reserved Disable MPC5200B Users Guide, Rev. 1 MPC5200B Memory Map Reserved 31 lsb SDRAM Size...
Page 127: Ipbi Control Register And Wait State Enable -Mbar+0X0054
Chip Select 0 Enable 16:30 Reserved These bits are reserved. Wait State Enable bit. This bit should always be enabled when running an IP bus frequency of >66MHz. Boot Reserved Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 128: Chapter 4 Resets And Reset Configuration
1. All “open drain” outputs of MPC5200B are actually regular 3-state output drivers with the output data tied low, and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage.
Page 129: Soft Reset—Sreset
HRESET for 4096 reference clock cycles HRESET APLLs Lock Reset Hold Sample configuration from RST_CONFIG[15:0] No Reset signals recognized for 2 Wait reference clock cycles Additional HRESET, SRESET Recognized Figure 4-1. Reset sequence MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 130: Other Resets
SRESET and internal soft reset to be asserted. Other Resets MPC5200B has four other reset signals. These signals are specific to certain peripheral modules and are controlled in the context of that module, not globally.
Page 131: Reset Configuration
MPC5200 Hardware Specifications. ATA Reset This is NOT a reset pin on MPC5200B. The ATA reset for the external drive must be supplied by the board level reset source, or if software control is required, generated via a GPIO.
Page 132 ROM bus, bit=1:muxed boot ROM bus, with PORCFG[16] large_flash_sel bit=0:No Boot in Large Flash Mode bit=1:Boot in Large Flash Mode MPC5200B Users Guide, Rev. 1 Reset Configuration Description max boot ROM address bus boot ROM address bus single tenure transfer.
Page 133 Resets and Reset Configuration Notes MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 134: Clock Distribution Module (Cdm)
Clock Distribution Module (CDM) The CDM is the source of all internally generated clocks and reset signals. The MPC5200B clock generation uses two analog phase locked loop (APLL) blocks. The system APLL takes an external reference frequency (nominal 27–33MHz) and generates the following internal clocks.
Page 135: Primary Synchronous Clock Domains
The SPI module therefore has a small asynchronous clock domain. C—There are two I C (Inter-Integrated Circuit) modules on MPC5200B. Both have input source clocks (I therefore asynchronous clock domains. RTC—The RTC (Real-Time Clock) has its own clock domain, clocked by an external 32.768KHz oscillator. The two oscillator pins are RTC_XTAL_IN and RTC_XTAL_OUT.
Page 136: Mpc5200 Clock Relations
5.3.1 MPC5200B Top Level Clock Relations Figure 5-2 shows the CDM clock divide circuitry. This picture shows only the functional clocks. The clock network regarding the scan and bypass modes is not included. XLB Clock Divider / (8 or 4)
Page 137 Table 5-2. System PLL Ratios sys_pll_cfg[0] VCOsys frequencies exceed the maximum operation frequency. See VCOsys Table 5-3. MPC5200B Clock Ratios IPB CLOCK pci_clk_sel[1:0] XLB /2 XLB /2 XLB /2 XLB /2 XLB /2 XLB /2 XLB /2 XLB /2 MPC5200B Users Guide, Rev.
Page 138 132.0 132.0 66.0 33.0 66.0 66.0 33.0 NOTE Table 5-4 represent possible ranges of operation. A variety of Table 5-5 NOTE MPC5200B Users Guide, Rev. 1 MPC5200B Clock Domains Clock Ratio XLB:IPB:PCI 66.0 4:4:2 33.0 4:4:1 66.0 4:2:2 33.0 4:2:1 33.0...
Page 139 APLL. A variety of conditions may prevent the part from actually performing at these frequency ranges. For data relating to actual performance, see the MPC5200B Hardware Specification. Table 5-6. e300 Core APLL Configuration Options...
Page 140: Processor Bus (Xlb ) Clock Domain
CLOCK frequency and PLL (f minimum operating frequencies. Refer to 5.3.3 Processor Bus (XLB ) Clock Domain The XLB clock (xlb_clk) is the fundamental MPC5200B clock frequency. The following operate at this frequency: • The internal processor address/data bus •...
Page 141: Ipb Clock Domain
The XLB is 64bits and the SDRAM external bus is 32bits. When SDR (single data rate) SDRAM memory is used, the XLB bandwidth is only half utilized. When DDR (dual data rate) memory is used, the XLB bandwidth is fully used on SDRAM transactions. MPC5200B supplies 2 external memory clocks as part of the SDRAM interface: •...
Page 142: Power Management
Full-Power Mode In Full-Power mode both the system PLL and microprocessor PLL are locked and the main system clocks are supplied to the MPC5200B system. In this mode, the e300 Core may use the Dynamic Power Mode (DPM). If this mode is enabled, logic not required for instruction execution, is not activated.
Page 143: Dynamic Power Mode
An interrupt from one of the MSCAN modules (which occurs when a data transition occurs on the serial input). The RTC clock is necessary to wake up MPC5200B using an RTC interrupt. However, no clock is required to trigger the wake up process in the case of an external interrupt or the MSCAN module interrupt.
Page 144: Entering Deep Sleep
Core Processor wakes up and puts MPC5200B into full power mode and then services the wakeup interrupt Waking up from Deep Sleep mode does not require the system to be reset or a boot sequence. The functional state of MPC5200B should remain the same as when it went into Deep Sleep.
Page 145: Cdm Jtag Id Number Register—Mbar + 0X0200
5.5.1 CDM JTAG ID Number Register—MBAR + 0x0200 The CDM JTAG ID Number Register is a read-only register that contains the JTAG Identification number identifying MPC5200B. The value is hard coded (1001 101D hex) and cannot be modified. msb 0...
Page 146 (24x, 32x). No net effect on any internal clocks, except that PLL VCO runs twice as fast. Useful in low frequency applications to keep VCO frequency (f above min, see MPC5200B Hardware Specification. sys_pll_cfg_0 Latched pin value at reset.
Page 147: Cdm Bread Crumb Register—Mbar + 0X0208
— — — — — CDM Bread Crumb Register (Never Reset) — — — — — — Table 5-11. CDM Configuration Register MPC5200B Users Guide, Rev. 1 — — — — — — 31 lsb — — — — —...
Page 148: Cdm 48Mhz Fractional Divider Configuration Register—Mbar + 0X0210
Table 5-12. CDM 48MHz Fractional Divider Configuration Register msb 0 Reserved Write 0 RESET: cfgd_p3_cnt RESET: Freescale Semiconductor Description system system Table 5-3 Table 5-4. NOTE cfgd_p2_cntt cfgd_p1_cnt MPC5200B Users Guide, Rev. 1 CDM Registers Reserved fd_en Write 0 31 lsb cfgd_p0_cnt 5-15...
Page 149: Cdm Clock Enable Register—Mbar + 0X0214
001–fractional counter divide ratio f 010–fractional counter divide ratio f 011–fractional counter divide ratio f 10X–fractional counter divide ratio f Table 5-13. CDM Clock Enable Register Reserved Write 0 MPC5200B Users Guide, Rev. 1 system system system system system system...
Page 150: Cdm System Oscillator Configuration Register—Mbar + 0X0218
The crystal oscillator pad cell is disabled to reduce power consumption (~6mW for system oscillator). Table 5-14. CDM System Oscillator Configuration Register msb 0 Reserved Write 0 RESET: Freescale Semiconductor Description C module clocks MPC5200B Users Guide, Rev. 1 CDM Registers Reserved Write 0 5-17...
Page 151: Cdm Clock Control Sequencer Configuration Register—Mbar + 0X021C
5.5.8 CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C This register contains the configuration that controls the CCS module. The CCS module lets MPC5200B enter deep sleep power down mode (all clocks stopped). Table 5-15. CDM Clock Control Sequencer Configuration Register...
Page 152 CCS Test bit—Used in CCS module functional simulation to simulate a QREQ signal. Freescale Semiconductor Description bit=0:QREQ input to CCS forced active. bit=1:QREQ input to CCS comes directly from e300 Core. MPC5200B Users Guide, Rev. 1 CDM Registers 5-19...
Page 153 Reserved Write 0 Description bit=0:requests CDM soft reset. bit=1:CDM soft reset request inactive. bit=0:Checkstop assertion causes HRESET. bit=1:Checkstop assertion does not cause HRESET. — MPC5200B Users Guide, Rev. 1 Reserved Write 0 31 lsb Reserved Write 0 31 lsb Reserved...
Page 154: Psc1 Mclock Config Register—Mbar + 0X
In PLL bypass mode, Lock is active after 256 System Oscillator clock rising edges. 2. In current MPC5200B CDM the PLL Lock Circuitry is for information only. CDM does not wait for PLL lock to start clocks or use PLL_LOST_LOCK as an interrupt source.
Page 155: Psc2 Mclock Config Register—Mbar + 0X022C
Mclock. bit=1:Turns on internally generated Mclock. frequency by MclkDiv+1. A vallue of 0x00 in this system clock is always 12 or 16 times the reference clock, sys_xtal_in, system MPC5200B Users Guide, Rev. 1 — 31 lsb MclkDiv[8:0] 31 lsb MclkDiv[8:0]...
Page 156 Mclock. bit=1:Turns on internally generated Mclock. frequency by MclkDiv+1. A vallue of 0x00 in this system clock is always 12 or 16 times the reference clock, sys_xtal_in, system MPC5200B Users Guide, Rev. 1 CDM Registers — 31 lsb MclkDiv[8:0] 5-23...
Page 157 CDM Registers MPC5200B Users Guide, Rev. 1 5-24 Freescale Semiconductor...
Page 158: Overview
The MPC5200B integrates a e300 processor core based on, and compatible with, the 603e which is a PowerPC compliant microprocessor. The e300 core is completely embedded, as its address, data, and control signals are not visible external to MPC5200B. The e300 core has the following features: •...
Page 159: Not Supported Instruction
Not supported XLB parity feature The e300 core supports an address and data parity error detection for the XL bus. This feature is not supported by the MPC5200B. The core input signals core_ap_in [0:3] are pulled-down to 0 and the core input signals core_dp_in [0:7] are pulled-up to 1. Enabling of the address or data parity error check by the HID0 [EBA, EBD] bits will generate a machine check exception or a checkstop depending on the HID0 [EMCP] bit.
Page 160 These are special GPIO pins with WakeUP capability. There are 8 such pins funneled into one interrupt. The source module is gpio_wkup. GPIO pins with simple interrupt capability (not available in power down mode). The source module is gpio_std. No vector handler, generates SRESET output indication. MPC5200B Users Guide, Rev. 1 Overview...
Page 161: Interrupt Controller
— BestComm HI, IRQ0, MSR[ce] Slice Timer 0, CCS WakeUp Slice Timer 1, MSR[ee] Programmable interrupts Programmable interrupts MSR[ee] MPC5200B Users Guide, Rev. 1 Section 7.2.1.1, Machine Figure 7-2 shows the interrupt Timing — Persistent (remains until cleared) Persistent Persistent...
Page 162 • ATAs • transport de-multiplexers • external I/O devices, etc. These interrupts are programmable as edge or level sensitive. See Freescale Semiconductor HI_int LO_int Indicates priority encoding programmability. Figure 7-1. MPC5200B Users Guide, Rev. 1 Interrupt Controller core_cint core_smi core_int...
Page 163: Interface Description
If the e300 core received the core_cint assertion during an core_int or core_smi assertion, it would preempt the current interrupt service routine and process the Critical Interrupt Service routine immediately. Since the MPC5200B Interrupt Controller postpones the core_cint assertion until after a current core_int or core_smi is finished, there can be a delay before the 603e receives and services Critical Interrupt Sources.
Page 164: Interrupt Controller Registers
• ICTL Main Interrupt Emulation All Register • ICTL Peripheral Interrupt Emulation All Register • (0x0544) ICTL IRQ Interrupt Emulation All Register • Per_mask MPC5200B Users Guide, Rev. 1 Interrupt Controller (0x0528) (0x052C) (0x0530) (0x0538) (0x0540) (0x0544) 31 lsb Reserved...
Page 165 ICTL Perstat, MainStat, CritiStat Encoded Register are suppressed, but the binary "all" status bits (PSa in ICTL Peripheral Interrupt Status All Register) are active as long as the source module is presenting an active input to the Interrupt Controller. Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 166 HI interrupt condition to the Interrupt Controller. These bits are writable and readable, but have no effect on controller operation. Freescale Semiconductor Per1_pri Per2_pri Per5_pri Per6_pri Description MPC5200B Users Guide, Rev. 1 Interrupt Controller Per3_pri 31 lsb Per7_pri...
Page 167: Ictl Peripheral Priority And Hi/Lo Select 3 Register —Mbar + 0X050C
All bits are programmable and significant. Per16_pri Peripheral 16 = I2C2 Per17_pri Peripheral 17 = CAN1 Per9_pri Per10_pri Per13_pri Per14_pri Description Per17_pri Per18_pri Per21_pri Per22_pri Description MPC5200B Users Guide, Rev. 1 Per11_pri 31 lsb Per15_pri Per19_pri 31 lsb Per23_pri Freescale Semiconductor...
Page 168 Reserved—unused bits, writing has no effect, always read as 0. Master External Enable—clearing this bit masks all IRQ input transitions (including status indications). Freescale Semiconductor Description ECLR(4) Etype0 EENA(4) Description MPC5200B Users Guide, Rev. 1 Interrupt Controller Etype1 Etype2 Etype3 31 lsb Reserved...
Page 169: Ictl Critical Priority And Main Interrupt Mask Register—Mbar + 0X
Crit3_pri Priority encoding value for CCS WakeUp source. Hard-wired as critical interrupt source number 3. 8:14 — Reserved 7-10 Description Crit2_pri Crit3_pri Main_Mask Description MPC5200B Users Guide, Rev. 1 Reserved Main_ Mask 31 lsb Freescale Semiconductor...
Page 170 Interrupt Controller. Masking IRQ[1:3], is redundant with External ENA bits in Reg4, but both masks are applied. 2. Slice Timer 1 is hard-coded and neither bank nor priority adjustable. Freescale Semiconductor Description MPC5200B Users Guide, Rev. 1 Interrupt Controller 7-11...
Page 171: Ictl Main Interrupt Priority And Int/Smi Select 1 Register —Mbar + 0X
1. Main source 0 (Slice Timer 1) is not listed, it is fixed as both the highest priority main interrupt and to generate an SMI interrupt output only. 7-12 Main2_pri Main3_pri Main6_pri Main7_pri Description MPC5200B Users Guide, Rev. 1 Main4_pri 31 lsb Main8_pri Freescale Semiconductor...
Page 172: Ictl Main Interrupt Priority And Int/Smi Select 2 Register—Mbar + 0X051C
PWM output. As such, there is an I/O pin associated with each timer. The timer can use this pin as GPIO, in which case the internal timer function becomes available. These eight timers complete the MPC5200B GPIO structure. All potential GPIO interrupt sources are represented by main sources 7, 8, and 9–16.
Page 173: Ictl Perstat, Mainstat, Mainstat, Critstat Encoded Register—Mbar + 0X
In this case it is necessary to parse the PSe to determine which peripheral source is active. See Note 1. 16:20 — Reserved 7-14 Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Reserved CEbSh Freescale Semiconductor...
Page 174: Ictl Critical Interrupt Status All Register—Mbar + 0X
4. For recovery from deep-sleep mode, it is necessary to acknowledge this WakeUp interrupt by writing 1 to the msb of this field (CSe). Only then does the CCS module release it's power-down internal signal and let MPC5200B operate normally.
Page 175: Ictl Main Interrupt Status All Register—Mbar + 0X052C
IRQ[2] input pin MSa3 IRQ[3] input pin MSa4 LO_int (some Peripheral source) MSa5 RTC_periodic interrupt MSa6 RTC_stopwatch interrupt MSa7 GPIO std interrupt 7-16 Description ICTL External Enable and External Types Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 176 Number in parenthesis indicates equivalent encoded value in PSe, ICTL PerStat, MainStat, CritStat Encoded Register. PSa23 BestComm LocalPlus PSa22 BDLC PSa0 BestComm interrupt source PSa1 PSC1 PSa2 PSC2 PSa3 PSC3 PSa4 PSC6 PSa5 Ethernet Freescale Semiconductor Description Description MPC5200B Users Guide, Rev. 1 Interrupt Controller 31 lsb Reserved PSa21 7-17...
Page 177: Ictl Peripheral Interrupt Status All Register—Mbar + 0X0530
Bus Error 1—Indicates write attempt to read-only register, clear with a write to 1. Bus Error 0—Indicates access to unimplemented register, clear with a write to 1. 8:31 — Reserved 7-18 Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 178 GPIO WakeUp interrupt MEa9 TMR0 interrupt MEa10 TMR1 interrupt MEa11 TMR2 interrupt MEa12 TMR3 interrupt MEa13 TMR4 interrupt MEa14 TMR5 interrupt MEa15 TMR6 interrupt MEa16 TMR7 interrupt Freescale Semiconductor Reserved Description MPC5200B Users Guide, Rev. 1 Interrupt Controller 31 lsb 7-19...
Page 179 PEa7 PEa8 PCI Control module PEa9 PCI SC Initiator Rx PEa10 PCI SC Initiator Tx PEa11 PSC4 PEa12 PSC5 PEa13 SPI modf PEa14 SPI spif PEa15 PEa16 7-20 Description MPC5200B Users Guide, Rev. 1 31 lsb Reserved PEa21 Freescale Semiconductor...
Page 180 1. The emulation is only possible if the IRQ pins are externally pulled down. Otherwise the OR between the external pin values and the IRQEa[x] bits is whole the time one. Freescale Semiconductor Description IRQEa Reserved Description MPC5200B Users Guide, Rev. 1 Interrupt Controller Reserved 31 lsb 7-21...
Page 181: General Purpose I/O (Gpio)
General Purpose I/O (GPIO) There are a total of 56 possible GPIO pins on the MPC5200B. Virtually all of these pins are shared with alternate hardware functions. Therefore, GPIO availability is entirely dependant on the peripheral set a particular application requires.
Page 182 USB2 USB2/SPI USB2/SPI USB2/SPI USB2/SPI USB1 (OE) USB1 (PORTPWR)/UART5 (TXD) USB1 (SPEED)/UART5 (RTS) USB1 (SUSPEND)/UART5 (CTS) USB1 (OvrCrnt) Ethernet Ethernet/UART5 Ethernet/USB2/UART5 Ethernet/USB2/UART4 Ethernet/USB2/J1850 Ethernet/USB2/UART4 Ethernet/USB2 Ethernet/USB2 Ethernet/UART5 Ethernet/UART5 MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) Interrupt WakeUp 7-23...
Page 183 7-24 Table 7-20. GPIO Pin List (continued) Alternate Functionality Ethernet Ethernet Ethernet/USB2/J1850 Ethernet/USB2/UART4 Ethernet/USB2/UART4 Ethernet/USB2/UART4 Ethernet IRDA/UART6/Codec6 IRDA(and/or USB)/UART6/Codec6 IRDA/UART6/Codec6 IRDA/UART6/Codec6 Dedicated GPIO Pin/SDRAM CS1 Dedicated GPIO Pin/LocalPlus Most/Graphics mode TSIZ1 MPC5200B Users Guide, Rev. 1 Interrupt WakeUp Freescale Semiconductor...
Page 184: Gpio Pin Multiplexing
2. Pin MUX Logic is controlled by the Port Configuration Register and supersedes any individual GPIO register programming. Freescale Semiconductor Pin MUX Logic Priority Output Enable Logic Figure 7-3. GPIO/Generic MUX Cell MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) I/O Cell Multi- Function 7-25...
Page 185: Psc1 (Uart1/Ac97/Codec1)
This port is configured such that 7-wire Ethernet and a secondary USB port can exist simultanaeouly. This configuration makes available 1 GPIO WakeUp pin. 7-26 2-4. 2-5. 2-6. NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 186: Psc6
Timer pins 0 and 1 can operate as CAN2 Tx/Rx or ATA Chip Selects. • Timer pins 2–5 can operate as the SPI port. Freescale Semiconductor C2). If the alternate function is specified, the associated I MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) C port is consumed and 7-27...
Page 187: Dedicated Gpio Port
All GPIO functionality is dependent on the Port Configuration Register (PCR) setting. The PCR is the first register in the GPIO Standard Module. This register controls the Pin MUX Logic. Therefore, the PCR also controls the physical routing of MPC5200B I/O pins to and from internal logic.
Page 188 1 = IrDA/USB clock is sourced externally, input only Freescale Semiconductor — MBAR + 0x0B00 PSC3 Rsvd PSC2 Description SPI on PSC3 according to PSC3 setting. MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) IRDA Ether 31 lsb Rsvd PSC1 7-29...
Page 189 0 = Differential mode (Default after reset) 1 = Single ended mode 00 = 4 GPIOs and 1 Interrupt GPIO 18:19 01 = USB 10 = Two UARTs 11 = Reserved 7-30 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 190 GPS Simple GPIO Enables Register Table 7-22. GPS Simple GPIO Enables Register msb 0 RESET: Freescale Semiconductor Description Table 2-1 Table 2-2 to determine GPIO availability for the various — MBAR + 0x0B04 MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) 7-31...
Page 191 22 controls GPIO_ PSC3_1 (PSC3_1 pin) bit 23 controls GPIO_ PSC3_0 (PSC3_0 pin) 0 = Disabled for GPIO (default) 1 = Enabled for GPIO 7-32 ETHR Reserved PSC3 PSC2 Description MPC5200B Users Guide, Rev. 1 31 lsb PSC1 Freescale Semiconductor...
Page 192: Gps Simple Gpio Open Drain Type Register —Mbar + 0X0B08
0 = Normal CMOS output (default) 1 = Open Drain emulation (a drive to high creates Hi-Z) 8:11 — Reserved Freescale Semiconductor Description ETHR Reserved PSC3 PSC2 Description MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) 31 lsb PSC1 7-33...
Page 193: Gps Simple Gpio Data Direction Register—Mbar + 0X0B0C
7.3.2.1.4 GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C Table 7-24. GPS Simple GPIO Data Direction Register msb 0 Reserved IRDA RESET: Reserved RESET: 7-34 Description ETHR Reserved PSC3 PSC2 MPC5200B Users Guide, Rev. 1 31 lsb PSC1 Freescale Semiconductor...
Page 194 21 controls GPIO_ PSC3_2 (PSC3_2 pin) bit 22 controls GPIO_ PSC3_1 (PSC3_1 pin) bit 23 controls GPIO_ PSC3_0 (PSC3_0 pin) 0 = Pin is Input (default) 1 = Pin is Output Freescale Semiconductor Description MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) 7-35...
Page 195 28 controls GPIO_PSC1_3 (PSC1_3 pin) bit 29 controls GPIO_PSC1_2 (PSC1_2 pin) bit 30 controls GPIO_PSC1_1 (PSC1_1 pin) bit 31 controls GPIO_PSC1_0 (PSC1_0 pin) 0 = Pin is Input (default) 1 = Pin is Output 7-36 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 196: Gps Simple Gpio Data Output Values Register —Mbar + 0X0B10
23 controls GPIO_ PSC3_0 (PSC3_0 pin) 0 = Drive 0 on the pin (default) 1 = Drive 1 on the pin Freescale Semiconductor ETHR Reserved PSC3 PSC2 Description MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) 31 lsb PSC1 7-37...
Page 197: Gps Simple Gpio Data Input Values Register —Mbar + 0X0B14
4 reflects GPIO_ETHI_3 (ETH_11 pin) bit 5 reflects GPIO_ETHI_2 (ETH_10 pin) bit 6 reflects GPIO_ETHI_1 (ETH_9 pin) bit 7 reflects GPIO_ETHI_0 (ETH_8 pin) 8:11 — Reserved 7-38 Description ETHR Reserved PSC3 PSC2 Description MPC5200B Users Guide, Rev. 1 31 lsb PSC1 Freescale Semiconductor...
Page 198: Gps Gpio Output-Only Enables Register —Mbar + 0X0B18
Note: These status bits operate regardless of the function on the pin. 7.3.2.1.7 GPS GPIO Output-Only Enables Register —MBAR + 0x0B18 Table 7-27. GPS GPIO Output-Only Enables Register msb 0 ETHR RESET: RESET: Freescale Semiconductor Description Reserved Reserved MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) 31 lsb 7-39...
Page 199: Gps Gpio Output-Only Data Value Out Register —Mbar + 0X0B1C
— Reserved 7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register —MBAR + 0x0B1C Table 7-28. GPS GPIO Output-Only Data Value Out Register msb 0 ETHR RESET: RESET: 7-40 Description Reserved Reserved MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 200: Gps Gpio Simple Interrupt Enable Register—Mbar + 0X0B20
— 7.3.2.1.9 GPS GPIO Simple Interrupt Enable Register—MBAR + 0x0B20 Table 7-29. GPS GPIO Simple Interrupt Enables Register msb 0 SIGPIOe RESET: RESET: Freescale Semiconductor Description Reserved MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) Reserved 31 lsb 7-41...
Page 201: Gps Gpio Simple Interrupt Open-Drain Emulation Register —Mbar + 0X0B
7 controls GPIO_SINT_0 (PSC3_4 pin) 0 = Normal CMOS output (default) 1 = Open Drain emulation (a drive to high creates Hi-Z) 8:31 — Reserved 7-42 Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 202: Gps Gpio Simple Interrupt Data Value Out Register —Mbar + 0X0B2C
GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C Table 7-32. GPS GPIO Simple Interrupt Data Value Out Register msb 0 SIDVO RESET: RESET: Freescale Semiconductor Reserved Description Reserved MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) Reserved 31 lsb Reserved 31 lsb 7-43...
Page 203: Gps Gpio Simple Interrupt Interrupt Types Register —Mbar + 0X0B34
Master Interrupt Enable bit must be set in the Register, before any Simple Interrupt pin can generate an Interrupt. 7-44 Description Reserved Description GPS GPIO Simple Interrupt Master Enable Register —MBAR + 0x0B38 MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Register. Also, Freescale Semiconductor...
Page 204: Gps Gpio Simple Interrupt Master Enable Register —Mbar + 0X0B38
Table 7-35. GPS GPIO Simple Interrupt Master Enable Register msb 0 Reserved RESET: RESET: Freescale Semiconductor ITYP5 ITYP4 ITYP3 Reserved Description Reserved Reserved MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) ITYP2 ITYP1 ITYP0 31 lsb 31 lsb 7-45...
Page 205: Gps Gpio Simple Interrupt Status Register—Mbar + 0X0B3C
Bit 15 reflects GPIO_SINT_0 (PSC3_4 pin) IVAL is always available regardless of enable or setting, even if not used as GPIO. Writing to this byte has no effect. 16:31 — Reserved 7-46 Description Reserved Description MPC5200B Users Guide, Rev. 1 IVAL 31 lsb Freescale Semiconductor...
Page 206: Gpw Wakeup Gpio Enables Register—Mbar + 0X0C00
It should be noted that WakeUp GPIO can operate as Simple Interrupt GPIO. Because of this, there are separate registers to enable these pins as Wakeup interupts and/or Simple Interrupts. The distiniction between these two types of interrupts is made according to the powered state of MPC5200B. •...
Page 207: Gpw Wakeup Gpio Data Direction Register—Mbar + 0X0C08
Reserved 7.3.2.2.3 GPW WakeUp GPIO Data Direction Register—MBAR + 0x0C08 Table 7-39. GPW WakeUp GPIO Data Direction Register msb 0 WDDR[7:0] RESET: RESET: 7-48 Reserved Description Reserved MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 208: Gpw Wakeup Gpio Data Value Out Register —Mbar + 0X0C0C
1 = Drive 1 on the pin. Note: If pin is emulating open drain, this setting results in Hi-Z 8:31 — Reserved Freescale Semiconductor Description Reserved Description MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) Reserved 31 lsb 7-49...
Page 209: Gpw Wakeup Gpio Individual Interrupt Enable Register —Mbar + 0X0C14
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin) 0 = Pin cannot generate WakeUp Interrupt (default). 1 = Pin can generate WakeUp Interrupt while MPC5200B is in Deep Sleep mode. Note: These enable bits apply ONLY when MPC5200B is in Deep Sleep mode.
Page 210: Gpw Wakeup Gpio Interrupt Types Register—Mbar + 0X0C18
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin) 0 = Pin cannot generate Simple Interrupt (default). 1 = Pin can generate Simple Interrupt while MPC5200B is not in Deep Sleep mode. Note: These enable bits apply only when MPC5200B is not in Deep Sleep mode.
Page 211: Gpw Wakeup Gpio Master Enables Register —Mbar + 0X0C1C
10=Interrupt on falling edge Ityp4 11=Interrupt on pulse (any 2 transitions) Ityp3 The above interrupt types describe operation for interrupts occuring while MPC5200B is not in Deep Sleep mode (i.e., Simple Interrupt types). For operation while in Deep Sleep 10:11 Ityp2...
Page 212: Gpw Wakeup Gpio Data Input Values Register —Mbar + 0X0C20
Bit 4 reflects GPIO_WKUP_3 (ETH_17 pin) Bit 5 reflects GPIO_WKUP_2 (PSC3_9 pin) Bit 6 reflects GPIO_WKUP_1 (PSC2_4 pin) Bit 7 reflects GPIO_WKUP_0 (PSC1_4 pin) 8:31 — Reserved Freescale Semiconductor Description Reserved Description MPC5200B Users Guide, Rev. 1 General Purpose I/O (GPIO) Reserved 31 lsb 7-53...
Page 213: Gpw Wakeup Gpio Status Register—Mbar + 0X0C24
Bit 5 reflects interrupt on GPIO_WKUP_2 (PSC3_9 pin) Bit 6 reflects interrupt on GPIO_WKUP_1 (PSC2_4 pin) Bit 7 reflects interrupt on GPIO_WKUP_0 (PSC1_4 pin) 8:31 — Reserved 7-54 Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 214: General Purpose Timers (Gpt)
The Terminal Count value is programmable. If the counter is allowed to expire, a full MPC5200B reset occurs. To prevent the Watchdog Timer from expiring, software must periodically write a specific value to a specific register (in Timer 0).
Page 215: Gpt 0 Enable And Mode Select Register—Mbar + 0X0600
GPT 4 Enable and Mode Select Register GPT 5 Enable and Mode Select Register GPT 6 Enable and Mode Select Register GPT 7 Enable and Mode Select Register Reserved Rsvd IntEn Reserved MPC5200B Users Guide, Rev. 1 (0x0608) (0x060C) Reserved 31 lsb GPIO Rsvd Timer_MS...
Page 216 WDen Watchdog enable—bit enables watchdog operation. A timer expiration causes an internal MPC5200B reset. Watchdog operation requires the Timer_MS field be set for internal timer mode and the CE bit to be set high. In this mode the OCPW byte field operates as a watchdog reset field. Writing A5 to the OCPW field resets the watchdog timer, preventing it from expiring.
Page 217 10=Timer enabled as simple GPIO output, value=0 11=Timer enabled as simple GPIO output, value=1 (tri-state if Open_Drn=1) While in GPIO modes, internal timer mode is also available. To prevent undesired timer expiration, keep the CE bit low. 7-58 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 218: Gpt 0 Counter Input Register—Mbar + 0X0604
GPT 2 Counter Input Register GPT 3 Counter Input Register GPT 4 Counter Input Register GPT 5 Counter Input Register GPT 6 Counter Input Register GPT 7 Counter Input Register Prescale Count MPC5200B Users Guide, Rev. 1 General Purpose Timers (GPT) 31 lsb 7-59...
Page 219: Gpt 0 Pwm Configuration Register—Mbar + 0X0608
GPT 2 PWM Configuration Register GPT 3 PWM Configuration Register GPT 4 PWM Configuration Register GPT 5 PWM Configuration Register GPT 6 PWM Configuration Register GPT 7 PWM Configuration Register WIDTH PWMOP Description MPC5200B Users Guide, Rev. 1 31 lsb Reserved LOAD Freescale Semiconductor...
Page 220: Gpt 0 Status Register—Mbar + 0X060C
GPT 3 Status Register GPT 4 Status Register GPT 5 Status Register GPT 6 Status Register GPT 7 Status Register CAPTURE Reserved Reserved Description MPC5200B Users Guide, Rev. 1 General Purpose Timers (GPT) 31 lsb TEXP PWMP COMP CAFT 7-61...
Page 221: Slice Timers
SLT 1 Count Value Register (0x0718) • SLT 0 Timer Status Register (0x070C) • SLT 1 Timer Status Register (0x071C) • 7-62 Description MBAR + 0x0700 + register address Read Only Read Only Read Only Read Only MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 222: Slt 0 Terminal Count Register—Mbar + 0X0700
0 Reserved RESET: RESET: Freescale Semiconductor SLT 1 Terminal Count Register Terminal Count Description Table 7-52. SLT 0 Control Register SLT 1 Control Register Reserved MPC5200B Users Guide, Rev. 1 Slice Timers Terminal Count 31 lsb Reserved 31 lsb 7-63...
Page 223: Slt 0 Count Value Register—Mbar + 0X0708
Provides current state of the Timer counter. This register does not chodange while a read is in Count progress, but the actual Timer counter continues unaffected. 7-64 Description Table 7-53. SLT 0 Count Value Register SLT 1 Count Value Register TimerCount Description MPC5200B Users Guide, Rev. 1 TimerCount 31 lsb Freescale Semiconductor...
Page 224: Slt 0 Timer Status Register—Mbar + 0X070C
Crystal support (32.768KHz only) RTC registers are writable, letting time and date be updated. If software enabled, RTC operates during all MPC5200B power-down modes. At a reset , control registers are put in a default state such that no interrupts generate until software enabled.
Page 225: Real-Time Clock Signals
Alarm case, this means enabling the Alarm. Clearing Stopwatch or Alarm interrupts is accomplished by writing 1 to the appropriate status bit. Either of the RTC interrupts to the CPU can be used to awaken the MPC5200B from any power down mode.
Page 226: Rtc Time Set Register—Mbar + 0X0800
RTC Periodic Interrupt and Bus Error Register (0x0808) • read-only RTC Test Register/Divides Register (0x0820) (0x080C) • Table 7-56. RTC Time Set Register Reserved Minute_set Reserved Description MPC5200B Users Guide, Rev. 1 Real-Time Clock (0x081C), C24Hour_set 31 lsb Second_set 7-67...
Page 227: Rtc Date Set Register—Mbar + 0X0804
Actually the lower 5 bits is used. Note: Year_set in the following register is also part of the date set function. 7-68 Description Table 7-57. RTC Date Set Register Reserved Weekday_set Reserved Description MPC5200B Users Guide, Rev. 1 Month_set 31 lsb Day_set Freescale Semiconductor...
Page 228: Rtc New Year And Stopwatch Register—Mbar + 0X0808
Alarm Enable bit for once-a-day Alarm. If high, Alarm status/interrupt operation is enabled. If low, Alarm setting is not compared to time of day. Freescale Semiconductor Year_set Description Reserved Alm_Min_set Reserved Description MPC5200B Users Guide, Rev. 1 Real-Time Clock SW_set 31 lsb Alm_24H_set 31 lsb 7-69...
Page 229: Rtc Current Time Register—Mbar + 0X0810
• Hour[1:4] designates current time in 12-hour format. 16:17 — Reserved 18:23 Minute Shows minutes in current time. 7-70 Description Table 7-60. RTC Current Time Register Reserved Minute Reserved Description MPC5200B Users Guide, Rev. 1 Hour 31 lsb Second Freescale Semiconductor...
Page 230: Rtc Current Date Register—Mbar + 0X0814
Table 7-62. RTC Alarm and Stopwatch Interrupt Register msb 0 Reserved RESET: Reserved RESET: Freescale Semiconductor Description Table 7-61. RTC Current Date Register Month Weekday Year Description MPC5200B Users Guide, Rev. 1 Real-Time Clock 31 lsb Reserved 31 lsb SW_min 7-71...
Page 231: Rtc Periodic Interrupt And Bus Error Register—Mbar + 0X081C
Periodic interrupt at midnight. High indicates interrupt has occurred. OR’d function of Int_day, Int_min and Int_sec produces RTC periodic interrupt to CPU interface. Cleared by writing 1 to this bit position. 7-72 Description Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved Freescale Semiconductor...
Page 232: Rtc Test Register/Divides Register—Mbar + 0X0820
However, be aware that these values are affected by reset. Therefore, any adjustment value must be stored and retrieved from non-volatile memory. Further, the adjustment could only increase the clock rate, not decrease it. Freescale Semiconductor Description PTERM Reserved Description MPC5200B Users Guide, Rev. 1 Real-Time Clock ETERM 31 lsb 7-73...
Page 233 Real-Time Clock MPC5200B Users Guide, Rev. 1 7-74 Freescale Semiconductor...
Page 234: Terminology And Notation
But while transporting bits from one location to another, the hardware transport media almost never have any knowledge of the concepts represented by the data, or the contexts in which they are valid (this does not include protocol bits of the media, which may be added and Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Overview...
Page 235 MEM_MDQ[31:24], MEM_DQM[3], and MEM_MDQS[3] are associated with address offset 0 modulo 4 (4n); MEM_MDQ[7:0], MEM_DQM[0], and MEM_MDQS[0] are associated with address offset 3 modulo 4 (4n+3). Features The MPC5200B SDRAM Memory Controller has the following features: • Supports either: — SDR SDRAM—memory I/Os are powered at 3.3V —...
Page 236 2Gbit when available, assuming the same interface style; The MPC5200B limits external memory to a maximum of 4 memory chips placed within 5 cm of the MPC5200B processor. Flight delay on the board should be no more than 0.5 ns each way, and all signals must be matched. The maximum load is 20pF/pin.
Page 237 8M x 4bank x 8bit 8M x 4bank x 16bit 8M x 4bank x 32bit 8M x 4bank x 16bit 8M x 4bank x 32bit MPC5200B Users Guide, Rev. 1 Physical Address Range 1 x 64Mb 2 x 64Mb 16MB...
Page 238 512K x 4bank x 32bit 16M x 4bank x 32bit 1M x 4bank x 16bit 2M x 4bank x 16bit 1M x 4bank x 16bit 4M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Features Physical Address Range 4 x 512Mb 256MB...
Page 239: Features
4M x 4bank x 16bit 2M x 4bank x 16bit 4M x 4bank x 16bit 2M x 4bank x 16bit 8M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Physical Address Range 2 x 64Mb 144MB 2 x 512Mb...
Page 240 2M x 4bank x 32bit 8M x 4bank x 32bit 2M x 4bank x 32bit 16M x 4bank x 32bit 2M x 4bank x 32bit 16M x 4bank x 32bit MPC5200B Users Guide, Rev. 1 Features Physical Address Range 2 x 128Mb 160MB...
Page 241 4M x 4bank x 32bit 16M x 4bank x 32bit 4M x 4bank x 32bit 16M x 4bank x 32bit 8M x 4bank x 32bit 16M x 4bank x 32bit MPC5200B Users Guide, Rev. 1 Physical Address Range 2 x256Mb 192MB 2 x 512Mb...
Page 242 2M x 4bank x 8bit 2M x 4bank x 16bit 4M x 4bank x 8bit 4M x 4bank x 16bit 4M x 4bank x 8bit 4M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Features Physical Address Range 2 x 512Mb 384MB...
Page 243 2Mx 4bank x 8bit 8M x 4bank x 8bit 2Mx 4bank x 8bit 8M x 4bank x 16bit 2M x 4bank x 8bit 16M x 4bank x 8bit MPC5200B Users Guide, Rev. 1 Physical Address Range 2 x 256Mb 64MB 1 x 512Mb...
Page 244 4M x 4bank x 8bit 4M x 4bank x 16bit 4M x 4bank x 8bit 8M x 4bank x 8bit 4M x 4bank x 8bit 8M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Features Physical Address Range 2 x 64Mb 144MB...
Page 245 16M x 4bank x 8bit 8M x 4bank x 8bit 16M x 4bank x 16bit 8M x 4bank x 16bit 16M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Physical Address Range 2 x 128Mb 160MB 2 x 256Mb...
Page 246 Table 8-2. 16-Bit External Data Width Legal Memory Configurations (continued) Row Bits Column Bits Freescale Semiconductor Spaces Bank Bits (CS) 16M x 4bank x 8bit 16M x 4bank x 16bit MPC5200B Users Guide, Rev. 1 Features Physical Address Range 2 x 512Mb 256MB 1 x 1Gb 8-13...
Page 247: Block Diagram—Sdram Subsystem Example
Both chip selects contribute together to access the whole memory. Each CS base address and size are programmed independently. Each CS base address must be size-aligned. The MPC5200B does not support DIMM memory modules, however it can support a DIMM-compatible EEPROM using an on-chip I interface (with appropriate configuration of pin functions).
Page 248: Functional Description
Note: Signals MEM_RAS, MEM_CAS, MEM_WE, and MEM_CLK_EN encode the SDRAM commands to control the different SDRAM operations. Note: For 16-bit mode external pull-down devices are required on MEM_MDQS[1:0]. Freescale Semiconductor Table 8-3. SDRAM External Signals Description Outputs Bidirectional Signals MPC5200B Users Guide, Rev. 1 Functional Description 8-15...
Page 249: Block Diagram
32 Byte block, 4 XLB data beats (8 memory data beats), spanning a modulo 32 address range. The starting address can be any 8-16 Address Pipeline Latches SDRAM Memory Controller State Machine Write Data Buffer Read Data Buffer MPC5200B Users Guide, Rev. 1 A[12:0] Address Output BA[1:0] CS[1:0] DQM[3:0] OUT_EN[3:0] DQSOUT DQSIN...
Page 250: Commands
This is done by setting or clearing the Control register mode_en bit.See Freescale Semiconductor Table 8-4. SDRAM Commands Symbol READ WRIT PALL LEMR AREF SREF H→L PDWN H→L Section 8.7.1, Mode Register—MBAR + 0x0100 MPC5200B Users Guide, Rev. 1 Functional Description BA[1:0] Other A 8-17...
Page 251: Precharge All Banks Command
Precharge command to close the active row, followed by a Bank Active command to activate the necessary row and bank for the new access, followed finally by the Write command. The Precharge and Bank Active commands (if necessary) can sometimes be issued in parallel with an on-going data movement. 8-18 NOTE NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 252: Auto Refresh Command
Step 2. Determine the number of SDRAM CS spaces. If using both CS spaces, configure GPIO_WKUP6/CS1 for CS1 mode. Freescale Semiconductor Section 5.5.6, CDM Clock Enable Register—MBAR NOTE if using serial EEPROM. NOTE MPC5200B Users Guide, Rev. 1 Operation C serial EEPROM, or compiled 8-19...
Page 253: Read Clock
Read Clock The MPC5200B implements a self-calibrating, software adjustable, read clock recovery circuit. A 400 tap master delay chain, continuously measures either the half or full period delay of the memory clock. The master tap value is used to derive a 1/4 period tap value, for use in 4 independent, 256 tap, slave delay chains.
Page 254 See SDRAM data sheet. Select either the memory device Mode register or the memory [1:0] device Extended Mode register, if present. 2:13 MEM_MA[11:0] See SDRAM data sheet. MPC5200B supports: Read CAS Latency, SDR: 2, 3 Read CAS Latency, DDR: 2, 2.5 Burst type: Sequential only Burst length: 8 only Other fields: As appropriate Specific bit allocation can vary from device to device.
Page 255: Memory Controller Registers (Mbar+0X0100:0X010C)
Reserved (must be written 0) drive_rule 0 “Tri-state except to write” mode: MPC5200B drives the MDQ and MDQS lines only when necessary to perform write commands. 1 “Drive except to read” mode: MPC5200B tri-states the MDQ and MDQS lines only when necessary to perform read commands.
Page 256 = 64ms / 4K = 15.625µs; 15.625µs x 133MHz = 2078.1 Table 8-7. High Address Usage XL Bus Address Line Mapping to Column or Row Address CA12 CA11 CA11 CA13 CA12 CA12 CA11 MPC5200B Users Guide, Rev. 1 RA12 CA11 8-23...
Page 257 CA11 — RA12 CA12 CA11 CA11 RA12 — CA11 — RA12 CA12 CA11 CA11 RA12 CA12 CA11 CA11 RA12 MPC5200B Users Guide, Rev. 1 9:19 20:21 22:29 [10:0] [1:0] [7:0] RA[11:0] RA[11:0] [1:0] [7:0] RA[11:0] [1:0] [7:0] RA[11:0] [1:0] [7:0]...
Page 258: Configuration Register 1—Mbar + 0X0108
(but with decreased performance). The “suggested values” are based on the maximum routing delay of memory signals and the MPC5200B maximum memory frequency of 133MHz;...
Page 259 = 20ns and MEM_CLK = 99 MHz 20ns / 10.1 ns = 1.98; round to 2; write 0x1. = 20 ns and MEM_CLK = 132 MHz 20ns / 7.5 ns = 2.66; round to 3; write 0x2. MPC5200B Users Guide, Rev. 1 Rsvd act2rw 31 lsb...
Page 260: Configuration Register 2—Mbar + 0X010C
= 75ns and MEM_CLK = 99 MHz 75ns / 10.1ns = 7.425; round to 8; write 0x7. = 75ns and MEM_CLK = 132 MHz 75ns / 7.5ns = 10; round to 9; write 0x9. bwt2rwp brd2wt Reserved MPC5200B Users Guide, Rev. 1 burst_length 31 lsb 8-27...
Page 261 If CL==3: 3 + 8 + 1 + 5.4ns - 1 = 11clk + 5.4ns, round to 0xC. 12:15 burst_length Write 0x07 (Burst Length - 1) 16:31 — Reserved 8-28 Description - 2) - 1.5 clk; round up. = 0.75 ns: - 1 clk: MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 262 (srd2rwp +1) or (brd2wt + 1) Read Prech bwt2rwp + 1 Active Read ref2act + 1 MPC5200B Users Guide, Rev. 1 Single Read to Read/Write/Precharge Data Burst Read to Write/Precharge Write wr_latency/3 Data Burst Read to Read Single Write to Read/Write/Precharge...
Page 263: Address Bus Mapping
XL bus address bits 20:21 select the internal bank of an SDRAM device. Each SDRAM device has 4 internal banks. XL bus address bits 20:21 are presented on the MPC5200B MEM_BA[1:0] pins during SDRAM Active, Read, and Write commands. The Memory Controller extracts the Column Address from the XL bus address. The Column Address is presented on the MPC5200B MEM_MA[12:0] pins during SDRAM Read and Write commands.
Page 264: Example—Physical Address Multiplexing
Using the MT46V32M16 DDR SDRAM memory from Micron as an example, the device holds 512Mb organized as 8M x 16bit x 4banks. 2 devices are required to support the MPC5200B 32bit memory data bus, giving a total 128MB of address space (assuming just one CS).
Page 265 By default, the Memory Controller only provides 12 row address bits and 12 column address bits. To enable the 13 row address bit, the hi_addr bit of the Control register must be set to 1 (MBAR+0x0104, Control[7]). This also reduces the column address width to 11 bits. MPC5200B Users Guide, Rev. 1 8-32 Freescale Semiconductor...
Page 266: Overview
LocalPlus Bus (External Bus Interface) Overview The LocalPlus Bus is the external bus interface of the MPC5200B. This multi-function bus system supports interfacing to external Boot ROM or Flash memories, external SRAM memories or other memory mapped devices. The following sections are contained herein: •...
Page 267: Interface
Address Latch Enable Table 9-1. LocalPlus External Signals Definition bits are available in non-muxed modes on GPIO_WKUP_7 and TEST_SEL_1 pins, if the LPTZ bit is set in the GPS Port Configuration Register—MBAR + 0x0B00 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 268: Lpc Concept Diagram
The reference clock is the PCI_CLOCK and all clock counts are referred to this clock. All transitions are synchronized to the rising edge of the PCI_CLOCK. Start/Stop registers to define the CS address range for each CS output are contained in the MPC5200B MMAP register group, see Section 3.3.3.2, Boot and Chip Select Addresses.
Page 269: Non-Muxed Mode
Each CS can be programmed to a different mode of operation (MUXed, non-MUXed, number of wait states, byte swapping etc.). The MPC5200B always begins execution from the release of HRESET on the LocalPlus Bus and from the memory device connected to CS0.
Page 270 Addr[1:0] AD[31:24] AD[23:16] Data Data Data Data Data Data MPC5200B Users Guide, Rev. 1 Modes of Operation Comments Legacy Mode Legacy Mode Legacy Mode Legacy Mode (BOOT OPTION) Legacy Mode (BOOT OPTION) MOST Graphics (BOOT OPTION) Burst support. No PCI or ATA support Large Flash Mode (BOOT OPTION).
Page 271: Muxed Mode
1. Burst Mode is only available for Large Flash and MOST Graphics mode. 2. ACK is output and indicates the burst. Valid Address Valid write Data Valid read Data Valid Address Figure 9-5. Timing Diagram—Burst Mode MPC5200B Users Guide, Rev. 1 Valid read Data Freescale Semiconductor...
Page 272: Address Tenure
32 MBytes 128 MBytes 32 MBytes 128 MBytes NOTE The 24-bit data width is not supported. MPC5200B Users Guide, Rev. 1 Modes of Operation Twelve different modes of address and Comments A0 not used. A0, A1 not used. A0 not used.
Page 273: Data Tenure
Only TSIZs of 1, 2, or 4 are supported. NOTE Table 9-5. Muxed Aligned Data Transfers AD[1:0] AD[31:24] AD[23:16] Data Data Data Data Data Data NOTE MPC5200B Users Guide, Rev. 1 Data lanes AD[15:8] AD[7:0] Data Data Data Data Data Data Freescale Semiconductor...
Page 274: Configuration
The number of wait states during boot can be 4 or 48 PCI bus clock cycles. Freescale Semiconductor valid write Data valid write Data TSIZ[0:2] bits valid write Data Bank[0:1] bits valid write Data Address[7:31] Data tenure Table 9-6. MPC5200B Users Guide, Rev. 1 Configuration valid read Data...
Page 275: Chip Selects Configuration
The Boot space does NOT support: • an 8-bit wide MUXed mode configuration during boot. After boot, CS Boot space can be programmed to act as other MPC5200B Chip Select spaces (CS0-7). This capability is described in the sections below. 9.5.2 Chip Selects Configuration All Chip Selects CS0-7 have the same functionality.
Page 276: Dma (Bestcomm) Interface (Sclpc)
If swap indicated: performed on reads from Boot Device NOTE MBAR + 0x0300 + register address MPC5200B Users Guide, Rev. 1 DMA (BestComm) Interface (SCLPC) Notes 8-bit access = no swap 16-bit access = 2Byte swap 32-bit access = 4Byte swap...
Page 277 Section 9-7, Chip Select 0/Boot Configuration Register (0x0300) • Section 9-10, Chip Select Status Register (0x031C) • Section 9-11, Chip Select Burst Control Register (0x0328) • Section 9-12, Chip Select Deadcycle Control Register (0x032C) 9-12 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 278: Chip Select 0/Boot Configuration Register—Mbar + 0X0300
Chip Select Control Register ME bit must also be high, except when CS[0] is used for boot ROM. 1 = Enable 0 = Disabled, register writes can occur but no external access is generated. Freescale Semiconductor Bank Description MPC5200B Users Guide, Rev. 1 Programmer’s Model WaitX 31 lsb WTyp 9-13...
Page 279 Endian swapped when read. This only has effect for boot devices configured as 16- or 32-bit data size. 9-14 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 280: Chip Select 1 Configuration Register—Mbar + 0X0304
Chip Select 2 Configuration Register Chip Select 3 Configuration Register Chip Select 4 Configuration Register Chip Select 5 Configuration Register Chip Select 6 Configuration Register Chip Select 7 Configuration Register Bank Description MPC5200B Users Guide, Rev. 1 Programmer’s Model WaitX 31 lsb WTyp 9-15...
Page 281 01 = WaitX is applied to Read cycles, WaitP is applied to Write cycles 10 = WaitX is applied to Reads, WaitP/WaitX (16-bit value) is applied to Writes 11 = WaitP/Waitx (as a full 16-bit value) is applied to Reads and Writes 9-16 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 282: Chip Select Control Register—Mbar + 0X0318
2. MOST Graphics mode is used, if AS is set to 10 and DS is set to 11. 9.7.1.3 Chip Select Control Register—MBAR + 0x0318 msb 0 Reserved RESET: RESET: Freescale Semiconductor Description Table 9-9. Chip Select Control Register Reserved MPC5200B Users Guide, Rev. 1 Programmer’s Model Reserved 31 lsb 9-17...
Page 283: Chip Select Status Register—Mbar + 0X031C
Table 9-11. Chip Select Burst Control Register msb 0 SLB7 Rsvd RESET: 9-18 Description Table 9-10. Chip Select Status Register Rsvd CSxerr Reserved Description CW6 SLB6 Rsvd CW5 SLB5 MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Rsvd CW4 SLB4 Rsvd Freescale Semiconductor...
Page 284 Chip Select 4 Cache Wrap capable, set if peripheral burst can perform PPC cache wrap. This bit setting only applies in Large Flash or MOST Graphics Mode. Freescale Semiconductor CW2 SLB2 Rsvd CW1 SLB1 Description MPC5200B Users Guide, Rev. 1 Programmer’s Model 31 lsb Rsvd CW0 SLB0 Rsvd 9-19...
Page 285 Chip Select 1 Burst Read Enable, 1 to enable peripheral bursting for given chip select. Must be set to enable any Bursting reads. This bit setting only applies in Large Flash or MOST Graphics Mode. 9-20 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 286: Chip Select Deadcycle Control Register—Mbar + 0X032C
This is for all access types. Freescale Semiconductor Description Reserved Reserved Reserved Reserved Description MPC5200B Users Guide, Rev. 1 Programmer’s Model Reserved 31 lsb Reserved 9-21...
Page 287 Deadcycle counter is only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If an arbitration happens the bus can be dirven within 4 IPB clocks by an other module. 9-22 Description NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 288: Sclpc Registers—Mbar + 0X3C00
Restart a transaction AND change the Packet_Size in a single write. Maximum packet size is 16M-1 bytes. Freescale Semiconductor MBAR + 0x3C00 + register address (0x3C00) (0x3C04) (0x3C08) (0x3C0C) (0x3C14) Table 9-13. SCLPC Packet Size Register Packet Size Description MPC5200B Users Guide, Rev. 1 Programmer’s Model Packet Size 31 lsb 9-23...
Page 289: Sclpc Start Address Register—Mbar + 0X3C04
Table 9-15. SCLPC Control Register Reserved Description 1 = SCLPC will read from the peripheral, i.e. Fifo Receive 0 = SCLPC will write to the peripheral, i.e. Fifo Transmit MPC5200B Users Guide, Rev. 1 31 lsb Reserved Flush 31 lsb...
Page 290: Sclpc Enable Register—Mbar + 0X3C0C
Description 1. Although RC does *not* reset this register interface, it does clear interrupt and interrupt status conditions. 2. Never reset the SCLPC Controller during a transaction (tx or rx). MPC5200B Users Guide, Rev. 1 Programmer’s Model Reserved 31 lsb...
Page 291: Sclpc Bytes Done Status Register—Mbar + 0X3C
Note: This bit (and any interrupt) is also cleared if; 1) RC bit is set, 2) ME bit is clear, or 3) Restart occurs. — Reserved 9-26 Notes Description Reserved Bytes Done Read Only Description MPC5200B Users Guide, Rev. 1 Bytes Done Read Only 31 lsb Freescale Semiconductor...
Page 292 Bytes Done is updated dynamically by the SCLPC state machine to represent the actual number of bytes transmitted at a given point in time. At the normal conclusion of a Packet, the bytes_done field should match the Packet_Size field. MPC5200B Users Guide, Rev. 1 Freescale Semiconductor 9-27...
Page 293: Lpc Rx/Tx Fifo Data Word Register—Mbar + 0X3C40
• Section 9-21, LPC Rx/Tx FIFO Alarm Register (0x3C4C) • Section 9-22, LPC Rx/Tx FIFO Read Pointer Register (0x3C50) • Section 9-23, LPC Rx/Tx FIFO Write Pointer Register (0x3C54) FIFO_Data_Word FIFO_Data_Word MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 294: Lpc Rx/Tx Fifo Status Register—Mbar + 0X3C
FIFO must be written to a level in which the space remaining is less than the granularity bit setting. Emty FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state. 16:31 — Reserved Freescale Semiconductor Description Reserved Description MPC5200B Users Guide, Rev. 1 Programmer’s Model Full Emty 31 lsb 9-29...
Page 295: Lpc Rx/Tx Fifo Alarm Register—Mbar + 0X3C4C
FIFO contains 32Bytes or less. Once asserted, alarm does not negate until high level mark is reached, as specified by FIFO control register granularity bits. 9-30 Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb 31 lsb Alarm Freescale Semiconductor...
Page 296: Lpc Rx/Tx Fifo Write Pointer Register—Mbar + 0X3C54
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in special cases, but this disrupts data flow integrity. Value represents the Read address presented to the FIFO RAM. Freescale Semiconductor Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 Programmer’s Model 31 lsb ReadPtr 31 lsb WritePtr 9-31...
Page 297 LocalPlus Bus (External Bus Interface) Notes MPC5200B Users Guide, Rev. 1 9-32 Freescale Semiconductor...
Page 298 The MPC5200B contains PCI central resource functions such as the PCI Arbiter bus clock is always sourced from the MPC5200B and either equal to 1, 1/2 the frequency of the Slave bus clock (IP bus clock) or 1/4 the frequency of the XL Bus clock. Even when the PCI internal controller is disabled, the PCI clock is sourced by the MPC5200B.
Page 299: Pci External Signals
Req/Gnt Controller Config Config Interface Master bus Target Target Interface Master bus/ Com- Initiator mBus Interface Initiator Figure 10-1. PCI Block Diagram Table 10-1. PCI External Signals Definition MPC5200B Users Guide, Rev. 1 External REQ/GNT External PCI bus Freescale Semiconductor...
Page 300: Pci_Ad[31:0] - Address/Data Bus
PCI_RST - Reset The PCI_RST signal is asserted active low by MPC5200B to reset the PCI bus. This signal is asserted after MPC5200B reset and must be negated to enable usage of the PCI bus. An external shared pull-up resistor is required on this pin.
Page 301 10.3 Registers MPC5200B has several sets of registers that control and report status for the different interfaces to the PCI controller: PCI Type 0 Configuration Space Registers, General Status/Control Registers, and Communication Sub-System Interface Registers. All of these registers are accessible as offsets of MBAR (the PCI interface is located starting at offset 0x0D00 relative to the MBAR register’s value, while the BestComm interface starts at offset 0x3800).
Page 302 Reserved Tx Transaction Control Register Tx Bytes Done Counts Tx Packets Done Counts Reserved Tx FIFO Read Pointer Tx FIFO Write Pointer MPC5200B Users Guide, Rev. 1 Registers Name Name Tx Packet Size Tx Start Address Tx Enables Tx Next Address...
Page 303: Pci Controller Type 0 Configuration Space
0xFC 10.3.1 PCI Controller Type 0 Configuration Space MPC5200B supplies a type 0 PCI Configuration Space header. These registers are accessible as an offset from MBAR Map) or through externally mastered PCI Configuration Cycles. Register Memory The internal PCI controller can discover itself (by means of connecting an AD line [preferably AD24 to AD31]to the PCI _IDSEL input).
Page 304: Registers
RESET Bits Name 0:15 Device ID This field is read-only and represents the PCI Device Id assigned to MPC5200B Its value is: 0x5809. 16:31 Vendor ID This field is read-only and represents the PCI Vendor Id assigned to MPC5200B Its value is: 0x1057.
Page 305 Special Cycle) with a Master-Abort. This register is read-write-clear (RWC) via PCI (MA) configuration cycles. Target Abort This bit is set whenever MPC5200B is the PCI master and a transaction is terminated by a Received Target Abort from the currently-addressed target. This register is read-write-clear (RWC) via (TR) PCI configuration cycles.
Page 306 This bit indicates whether or not MPC5200B has the ability to serve as a master on the PCI Enable bus. A value of 1 indicates this ability is enabled. If MPC5200B is used as a master on the PCI bus (via XL bus or CommBus), a 1 should be written to this bit during initialization. Even if set to 0, a transaction initiated by an internal master (the core, BestComm) is allowed to take place.
Page 307 This bit is programmable (read/write from both the IP bus and PCI bus Configuration cycles). IO access Fixed to 0. This bit is not implemented because there is no MPC5200B IO type space Control accessible from the PCI bus. The PCI base address registers are Memory address ranges (IO) only.
Page 308 Initialization software should write a 0x00 to this register location. 16:23 Latency Timer This register contains the latency timer value, in PCI clocks, used when MPC5200B is the PCI master. The lower three bits of the register are hardwired low and the upper five bits are programmable (read/write from both the IP bus and PCI bus Configuration cycles).
Page 309 RESET Bits Name Base Address MPC5200B PCI Base Address Register 1 (1Gbyte). Applies only when MPC5200B is Register 1 target. These bits are programmable (read/write from both the IP bus and PCI bus (BAR1) Configuration cycles). This BAR register shall be used to point at the local SDRAM/DDR Memory Space.
Page 310: Global Status/Control Register Pcigscr(Rw) —Mbar + 0X0D
The register is read/write to/from the Slave bus, but read only from the PCI bus. Note: The MPC5200B does NOT support initiator latency time-outs, the internal PCI Arbiter does not support preemption of the internal masters XIPCI or SCPCI. The internal master is granted until the transaction has been completed.
Page 311 This bit enables CPU Interrupt generation when a PCI System Error is detected on the Interrupt Enable SERR line. When enabled and SERR asserts, software must clear the SE status bit to (SEE) clear the interrupt condition. 10-14 Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 312 The reset value of the bit is 1 (PCI RST asserted). Note: A global PCI reset should be asserted just by the MPC5200B controller. Any external common reset controller signal will be ignored by the internal PCI controller.
Page 313 Unused bits. Software should write zero to this register. Enable 0 This bit enables a transaction in BAR0 space. If this bit is zero and a hit on MPC5200B PCIBAR0 occurs, the target interface gasket will abort the PCI transaction.
Page 314 Unused bits. Software should write zero to this register. Enable 1 This bit enables a transaction in BAR1 space. If this bit is zero and a hit on MPC5200B PCI BAR1 occurs, the target interface gasket will abort the PCI transaction.
Page 315 PCI page address onto the XL Bus address. A “1” in the Address Mask byte indicates that the XL Bus address bit will be passed to PCI unaltered. 10-18 Description MPC5200B Users Guide, Rev. 1 Window 0 Address Mask 31 lsb Reserved...
Page 316 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) —MBAR + 0x0D74 msb 0 Window 1 Base Address RESET Window 1 Translation Address RESET Freescale Semiconductor Table 1. MPC5200B Users Guide, Rev. 1 Registers Window 1 Address Mask 31 lsb Reserved 10-19...
Page 317 Window 0 Reserved Control Window 2 Control Description Table 10-15. If bit[3] is set to “1”, the value of these bits MPC5200B Users Guide, Rev. 1 Window 2 Address Mask 31 lsb Reserved Window 1 Control 31 lsb Reserved Freescale Semiconductor...
Page 318 For a Write transaction an interrupt will be generated, for a Read transaction an interrupt and a TEA on the XL Bus will be generated. Freescale Semiconductor Description MPC5200B Users Guide, Rev. 1 Registers Reserved 31 lsb...
Page 319 PCI Arbiter Register PCIARB(RW) —MBAR + 0x0D8C msb 0 Reserved RESET RESET Bits Name Reserved Unused bits. Software should write zero to this register. 10-22 Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 320: Configuration Address Register Pcicar (Rw) —Mbar + 0X0Df
Unused bits. Software should write zero to this register. 8:15 This register field is an encoded value used to select the target bus of the configuration Number access. For target devices on the PCI bus connected to MPC5200B, this field should be set to 0x00. 16:20 Device This field is used to select a specific device on the target bus.
Page 321 (addressing is assumed to be sequential from the start address). 10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 msb 0 Reserved RESET 10-24 Packet_Size[31:16] Packet_Size[15:2] Description Start_Add Start_Add Description PCI_cmnd 0111 MPC5200B Users Guide, Rev. 1 31 lsb PacketSize[1:0] 31 lsb Max_Retries Freescale Semiconductor...
Page 322 The default setting is 0, incrementing the address by 4 (4 byte data bus). (DI) Note: This feature is recommended when an external FIFO (with a fixed address) must be written. Freescale Semiconductor Max_Beats Reserved Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb Reserved 10-25...
Page 323: Tx Enables Pciter(Rw)—Mbar + 0X380C
Multi-Channel DMA is controlling operation, but in such a case someone should be polling the status bits to prevent a possible lock-up condition. 10-26 Reserved Reserved Reserved Description for Bus Error descriptions. Normally this bit will be low MPC5200B Users Guide, Rev. 1 31 lsb Section 10.3.3.1.9, Tx Status Freescale Semiconductor...
Page 324: Tx Next Address Pcitnar(R) —Mbar + 0X
Start_Add value whenever the Start_Add is reloaded. It is intended to be accurate even in the case of abnormal terminations on the PCI bus. Freescale Semiconductor Description Next_Address Next_Address Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb 10-27...
Page 325: Tx Packets Done Counts Pcitpdcr(R) —Mbar + 0X
Bytes_Done value will read zero at the end of a successful packet and the Packets_Done field will be incremented. 10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) —MBAR + 0x3820 msb 0 RESET 10-28 Last_Word Last_Word Description Bytes_Done Bytes_Done Description Packets_Done MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 326: Tx Status Pcitsr(Rwc) —Mbar + 0X381C
(BE2) error Enable bit (BE). If software is polling this Byte and wishes to disregard this error it must mask this bit out. Freescale Semiconductor Packets_Done Description Reserved Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb 31 lsb 10-29...
Page 327: Tx Fifo Data Register Pcitfdr(Rw) —Mbar + 0X
Unused. Software should write zero to these bits. 10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840 msb 0 RESET RESET 10-30 Description FIFO_Data_Word uninitialized random 16 bit value FIFO_Data_Word uninitialized random 16 bit value MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 328: Tx Fifo Status Register Pcitfsr(R/Rwc) —Mbar + 0X3844
The FIFO is empty. This is not a sticky bit or error condition. 16:31 Reserved Unused. Software should write zero to these bits. Freescale Semiconductor Description Reserved Reserved Description MPC5200B Users Guide, Rev. 1 Registers Full Alarm Empty 31 lsb 10-31...
Page 329: Tx Fifo Control Register Pcitfcr(Rw) —Mbar + 0X3848
Unused. Software should write zero to these bits. 16:31 Reserved Unused. Software should write zero to these bits. (R/W) 10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0x384C msb 0 RESET 10-32 Reserved Description Reserved MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 330 0x20 (32 bytes) for the Multi-Channel DMA to continue to write enough data to complete at least one PCI burst.) Note: TX PCI FIFO is 512 bytes deep. Freescale Semiconductor Alarm Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb Alarm 10-33...
Page 331: Tx Fifo Read Pointer Register Pcitfrpr(Rw) —Mbar + 0X3850
PCI Rx is controlled by 13 32-bit registers. These registers are located at an offset from MBAR. Register addresses are relative to this offset. 10-34 Reserved ReadPtr Description Reserved WritePtr Description MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 332: Rx Packet Size Pcirpsr(Rw) —Mbar + 0X3880
This register will not increment as the PCI packet proceeds. 10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) —MBAR + 0x3888 msb 0 Reserved RESET Freescale Semiconductor Packet_Size[31:16] Packet_Size[15:2] Description Start_Add Start_Add Description PCI_cmnd 1100 MPC5200B Users Guide, Rev. 1 Registers 31 lsb Packet_Siz[1:0] 31 lsb Max_Retries 10-35...
Page 333 0, increment address by 4 (4 byte data bus). Incrementing Note: This feature is recommended when reading from an external FIFO (having a fixed (DI) address). 10-36 Max_Beats Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Reserved Freescale Semiconductor...
Page 334: Rx Enables Pcirer (Rw) —Mbar + 0X388C
Multi-Channel DMA is controlling operation, but in such a case software should poll the status bits to prevent a possible lock-up condition. Freescale Semiconductor Reserved Reserved Description for Bus Error descriptions. Normally this bit will be 0 MPC5200B Users Guide, Rev. 1 Registers 31 lsb Section 10.3.3.2.9, Rx Status 10-37...
Page 335: Rx Next Address Pcirnar(R) —Mbar + 0X3890
Start_Add value when Start_Add is reloaded. This register is intended to be accurate even if an abnormal PCI bus termination occurs. 10.3.3.2.6 Rx Last Word PCIRLWR(R) —MBAR + 0x3894 msb 0 RESET 10-38 Description Next_Address Next_Address Description Last_Word MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 336: Rx Bytes Done Counts Pcirdcr(R) —Mbar + 0X
Bytes_Done value reads 0 at the end of a successful packet and the Packets_Done field is incremented. 10.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) —MBAR + 0x38A0 msb 0 RESET RESET Freescale Semiconductor Last_Word Description Bytes_Done Bytes_Done Description Packets_Done Packets_Done MPC5200B Users Guide, Rev. 1 Registers 31 lsb 31 lsb 31 lsb 10-39...
Page 337: Rx Status Pcirsr (R/Sw1) —Mbar + 0X389C
FIFO Error status register. Also, the error condition must be cleared at the FIFO prior to clearing this Sticky bit or this flag will continue to assert. 10-40 Description Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 338: Rx Fifo Data Register Pcirfdr(Rw) —Mbar + 0X38C0
FIFO data will be corrupted. 10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) —MBAR + 0x38C4 msb 0 RESET Freescale Semiconductor Description FIFO_Data_Word uninitailized random 16 bit value FIFO_Data_Word uninitalized random 16 bit value Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb 10-41...
Page 339: Rx Fifo Control Register Pcirfcr(Rw) —Mbar + 0X38C8
Unused. Software should write zero to these bits. 10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8 msb 0 Reserved RESET RESET 10-42 Reserved Description Reserved MPC5200B Users Guide, Rev. 1 Full Alarm Empty 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 340: Rx Fifo Alarm Register Pcirfar(Rw) —Mbar + 0X38Cc
The alarm, once asserted, will not negate until the high level mark is reached, as specified by the Granularity bits in the Rx FIFO Control Register. Note: The PCI RX FIFO is 512 bytes deep. Freescale Semiconductor Description Reserved Alarm Description MPC5200B Users Guide, Rev. 1 Registers 31 lsb Alarm 10-43...
Page 341: Rx Fifo Write Pointer Register Pcirfwpr (Rw) —Mbar + 0X38D4
Communication Sub-System, which can be accessed by the Multi-Channel DMA engine. The internal PCI target interface provides external PCI masters access into two memory windows of MPC5200B address space. PCI arbitration is handled external to this module, by the MPC5200B internal PCI arbiter.
Page 342: Pci Bus Protocol
Only the internal PCI arbiter of the MPC5200B can be used as PCI arbiter for the PCI bus. An external PCI arbiter cannot be used. The registers, described in Section 10.3, Registers, control and provide information about these multiple interfaces. An additional Configuration interface allows internal access through the Slave bus(also referred to as IP bus) to the PCI Type 0 Configuration registers, which are accessible to both MPC5200B and external masters through the PCI bus.
Page 343: Pci Transactions
IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates the final data transfer (by asserting TRDY), the PCI bus may return to the idle state (both FRAME and IRDY are negated). No Fast Back-to-Back transactions are supported by the MPC5200B. 10.4.1.3 PCI Transactions The figures in this section show the basic “memory read”...
Page 344: Pci Bus Commands
PCI I/O space. The I/O-write command accesses agents mapped into the PCI I/O space. The memory read command accesses agents mapped into PCI memory space. MPC5200B Users Guide, Rev. 1 Functional Description (wait) Data Phase 2 Definition 10-47...
Page 345: Addressing
1111 Memory write and invalidate Though MPC5200B supports many PCI commands as an initiator, the Communication Sub-System Initiator interface is intended to use PCI Memory Read, and Memory Write commands. 10.4.1.5 Addressing PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configuration space. Address decoding on the PCI bus is performed by every device for every PCI transaction.
Page 346: I/O Space Addressing
For zero-word-aligned bursts and single-beat transactions, MPC5200B drives AD[1:0] to 0b00. As a target, the MPC5200B treats cache wrap mode as a reserved memory mode. MPC5200B will return the first beat of data and then signal a disconnect without data on the second data phase.
Page 347: Address Decoding
Only one device on a PCI bus may use subtractive address decoding, and its use is optional. 10-50 Target configuration doubleword number 11 10 Function Number 16 15 11 10 Function Device Number Number Number MPC5200B Users Guide, Rev. 1 2 1 0 Number Figure 10-5 illustrates the contents of 2 1 0 Number Freescale Semiconductor...
Page 348: Initiator Arbitration
10.4.3 Configuration Interface The PCI bus protocol requires the implementation of a standardized set of registers for most devices on the PCI bus. MPC5200B implements a Type 0 Configuration register set or header. They are described in registers are primarily intended to be read or written by the PCI configuring master at initialization time through the PCI bus. MPC5200B provides internal access to these registers through a Slave bus interface.
Page 349: Endian Translation
If the target for an XL bus read from PCI disconnects part way through the burst, MPC5200B may have to handle a local memory access from an alternate PCI master before the disconnected transfer can continue.
Page 350 Freescale Semiconductor OP6 OP7 OP6 OP7 OP6 OP7 OP5 OP6 OP7 OP5 OP6 OP7 OP5 OP6 OP4 OP5 OP6 OP7 OP4 OP5 OP6 MPC5200B Users Guide, Rev. 1 Functional Description Transactions (continued) PCI Bus 31:2 23:1 15:8 [2:0] [3:0] 1101...
Page 351: Configuration Mechanism
0x1F8. The register specifies the target PCI bus, device, function, and configuration register to be accessed. A read or a write to the MPC5200B window defined as PCI I/O space, in PCIIWCR, causes the host bridge to translate the access into a PCI configuration cycle if the enable bit in the Configuration Address Register is set and the device number does not equal 0b1_1111.
Page 352: Type 0 Configuration Translation
AD[31:0] Signals During Address Phase IDSEL (only one signal high) Figure 10-7. Type 0 Configuration Translation For Type 0 configuration cycles, MPC5200B translates the device number field of the Configuration Address Register into a unique IDSEL line shown in Table 10-8.
Page 353: Type 1 Configuration Translation
MPC5200B can issue PCI configuration transactions to itself. A Type 0 configuration initiated by MPC5200B can access its own configuration space by asserting its IDSEL input signal. This is the only way MPC5200B can clear its own status register bits (read-write-clear).
Page 354: Transaction Termination
BAR1 in MPC5200B PCI Type 00h Configuration space register (PCI space). When there is a hit on MPC5200B PCI base address ranges (0 or 1), the upper bits of the address are written over by this register value to address some space in MPC5200B. One 256Kbyte base address range (BAR0) maps to non-prefetchable local memory and one 1Gbyte range (BAR1) targeted to prefetchable memory.
Page 355: Reads From Local Memory
Reads from Local Memory MPC5200B can provide continuous data to a PCI master using two 32-byte buffers. The PCI controller bursts reads internally at each 32-byte PCI address boundary. The data is stored in the first 32-byte buffer until either the PCI master flushes the data or the transaction terminates (FRAME deasserts).
Page 356: Target Abort
PCI Multi-Channel DMA activities. In general, this block will be used by functions in the Multi-Channel DMA API. Freescale Semiconductor 15:8 A[29:31] 0x0D68. Section 10.3.2.4, Target Control Register PCITCR(RW) —MBAR + MPC5200B Users Guide, Rev. 1 Functional Description XL bus Data Bus Byte Lanes Section 10.3.2.2, Section 10.3.2.3, Target Base Address 0x0D6C, (Section 10.4.2, Initiator...
Page 357: Access Width
The following list is the recommended procedure for setting up either the Transmit or Receive controller. Set the Start Address 10-60 Data Bus PCI_ 15:8 [1:0] MPC5200B Users Guide, Rev. 1 Table 10-13 shows the byte lane mapping Transactions PCI data bus Data Bus [3:0]...
Page 358: Restart And Reset
FIFO. This operation is expected to be accomplished through Multi-Channel DMA which can also perform the register writes to the controller, including necessary Restart sequences. Freescale Semiconductor 0x3888, in which case BE[3:0] = 1100. MPC5200B Users Guide, Rev. 1 Functional Description Section 10.3.3.2.3, Rx Transaction 10-61...
Page 359: Alarms
Internal Interrupt The PCI module is capable of generating 3 interrupts to MPC5200B interrupt controller in MPC5200B SIU. Each interrupt can be enabled for a variety of conditions, mostly error conditions. For the XL bus Initiator interface, the internal interrupt can be enabled for Retry errors, Target Aborts and Initiator (Master) Aborts.
Page 360: Application Information
Freescale Semiconductor Initiator Register Settings Configuration Initiator Window Cache Line Configuration bits Size Register= IO/M# false true MPC5200B Users Guide, Rev. 1 Application Information 0x0D80. Address PCI Transaction Register Controller (XL Bus Initiator Interface) -> device PCI Target number b1_1111...
Page 361: Address Maps
Window Translation Register to address Initiator Window space. In that event, MPC5200B-as-Target transaction would propagate through MPC5200B’s internal bus and request PCI bus access as the PCI Initiator. The PCI arbiter could see the PCI bus as busy (target read transaction in progress) and only a time-out would free the PCI bus.
Page 362: Outbound Address Translation
10.6.2.1.2 Outbound Address Translation Figure 10-9 shows example XL Bus Initiator Window configurations. Overlapping the inbound memory window (MPC5200B Memory) and the outbound translation window is not supported and can cause unpredictable behavior. This figure doesn’t show configuration mechanism. Freescale Semiconductor...
Page 363: Base Address Register Overview
Associated with PCI I/O Associated with PCI Non-Prefetchable Memory 10.6.2.1.3 Base Address Register Overview Table 10-15 shows the available accessibility for all PCI associated base address and translation address registers in MPC5200B. Base Address Register Function Register BAR0 PCI Base Address Register 0...
Page 364: Xl Bus Arbitration Priority
The only resolution that guarantees that this live lock scenario will not occur is to set all the XL Bus Arbiter master priorities to be equal. Additionally, it is usually preferable that all master priorities are not set to zero, as this can generate an interrupt by the XL Bus Arbiter, if enabled. MPC5200B Users Guide, Rev. 1 Freescale Semiconductor 10-67...
Page 365 Application Information MPC5200B Users Guide, Rev. 1 10-68 Freescale Semiconductor...
Page 366: Bestcomm Key Features
Ultra-33. For more ATA Standards information, refer to "American National Standard for Information Technology—AT Attachment with Packet Interface Extension (ATA/ATAPI-4)". A dedicated MPC5200B pin for ATA reset is not provided. An appropriate signal on the board should be routed to the reset input on the ATA HRESET connector.
Page 367: Bestcomm Write
ATA Ultra DMA Timing 3 Register (0x3A0C) • ATA Ultra DMA Timing 4 Register (0x3A10) • ATA Ultra DMA Timing 5 Register (0x3A14) IORDY Reserved Description Table 11-29.) MPC5200B Users Guide, Rev. 1 (0x3A18) (0x3A1C) (0x3A20) (0x3A24) (0x3A28) Reserved 31 lsb Freescale Semiconductor...
Page 368: Ata Host Status Register—Mbar + 0X3A04
RESET: Freescale Semiconductor Description Table 11-2. ATA Host Status Register RERR WERR Reserved Description Table 11-29.). Table 11-3. ATA PIO Timing 1 Register MPC5200B Users Guide, Rev. 1 ATA Register Interface Reserved 31 lsb pio_t2_8 31 lsb Reserved 11-3...
Page 369: Ata Pio Timing 2 Register—Mbar + 0X3A0C
ATA Multiword DMA Timing 1 Register—MBAR + 0x3A10 Table 11-5. ATA Multiword DMA Timing 1 Register msb 0 dma_t0 RESET: dma_tk RESET: 11-4 Description Table 11-4. ATA PIO Timing 2 Register Description MPC5200B Users Guide, Rev. 1 pio_t1 31 lsb Reserved dma_td 31 lsb dma_tm Freescale Semiconductor...
Page 370: Ata Multiword Dma Timing 2 Register—Mbar + 0X3A14
ATA Ultra DMA Timing 1 Register—MBAR + 0x3A18 Table 11-7. ATA Ultra DMA Timing 1 Register msb 0 udma_t2cyc RESET: udma_tds RESET: Freescale Semiconductor Description Description MPC5200B Users Guide, Rev. 1 ATA Register Interface dma_tj 31 lsb Reserved udma_tcyc 31 lsb udma_tdh 11-5...
Page 371: Ata Ultra Dma Timing 2 Register—Mbar + 0X3A1C
ATA Ultra DMA Timing 3 Register—MBAR + 0x3A20 Table 11-9. ATA Ultra DMA Timing 3 Register msb 0 udma_tmli RESET: udma_tenv RESET: 11-6 Description Description MPC5200B Users Guide, Rev. 1 udma_tdvh 31 lsb udma_tli udma_taz 31 lsb udma_tsri Freescale Semiconductor...
Page 372: Ata Ultra Dma Timing 4 Register—Mbar + 0X3A24
DMARDY. Count value is based on system clock operating frequency. 24:31 udma_tack Setup and hold times for DMACK before negation or assertion. Count value is based on system clock operating frequency. Freescale Semiconductor Description Description MPC5200B Users Guide, Rev. 1 ATA Register Interface udma_trfs 31 lsb udma_tac 11-7...
Page 373: Ata Ultra Dma Timing 5 Register—Mbar + 0X3A28
ATA uses a single FIFO that changes direction based on the Rx/Tx mode. Software controls direction change and flushes FIFO before changing directions. FIFO memory is 512Bytes (Four 8 x 128 memories). 11-8 Reserved Description ata_shre_cnt Table 11-12. ata_share_cnt Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb 31 lsb Freescale Semiconductor...
Page 374: Ata Rx/Tx Fifo Data Word Register—Mbar + 0X3A3C
ATA Rx/Tx FIFO Alarm Register (0x3A40) • ATA Rx/Tx FIFO Read Pointer Register (0x3A44) • ATA Rx/Tx FIFO Write Pointer Register FIFO_Data_Word FIFO_Data_Word Description Reserved Description MPC5200B Users Guide, Rev. 1 ATA Register Interface (0x3A48) (0x3A4C) (0x3A50) 31 lsb Full Emty 31 lsb 11-9...
Page 375: Ata Rx/Tx Fifo Control Register—Mbar + 0X3A44
001 = FIFO stops data request when only one long word of space remains. 8:31 — Reserved 11.3.2.4 ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48 Table 11-16. ATA Rx/Tx FIFO Alarm Register msb 0 RESET: 11-10 Description Reserved Description Reserved MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 376: Ata Rx/Tx Fifo Read Pointer Register—Mbar + 0X3A4C
ATA Rx/Tx FIFO Write Pointer Register—MBAR + 0x3A50 Table 11-18. ATA Rx/Tx FIFO Write Pointer Register msb 0 RESET: Reserved RESET: Freescale Semiconductor Alarm Description Reserved ReadPtr Description Reserved WritePtr MPC5200B Users Guide, Rev. 1 ATA Register Interface 31 lsb 31 lsb 31 lsb 11-11...
Page 377: Ata Drive Registers—Mbar + 0X3A00
11.3.3 ATA Drive Registers—MBAR + 0x3A00 The ATA drive registers are physically located inside the drive controller on the ATA disk drive. The MPC5200B ATA Host Controller provides access to these registers using the chip selects and address bits. ATA Drive is controlled by 32-bit registers. These registers are located at an offset from MBAR of 0x3a00. Register addresses are relative to this offset.
Page 378: Ata Drive Alternate Status Register—Mbar + 0X3A5C
Data L Lower byte of drive data (read/write) 16:31 — Reserved Freescale Semiconductor Rsvd Reserved Description Table 11-21. ATA Drive Data Register Reserved Description MPC5200B Users Guide, Rev. 1 ATA Register Interface Reserved 31 lsb Data L 31 lsb 11-13...
Page 379: Ata Drive Features Register—Mbar + 0X3A64
ATA drive status register. Register content is not valid when drive is in sleep mode. 8:31 — Reserved 11-14 Table 11-22. ATA Drive Features Register Reserved Description Table 11-23. ATA Drive Error Register ABRT Data Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 380: Ata Drive Sector Count Register—Mbar + 0X3A68
DMACK is not asserted. If register is written when BSY and DRQ bits are set to 1, the result is indeterminate. Register content is not valid when drive is in sleep mode. 8:31 — Reserved Freescale Semiconductor Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 ATA Register Interface Reserved 31 lsb Reserved 31 lsb 11-15...
Page 381: Ata Drive Cylinder Low Register—Mbar + 0X3A70
DMACK is not asserted. If this register is written when BSY and DRQ bits are set to 1, the result is indeterminate. Register content is not valid when drive is in sleep mode. 8:31 — Reserved 11-16 Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 382: Ata Drive Device/Head Register—Mbar + 0X3A78
ATA Drive Device Command Register—MBAR + 0x3A7C Table 11-29. ATA Drive Device Command Register msb 0 Data RESET: RESET: Freescale Semiconductor Data Reserved Description Rsvd Reserved MPC5200B Users Guide, Rev. 1 ATA Register Interface Reserved 31 lsb UDMA READ WRITE 31 lsb 11-17...
Page 383 Bit is set when READ DMA command is issued. WRITE Bit is set when WRITE DMA command is issued. 16:31 — Reserved 11-18 Description until task loop count expires. Drive interrupt must be enabled by clearing bit 1 of drive control MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 384: Ata Drive Device Status Register—Mbar + 0X3A7C
DEVICE RESET command. Register content is not valid when drive is in sleep mode. Freescale Semiconductor Reserved ERR Rsvd HUT Reserved Description MPC5200B Users Guide, Rev. 1 ATA Register Interface UDMA Read Write 31 lsb 11-19...
Page 385: Ata Host Controller Operation
11-20 Description until task loop count expires. Drive interrupt must be enabled by clearing bit 1 of drive control ATA_mode_timing_spec ipbi_clock_period 1 ----------------------------------------------------------------------------------------------------------------------- - clock_period × 2 XCVR_PROP_DLY clock_period MPC5200B Users Guide, Rev. 1 – clock_period 1 – Freescale Semiconductor...
Page 386: Pio State Machine
Initiate and complete data transfers according to protocols described in ATA-4 specification. ATA host hardware does data transfers per chosen protocol. Hardware also maintains proper handshaking with the MPC5200B system. The ATA state machine is a combination of several small state machines. The data transfers is initiated by the software. The software chooses the mode of operation and sets up needed registers in the ATA Host Controller IPBI module.
Page 387: Dma State Machine
Ready for new write data Begin next cycle Start TJ, Start TN Negate DMACK, Go to Idle Clear DMA_In_Progress flag. Allow CS0, CS1 to be driven MPC5200B Users Guide, Rev. 1 Dependencies — IORDY=1 — — Dependencies DMARQ asserted by drive —...
Page 388: Signals And Connections
Bus for four PCI Clock Cycles, the LocalPlus Bus cannot initiate a bus cycle for approximately 10 cycles after the positive edge of HRESET. Therefore, bus conflict will not occur. Freescale Semiconductor Table 11-33. MPC5200B External Signals Description Description NOTE MPC5200B Users Guide, Rev.
Page 389: Ata Interface Description
Note: On system board: 1. All outgoing signals need 3.3V to 5V level shifters. 2. All incoming signals need 5V to 3.3V level shifters or 5V tolerant input buffers on MPC5200B ATA signals. Figure 11-2. Connections—Controller Cable, System Board, MPC5200B 11.6 ATA Interface Description Table 11-34.
Page 390 ‘isolate’ the ATA bus from the LocalPlus (shared) bus. It can force the transceiver direction "MPC5200B -> disk drive". Only during an ATA read is this signal allowed to go low, forcing tranceiver direction "disk drive ->MPC5200B".
Page 391: Ata Bus Background
ATA is the interface name adopted by the American National Standards Institute (ANSI). Thus far, ANSI has published ATA, ATA-2, ATA-3 and ATA-4 interfaces. More work is underway for ATA-5 and future extensions of the ATA interface. ATA standards. MPC5200B is compliant with the latest officially published ANSI ATA-4 interface. 11-26 D E V I C E MPC5200B Users Guide, Rev.
Page 392: Ata Modes
Ultra DMA—0,1,2 Table 11-36. ATA Physical Level Modes Cycle Time (ns) Transfer Rate (MB/s) 11.1 16.7 13.3 16.7 16.7 MPC5200B Users Guide, Rev. 1 ATA Bus Background introduced Relative to IDE/ATA Standard ATA-2 (IORDY required) ATA-2 (IORDY required) ATA-2 ATA-2 ATA-4...
Page 393: Ata Register Addressing
LBA bits Drive/head LBA bits Status Invalid address Figure 11-1. Each drive contains a number of disks, each with one or MPC5200B Users Guide, Rev. 1 Function WRITE (DIOW) Control Block Registers Not used Not used Not used Device control...
Page 394: Physical/Logical Addressing Modes
GAP2 Sync Cylinder Head Sector Freescale Semiconductor Write Splice VFO Sync 512 Bytes data Head Sector Sync 512 Bytes data Figure 11-4. ATA Sector Format MPC5200B Users Guide, Rev. 1 ATA Bus Background GAP3 Soft-Sector Format GAP3 Hard-Sector Format 11-29...
Page 395: Ata Transactions
HOST: Read ATA control/command block registers to get status. DRIVE: Clear interrupt after reading status register. HOST: Read ATA data register to get all sectors from sector buffer. 11-30 Table 11-36. Timing and sequence information are given MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 396: Class 2—Pio Write
HOST: Read ATA control/command block registers to get status. DRIVE: Clear interrupt after reading status register. Figure 11-6 shows the PIO Write process. Freescale Semiconductor Read Read Sector Status Buffer Read Read Sector Sector MPC5200B Users Guide, Rev. 1 ATA Bus Background Read Read Sector Status Buffer 11-31...
Page 397: Class 3—Non-Data Command
Write sub-command code 0x03 to features register to set transfer mode, based on value in sector count register. 11-32 Write Read Sector Status Buffer Write Sector Set Up Send Register Command Block Execute Execute Command Command MPC5200B Users Guide, Rev. 1 Write Read Sector Status Buffer Write Sector Freescale Semiconductor...
Page 398 [1] when ready to transfer data per multiword DMA timing or ultra DMA Table 11-38. DMA Command Parameters Parameters Used (Registers) Sector Sector Features Count Number/LBA MPC5200B Users Guide, Rev. 1 ATA Bus Background Cylinder Device/Head/LBA HI/LO/LBA D/H Both D/H Both 11-33...
Page 399: Flow Diagram—Dma Command Protocol
Drive: Set error status Drive: Clear BSY = 0 and DRQ = 0 Drive: Assert INTRQ Host: Read Status register Host: Read Status register Drive: Negate INTRQ MPC5200B Users Guide, Rev. 1 ready to transfer data ready to transfer data Drive: Transfer Done...
Page 400: Multiword Dma Transactions
DMA with desired mode. When enabled, the ultra DMA protocol is used instead of the multiword DMA protocol. Freescale Semiconductor Carry out DMA Read Read Sector Sector UNDEFINED UNDEFINED MPC5200B Users Guide, Rev. 1 ATA Bus Background Reset Reset Status 11-35...
Page 401: Ata Reset/Power-Up
SRST to 1 to enable the drive for software reset • issue a DEVICE RESET command while the status register BSY bit is set to 1. Hardware reset is a board requirement, not an MPC5200B function unless GPIO is used. 11.8.2 Software Reset The host sets the device control register bit SRST to 1.
Page 402: Ata I/O Cable Specifications
Freescale Semiconductor Can set BSY=0 if Drive 1 not present Can assert DASP to indicate tR Drive 0 active if Drive 1 not present PIO Timing Parameter MPC5200B Users Guide, Rev. 1 ATA I/O Cable Specifications Min/Max Timing 25µs 400ns...
Page 403 ATA Controller Notes MPC5200B Users Guide, Rev. 1 11-38 Freescale Semiconductor...
Page 404: Data Transfer Types
USB device. Freescale Semiconductor Registers, includes: Client Software USB Driver Host Controller Driver Host Controller USB Device Figure 12-1. USB Focus Areas MPC5200B Users Guide, Rev. 1 Overview Figure 12-1 shows the four main Scope of OHCI 12-1...
Page 405: Host Controller Interface
Communication Register. 12-2 OpenHCI Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 . . . Interrupt 31 ..Done Shared RAM Figure 12-2. Communication Channels NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 406: Data Structures
The HCCA includes the “virtual” registers HccaFrameNumber and HccaPad1. The offsets shall be 0x80 (for HccaFrameNumber) and 0x82 (for HccaPad1). In the USB module of the MPC5200B these two “virtual” registers are swapped. The HccaFrameNumber is a copy of the Frame Number field at the USB HC Timing Reference Register.
Page 407: Interrupt Ed Structure
Unused interrupt endpoint placeholders are bypassed and the link is connected to the next available endpoint in the hierarchy. 12-4 Endpoint Poll Interval (ms) Figure 12-4. Interrupt ED Structure NOTE MPC5200B Users Guide, Rev. 1 Interrupt Endpoint Descriptor Placeholder Freescale Semiconductor...
Page 408: Host Control (Hc) Operational Registers
USB /11. 33 MHz * 16 / 11 = 48 MHz (USB frequency) system must be initialized to communicate over the muxed USB port. It MPC5200B Users Guide, Rev. 1 Interrupt Endpoint Descriptor...
Page 409: Control And Status Partition—Mbar + 0X1000
MBAR + 0x1000 + register address (0x1008) (0x100C) (0x1010) (0x1014) Table 12-1. USB HC Revision Register Reserved Description Table 12-2. USB HC Control Register Reserved RWE RWC HCFS MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb CBSR Freescale Semiconductor...
Page 410 InterruptRouting—bit determines routing of interrupts generated by events registered in HcInterruptStatus. The IR Bit is ignored by the MPC5200B. It is here to maintain OHCI compliancy. The interrupt from the USB module is routed to the interrupt controller in the SIU where it can be routed to the SMI or NORMAL interrupt.
Page 411: Usb Hc Command Status Register—Mbar + 0X1008
OwnershipChangeRequest—OS HCD sets this bit to request an HC change of control. When set, HC sets the OwnershipChange field in HcInterruptStatus. After changeover, this bit is cleared and remains clear until the next OS HCD request. 12-8 Description Reserved Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 412: Usb Hc Interrupt Status Register —Mbar + 0X100C
System Management Interrupt (SMI). When the SMI pin is not implemented, the OC bit is tied to 0. 2:24 — Reserved Freescale Semiconductor Description Reserved RHSC Description MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb 12-9...
Page 413: Usb Hc Interrupt Enable Register—Mbar + 0X1010
Writing 1 to a bit in this register sets the corresponding bit, whereas writing 0 to a bit in this register leaves the corresponding bit unchanged. On read, the current value of this register is returned. Table 12-5. USB HC Interrupt Enable Register msb 0 RESET: Reserved RESET: 12-10 Description Reserved RHSC MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 414: Usb Hc Interrupt Disable Register—Mbar + 0X1014
HcInterruptEnable register, whereas writing a ‘0’ to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current value of the HcInterruptEnable register is returned. Table 12-6. USB HC Interrupt Disable Register msb 0 RESET: Freescale Semiconductor Description Reserved MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 12-11...
Page 415: Memory Pointer Partition—Mbar + 0X1018
USB HC Control Head Endpoint Descriptor Register • USB HC Control Current Endpoint Descriptor Register • USB HC Bulk Head Endpoint Descriptor Register 12-12 RHSC Description MBAR + 0x1018 + register address (0x101C) (0x1020) (0x1024) (0x1028) MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 416: Usb Hc Hcca Register—Mbar + 0X1018
HCD may read the content in determining which ED is currently being processed at the time of reading. 28:31 — Reserved Freescale Semiconductor (0x102C) Table 12-7. USB HC HCCA Register HCCA Description PCED PCED Description MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb Reserved 31 lsb Reserved 12-13...
Page 417: Usb Hc Control Head Endpoint Descriptor Register —Mbar + 0X1020
USB HC Bulk Head Endpoint Descriptor Register—MBAR + 0x1028 The HC Head Endpoint Descriptor register contains the physical address of the first bulk list endpoint descriptor. 12-14 CHED CHED Description CCED CCED Description MPC5200B Users Guide, Rev. 1 31 lsb Reserved 31 lsb Reserved Freescale Semiconductor...
Page 418: Usb Hc Bulk Current Endpoint Descriptor Register—Mbar + 0X102C
HCD does not need to read this register as its content is periodically written to the HCCA. Freescale Semiconductor BHED BHED Description BCED BCED Description MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb Reserved 31 lsb Reserved 12-15...
Page 419: Frame Counter Partition—Mbar + 0X1034
Table 12-14. USB HC Frame Interval Register msb 0 RESET: Reserved RESET: 12-16 Table 12-13. USB HC Done Head Register Description MBAR + 0x1034 + register address (0x1034) (0x1038) (0x103C) FSMPS MPC5200B Users Guide, Rev. 1 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 420: Usb Hc Frame Remaining Register—Mbar + 0X1038
16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. Table 12-16. USB HC Frame Number Register msb 0 RESET: Freescale Semiconductor Description Reserved Description Reserved MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb 12-17...
Page 421: Usb Hc Periodic Start Register—Mbar + 0X1040
This register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum 8-Byte LS packet before EOF. Neither the HC nor HCD are allowed to change this value. Table 12-18. USB HC LS Threshold Register msb 0 RESET: 12-18 Description Reserved Description Reserved MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 422: Root Hub Partition—Mbar + 0X1048
Table 12-19. USB HC Rh Descriptor A Register msb 0 POTPGT RESET: Freescale Semiconductor Description MBAR + 0x1048 + register address (0x1048) (0x104C) (0x1054) (0x1058) NOTE MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb Reserved 12-19...
Page 423: Usb Hc Rh Descriptor B Register—Mbar + 0X104C
This register is the second of two registers describing the Root Hub characteristics. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific. 12-20 NPS PSM Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 424: Usb Hc Rh Status Register—Mbar + 0X1050
Reserved bits should always be written 0. msb 0 CRWE RESET: DRWE RESET: Freescale Semiconductor PPCM Description Table 12-21. USB HC Rh Status Register Reserved Reserved MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers 31 lsb OCIC LPSC 31 lsb 12-21...
Page 425: Usb Hc Rh Port1 Status Register—Mbar + 0X1054
HcRhPortStatus registers that are implemented in hardware. The lower 16-bits is used to reflect the port status; the upper 16-bits reflects the status change bits. MPC5200B has NDP = 2, therefore, HcRhPort1Status (MBAR + 1054) and HcRhPort2Status (MBAR + 1058).
Page 426 Writing 0 has no effect. 0 = No change in PES 1 = Change in PES Freescale Semiconductor Reserved LSDA Reserved Description MPC5200B Users Guide, Rev. 1 Host Control (HC) Operational Registers PRSC OCIC PSSC PESC 31 lsb POCI 12-23...
Page 427 Writing 0 has no effect. If CurrentConnectStatus is cleared, a write does not set PortResetStatus. Instead, it sets ConnectStatusChange. This notifies the driver that an attempt was made to reset a disconnected port. 12-24 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 428 If CurrentConnectStatus is cleared, this write does not set PSS. Instead it sets ConnectStatusChange. This notifies the driver an attempt was made to suspend a disconnected port. Freescale Semiconductor Host Control (HC) Operational Registers Description MPC5200B Users Guide, Rev. 1 12-25...
Page 429: Usb Hc Rh Port2 Status Register—Mbar + 0X1058
HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status; the upper word reflects the status change bits. MPC5200B has NDP = 2, therefore, HcRhPort1Status (MBAR + 1054) and HcRhPort2Status (MBAR + 1058).
Page 430 This field is valid only when CurrentConnectStatus is set. ClearPortPower (write) • Writing 1 causes HC to clear the PortPowerStatus bit. • Writing 0 has no effect. Freescale Semiconductor Host Control (HC) Operational Registers Description MPC5200B Users Guide, Rev. 1 12-27...
Page 431 1 = Overcurrent condition detected. ClearSuspendStatus (write) • Writing 1 causes HC to initiate a resume. • Writing 0 has no effect. A resume is initiated only if PSS is set. 12-28 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 432 ClearPortEnable (write)—HCD writes 1 to this bit to clear PortEnableStatus bit. Writing 0 has no effect. CCS is not affected by any write. Note: This bit is always read ‘1b’ when the attached device is non-removable (DeviceRemoveable[NDP]). Freescale Semiconductor Host Control (HC) Operational Registers Description MPC5200B Users Guide, Rev. 1 12-29...
Page 433 Universal Serial Bus (USB) Notes MPC5200B Users Guide, Rev. 1 12-30 Freescale Semiconductor...
Page 434: Bestcomm Functional Description
Many of the peripherals’ port pins serve multiple functions, allowing flexibility in optimizing the system to meet a specific set of integration requirements. For a description of the pin multiplexing scheme and supported functions, refer to Other peripheral functions are included in MPC5200B, but are not directly supported by BestComm. These peripherals include: •...
Page 435: Features Summary
Memory organization is described in the register array pointed to by the Task Base Address Register (TaskBAR). The TaskBAR identifies a location for a table of pointers to multi-channel DMA tasks (Task TABLE or Entry Table). 13-2 NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 436: Descriptors
Additionally, the external request can generate an interrupt for the e300 core. The GPIO, which is indended to generate a DMA request, must be enabled and set up as input, in both cases (see General Purpose I/O (GPIO) chapter). MPC5200B doesn’t support external DMA Acknowledge. 13.13 External DMA Breakpoint The SDMA engine can be halted if the Enable Breakpoint (EB) and the Enable External Breakpoint (E) bits of the SDMA Debug Module Control Register are set and the 603e e300 core hits an Instruction Address Breakpoint or a Data Address Breakpoint.
Page 437: Task Table (Entry Table)
(0x1230) Register (0x1234) • Section 13-36, SDMA Debug Module Status Register (0x1238) (0x123C) (0x1240) Table 13-1. SDMA Task Bar Register taskBar taskBar Description MPC5200B Users Guide, Rev. 1 (0x1244) (0x125C) (0x1260) (0x1264) (0x1270) (0x1274) (0x1278) Freescale Semiconductor (0x1248) (0x124C) (0x1250)
Page 438: Sdma Current Pointer Register—Mbar + 0X1204
SDMA Variable Pointer Register—MBAR + 0x120C Table 13-4. SDMA Variable Pointer Register msb 0 RESET: Freescale Semiconductor CurrentPointer CurrentPointer Description Table 13-3. SDMA End Pointer Register EndPointer EndPointer Description VariablePointer MPC5200B Users Guide, Rev. 1 BestComm DMA Registers—MBAR+0x1200 31 lsb 31 lsb 13-5...
Page 439 SDMA Interrupt Vector, PTD Control Register—MBAR + 0x1210 Table 13-5. SDMA Interrupt Vector, PTD Control Register msb 0 Vector A[7:6] RESET: RESET: 13-6 VariablePointer Description INA[3:0] Vector B[7:6] Reserved MPC5200B Users Guide, Rev. 1 31 lsb INB[3:0] 31 lsb Freescale Semiconductor...
Page 440: Sdma Interrupt Pending Register—Mbar + 0X1214
Prefetch Disable: set to ‘1’ to disable prefetch. Set to ‘0’ to enable prefetch on CommBus 13.15.6 SDMA Interrupt Pending Register—MBAR + 0x1214 Table 13-6. SDMA Interrupt Pending Register msb 0 Rsvd RESET: RESET: Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Description Etn[3:0] TASK[15:0] MPC5200B Users Guide, Rev. 1 EU[7:0] 31 lsb 13-7...
Page 441: Sdma Interrupt Mask Register—Mbar + 0X1218
If the TEA Msk bit in the Mask register is set then no interrupt to the core will be generated. 8:15 EU[7-0] Execution Unit: only EU3 is valid for MPC5200B 16:31 TASK[15:0] Each bit corresponds to an interrupt source defined by the task number or execution unit.
Page 442: Sdma Task Control 0 Register—Mbar + 0X121C
SDMA engine encounters an error in the task. At system reset, this bit is cleared. Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 SDMA Task Control 1 Register IN[4:0] Auto High Hold Start TCR1 (same as for TCR0) Description MPC5200B Users Guide, Rev. 1 Rsvd AS [3:0] 31 lsb 13-9...
Page 443: Sdma Task Control 2 Register—Mbar + 0X1220
Task control register for task 2. Same bit layout as for TCR0 16:31 TCR3 Task control register for task 3. Same bit layout as for TCR0 13-10 Description SDMA Task Control 3 Register TCR2 TCR3 Description MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 444: Sdma Task Control 4 Register—Mbar + 0X1224
Task control register for task 7. Same bit layout as for TCR0 Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 SDMA Task Control 5 Register TCR4 TCR5 Description SDMA Task Control 7 Register TCR6 TCR7 Description MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb 13-11...
Page 445: Sdma Task Control 8 Register—Mbar + 0X122C
Task control register for task 11. Same bit layout as for TCR0 13-12 SDMA Task Control 9 Register TCR8 TCR9 Description SDMA Task Control B Register TCRA TCRB Description MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 446: Sdma Task Control C Register—Mbar + 0X1234
Task control register for task 15. Same bit layout as for TCR0 Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 SDMA Task Control D Register TCRC TCRD Description SDMA Task Control F Register TCRE TCRF Description MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb 13-13...
Page 447: Sdma Initiator Priority 0 Register—Mbar + 0X123C
Initiator Priority register for initiator 3.(or Task3 if PtdControl[16]=1) Same bit layout as IPR0 13-14 SDMA Initiator Priority 1 Register SDMA Initiator Priority 2 Register SDMA Initiator Priority 3 Register Prior [2:0] Description MPC5200B Users Guide, Rev. 1 IPR1 31 lsb IPR3 Freescale Semiconductor...
Page 448: Sdma Initiator Priority 4 Register—Mbar + 0X1240
SDMA Initiator Priority 5 Register SDMA Initiator Priority 6 Register SDMA Initiator Priority 7 Register Description SDMA Initiator Priority 9 Register SDMA Initiator Priority 10 Register SDMA Initiator Priority 11 Register MPC5200B Users Guide, Rev. 1 IPR5 31 lsb IPR7 IPR9 13-15...
Page 449: Sdma Initiator Priority 12 Register—Mbar + 0X1248
Initiator Priority register for initiator 13 (or Task13 if PtdControl[16]=1) Same bit layout as IPR0 13-16 Description SDMA Initiator Priority 13 Register SDMA Initiator Priority 14 Register SDMA Initiator Priority 15 Register Description MPC5200B Users Guide, Rev. 1 31 lsb IPR11 IPR13 31 lsb IPR15 Freescale Semiconductor...
Page 450: Sdma Initiator Priority 16 Register—Mbar + 0X124C
Initiator Priority register for initiator 19. Same bit layout as IPR0 Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Description SDMA Initiator Priority 17 Register SDMA Initiator Priority 18 Register SDMA Initiator Priority 19 Register Description MPC5200B Users Guide, Rev. 1 IPR17 31 lsb IPR19 13-17...
Page 451: Sdma Initiator Priority 20 Register—Mbar + 0X1250
SDMA Initiator Priority 21 Register SDMA Initiator Priority 22 Register SDMA Initiator Priority 23 Register Description SDMA Initiator Priority 25 Register SDMA Initiator Priority 26 Register SDMA Initiator Priority 27 Register MPC5200B Users Guide, Rev. 1 IPR21 31 lsb IPR23 IPR25 Freescale Semiconductor...
Page 452: Sdma Initiator Priority 28 Register—Mbar + 0X1258
Same bit layout as IPR0 Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Description SDMA Initiator Priority 29 Register SDMA Initiator Priority 30 Register SDMA Initiator Priority 31 Register Description MPC5200B Users Guide, Rev. 1 31 lsb IPR27 IPR29 31 lsb IPR31 13-19...
Page 453: Sdma Requestor Muxcontrol—Mbar + 0X125C
00: Requestor IrDA TX (PSC_6) 01: GPIO_PSC1_2 10: GPIO_ETH_0 11: Always Requestor 26 13-20 Description Table 13-24. SDMA Request MuxControl Req29 Req28 Req27 Req21 Req20 Req19 Description MPC5200B Users Guide, Rev. 1 Req26 Req25 Req24 31 lsb Req18 Req17 Req16 Freescale Semiconductor...
Page 454 01: GPIO_SINT_1 10: GPIO_PSC3_1 11: Always Requestor 17 30:31 Req16 00: Requestor LP 01: GPIO_SINT_0 10: GPIO_PSC3_0 11: Always Requestor 16 The remaining 16 Requestors are fixed as follows: Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Description MPC5200B Users Guide, Rev. 1 13-21...
Page 455: Sdma Task Size0—Mbar + 0X1260
Table 13-25. FIxed REquestors Table Table 13-26. SDMA task Size 0/1 1,5,9,13, 2,6,10,14, 17,21,25,29 18,22,26,30 srcSize[0] dstSize[1] At reset all Bits are set to 0 MPC5200B Users Guide, Rev. 1 Peripheral (RESERVED) PSC1_TX PSC1_RX PSC2_TX PSC2_RX PSC3_TX PSC3_RX PCI TX...
Page 456: Sdma Task 0 & Task Size 1 Map
Table 13-27. SDMA task Size Map Byte 0 Byte 1 Byte 2 TS[0:1] TS[2:3] TS[4:5] TS[8:9] TS[10:11] TS[12:13] Description Table 13-28. SDMA Reserved Register 4 res1 res1 Description MPC5200B Users Guide, Rev. 1 BestComm DMA Registers—MBAR+0x1200 Byte 3 Access TS[5:7] TS[14:15] 31 lsb 13-23...
Page 457: Sdma Reserved Register 2—Mbar + 0X126C
13.15.30 SDMA Debug Module Comparator 2, Value2 Register—MBAR + 0x1274 Table 13-31. SDMA Debug Module Comparator 2, Value2 Register msb 0 RESET: 13-24 Table 13-29. SDMA Reserved Register 2 res2 res2 Description Value1 Value1 Description Value2 MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 458 1 Indicates an AND’ing of the comparators Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Value2 Description Block Tasks and/ EU breakpoints Description Table 13-33 for the bit encoding. Table 13-34 for the bit encoding. MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb 13-25...
Page 459 These bits are cleared to zero at reset. See Table 13-35 for the bit encoding. MPC5200B has integrated only EU3 Enable External Breakpoint. 0 Do not enable external breakpoint to cause a halt condition...
Page 460: Sdma Debug Module Status Register—Mbar + 0X127C
(0). 0 Unblocked or normal operation 1 Blocked, task has been blocked due to a breakpoint Freescale Semiconductor BestComm DMA Registers—MBAR+0x1200 Table 13-35. EU Breakpoint encoding Reserved dbgStatusReg[15:0] Description MPC5200B Users Guide, Rev. 1 31 lsb 13-27...
Page 461: Task Descriptor Table
SRAM at boot. This SRAM resides in the MPC5200B internal register space and is also accessible by the processor core. As such it can be used for other purposes, such as scratch pad storage. The 16kBytes SRAM starts at location MBAR + 0x8000.
Page 462: Integer Mode
Task Descriptor End Pointer Variable Table Pointer Function Descriptor Base Address Reserved Reserved Base Address for Context Save Space Literal Base 1 MPC5200B Users Guide, Rev. 1 Programming Model E P I S Reserved E P I S Reserved 13-29...
Page 463: Integer Mode
Only increment at the end of an iteration Reserved Reserved Do not pack data Pack data Fractional data representation Integer data representation Disabled Enabled Do not enable combined writes Enable combined writes Do not enable line reads Enable line reads MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 464 24 through 31 of Freescale Semiconductor Table 13-38. Variable Table per Task Contents Table 13-38 are preloaded by the processor, as programmed by the user. MPC5200B Users Guide, Rev. 1 Programming Model Comments These twenty-four words (32 bits) are used for constant...
Page 465 Programming Model MPC5200B Users Guide, Rev. 1 13-32 Freescale Semiconductor...
Page 466: Overview
The FEC supports several standard MAC-PHY interfaces to connect to an external Ethernet transceiver. One is the 10/100 Mbps MII (18-wire) interface. Another is the 10-Mbps only 7-Wire interface, which uses a subset of the MII pins. Freescale Semiconductor Table 14-1 shows a block diagram. MPC5200B Users Guide, Rev. 1 Overview 14-1...
Page 467: Block Diagram—Fec
14-2 Interrupt tbus_addr FIFO Controller Tx FIFO (1KByte) Rx FIFO (1KByte) T-bus Transmit Counters TX_EN TX_CLK TXD[3:0] CRS,COL TX_ER MII/7-wire Data Option Figure 14-1. Block Diagram—FEC MPC5200B Users Guide, Rev. 1 IP bus Receive RX_CLK RX_DV RXD[3:0] RX_ER Freescale Semiconductor...
Page 468: Modes Of Operation
Chip Pin tx_en ETH0 tdata[0] ETH1 Freescale Semiconductor NOTE Table 14-1. Signal Properties Function MII—transmit data valid output 7-wire—transmit data valid output MII—transmit data bit 0 output 7-wire—transmit data output MPC5200B Users Guide, Rev. 1 Modes of Operation Reset State 14-3...
Page 469: Detailed Signal Descriptions
MII—Rx data bit 0 input 7-wire—Rx data input MII—Rx data bit 1 input MII—Rx data bit 2 input MII—Rx data bit 3 input MII—Rx error input MII—carrier sense input MPC5200B Users Guide, Rev. 1 Reset State Hi-Z (input) Freescale Semiconductor...
Page 470: Mii Management Frame Structure
0000 through 1111 0000 through 1111 0000 through 1111 0000 0001 through 1101 1110 1111 0000 through 1111 0000 through 1111 MPC5200B Users Guide, Rev. 1 I/O Signal Overview Indication Normal inter-frame Reserved Normal data transmission Transmit error propagation Table 14-3.
Page 471: Mii Management Register Set
Table 14-4. MMI Format Definitions Description Table 14-5. MII Management Register Set Register Name Control Status PHY Identifier Auto-Negotiation Advertisement AN Link Partner Ability AN Expansion AN Next Page Transmit Reserved Vendor Specific MPC5200B Users Guide, Rev. 1 Table 14-5. Basic/Extended Freescale Semiconductor...
Page 472: Control And Status (Csr) Memory Map
Upper 32 bits of individual Hash Table Lower 32 bits of individual Hash Table Upper 32 bits of Group Hash Table Lower 32 bits of Group Hash Table Reserved MPC5200B Users Guide, Rev. 1 FEC Memory Map and Registers Name 14-7...
Page 473: Mib Block Counters Memory Map
Transmit FIFO Status Transmit FIFO Control Transmit FIFO Last Read Frame Pointer Transmit FIFO Last Write Frame Pointer Transmit FIFO Alarm Pointer Transmit FIFO Read Pointer Transmit FIFO Write Pointer Reset Control Transmit FSM MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 474 Flow Control Pause Frames Transmitted Octet Count for Frames Transmitted w/o Error Reserved Count of frames Not Counted Correctly RMON Rx Packet Count RMON Rx Broadcast Packets RMON Rx Multicast Packets MPC5200B Users Guide, Rev. 1 FEC Memory Map and Registers 14-9...
Page 475: Fec Registers—Mbar + 0X3000
Count of frames not counted correctly Frames received OK Frames received with CRC error Frames received with alignment error Rx FIFO overflow count Flow Control Pause frames received Octet count for frames received without error Reserved Reserved MPC5200B Users Guide, Rev. 1 Description Freescale Semiconductor...
Page 476: Fec Id Register—Mbar + 0X3000
(0x31C0) • Section 14-38, FEC Reset Control Register • Section 14-39, FEC Transmit FSM Register Table 14-9. FEC ID Register FEC_ID DMA FIFO Rsvd MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 (0x31A4) (0x31A8) (0x31AC) (0x3190) (0x3194) (0x31C4) (0x31C8)
Page 477: Fec Interrupt Event Register—Mbar + 0X3004
BABT – RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC) • LATE_COL – IEEE_T_LCOL • COL_RETRY_LIM – IEEE_T_EXCOL • XFIFO_UN – IEEE_T_MACERR Table 14-10. FEC Interrupt Event Register msb 0 RESET: RESET: 14-12 Description Reserved Rsvd MPC5200B Users Guide, Rev. 1 Rsvd 31 lsb Freescale Semiconductor...
Page 478 3 = A graceful stop initiated by reception of a valid full duplex flow control “pause” frame is complete. Refer to “Full-Duplex Flow Control” section of the Ethernet Operation chapter. MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 14-13...
Page 479: Fec Interrupt Enable Register—Mbar + 0X3008
FEC will clear the R_DES_ACTIVE bit and cease receive descriptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the receive descriptor ring. 14-14 Reserved Rsvd Reserved Description MPC5200B Users Guide, Rev. 1 Rsvd 31 lsb Freescale Semiconductor...
Page 480: Fec Tx Descriptor Active Register—Mbar + 0X3014
The X_DES_ACTIVE bit is cleared at reset and by the clearing of ETHER_EN. Table 14-13. FEC Tx Descriptor Active Register msb 0 Reserved RESET: RESET: Freescale Semiconductor Reserved Description Reserved MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 Reserved 31 lsb Reserved 31 lsb 14-15...
Page 481: Fec Ethernet Control Register—Mbar + 0X3024
Also, any Tx/Rx currently in progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately 8 clock cycles after RESET is written with 1. 14-16 Description Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 482: Fec Mii Management Frame Register—Mbar + 0X3040
Writing this pattern causes control logic to shift out the data in the MII_DATA register following a preamble generated by the control state machine. During this time, the MII_DATA register contents are altered as the contents are serially shifted, and is unpredictable if read by the Freescale Semiconductor DATA Description MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 31 lsb 14-17...
Page 483: Fec Mii Speed Control Register—Mbar + 0X3044
(intended for manufacturing test) of an internal counter used in generating an MDC clock signal. Table 14-16. FEC MII Speed Control Register msb 0 RESET: Reserved RESET: 0 14-18 Reserved MII_SPEED MPC5200B Users Guide, Rev. 1 31 lsb Rsvd Freescale Semiconductor...
Page 484: Fec Mib Control Register—Mbar + 0X3064
Reserved RESET: 1 RESET: Freescale Semiconductor Description Table 14-17 MII_SPEED (Field in Register) Table 14-18. FEC MIB Control Register Reserved MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 shows MII_SPEED optimum MDC Frequency 2.5MHz 2.36MHz 2.5MHz 2.5MHz 31 lsb...
Page 485: Fec Receive Control Register—Mbar + 0X3084
Selects External Interface Mode—controls the interface mode for Tx/Rx blocks. • Setting bit to 1 selects MII mode. • Setting bit to 0 selects 7wire mode (used only for serial 10Mbps). 14-20 Description MAX_FL Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb LOOP Freescale Semiconductor...
Page 486: Fec Hash Register—Mbar + 0X3088
ETHER_EN = 0. msb 0 RESET: Freescale Semiconductor Description Table 14-20. FEC Hash Register HASH Reserved Description Table 14-21. FEC Tx Control Register Reserved MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 Reserved 31 lsb 14-21...
Page 487: Fec Physical Address Low Register—Mbar + 0X30E4
Bytes0:3 of the 6-Byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized. Table 14-22. FEC Physical Address Low Register msb 0 RESET: 14-22 Description PADDR1 MPC5200B Users Guide, Rev. 1 31 lsb FDEN HBC Freescale Semiconductor...
Page 488: Fec Physical Address High Register—Mbar + 0X30E8
This register is not reset and bits 16:31 must be initialized. Table 14-24. FEC Opcode/Pause Duration Register msb 0 RESET: Freescale Semiconductor PADDR1 Description PADDR2 TYPE Description OPCODE MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 31 lsb 31 lsb 14-23...
Page 489: Fec Descriptor Individual Address 2 Register—Mbar + 0X311C
DA field of receive frames with an individual DA. This register is not reset and must be initialized. Table 14-26. FEC Descriptor Individual Address 2 Register msb 0 RESET: 14-24 PAUSE_DUR Description IADDR1 IADDR1 Description IADDR2 MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 490: Fec Descriptor Group Address 1 Register—Mbar + 0X
This register must be initialized. Table 14-28. FEC Descriptor Group Address 2 Register msb 0 RESET: Freescale Semiconductor IADDR2 Description GADDR1 GADDR1 Description GADDR2 MPC5200B Users Guide, Rev. 1 FEC Registers—MBAR + 0x3000 31 lsb 31 lsb 14-25...
Page 491: Fec Tx Fifo Watermark Register—Mbar + 0X3144
This register value may need to be customized by software for specific FEC applications to be compatible with specific FIFO/system bus access latency requirements. Table 14-29. FEC Tx FIFO Watermark Register msb 0 RESET: RESET: 14-26 GADDR2 Description NOTE Reserved Reserved MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb X_WMRK Freescale Semiconductor...
Page 492: Fifo Interface
Receive (High/Low) Alarm Pointer Read Read Receive FIFO Read Pointer Write Write Receive FIFO Write Pointer Data Data Data Transmit FIFO Data Stat Transmit FIFO Status Transmit FIFO Control Transmit Last Read Frame Pointer MPC5200B Users Guide, Rev. 1 FIFO Interface Description 14-27...
Page 493: Fec Rx Fifo Data Register—Mbar + 0X3184
Transmit Last Write Frame Pointer Alarm Alarm Transmit (High/Low) Alarm Pointer Read Read Transmit FIFO Read Pointer Write Write Transmit FIFO Write Pointer FEC Tx FIFO Status Register Frame[0:3] Reserved Description MPC5200B Users Guide, Rev. 1 Description Full Alarm Empty 31 lsb Freescale Semiconductor...
Page 494: Fec Rx Fifo Control Register—Mbar + 0X318C
Ethernet has reported completion of transmission. Frame mode supersedes the FIFO granularity bits, through the assertion of a hardware signal to BestComm. Freescale Semiconductor FEC Tx FIFO Status Register—MBAR + 0x31A8 Description MPC5200B Users Guide, Rev. 1 14-29...
Page 495: Fec Rx Fifo Last Read Frame Pointer Register—Mbar + 0X3190
Table 14-33. FEC Rx FIFO Last Read Frame Pointer Register msb 0 RESET: 14-30 FEC Tx FIFO Control Register GR[2:0] MASK MASK Reserved Description FEC Tx FIFO Last Read Frame Pointer Register Reserved MPC5200B Users Guide, Rev. 1 Reserved MASK MASK 31 lsb Freescale Semiconductor...
Page 496: Fec Rx Fifo Last Write Frame Pointer Register—Mbar + 0X3194
FIFO memory, and the alarm pointer is initialized to zero. Freescale Semiconductor FEC Tx FIFO Status Register—MBAR + 0x31A8 Description FEC Tx FIFO Last Write Frame Pointer Register Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb LRFP[9:0] 31 lsb LRFP[9:0] 14-31...
Page 497: Fec Rx Fifo Read Pointer Register—Mbar + 0X319C
This pointer indicates the next location to be read by the FIFO controller. 14-32 FEC Tx FIFO Alarm Pointer Register Reserved Description FEC Tx FIFO Read Pointer Register Reserved Description MPC5200B Users Guide, Rev. 1 31 lsb Alarm[9:0] 31 lsb READ[9:0] Freescale Semiconductor...
Page 498: Fec Rx Fifo Write Pointer Register—Mbar + 0X31A0
1 = Reset FIFO controllers. Freescale Semiconductor FEC Tx FIFO Status Register—MBAR + 0x31A8 FEC Tx FIFO Write Pointer Register Reserved Description Table 14-38. FEC Reset Control Register Reserved Table 1-1. Description MPC5200B Users Guide, Rev. 1 31 lsb WRITE[9:0] Reserved 31 lsb 14-33...
Page 499: Fec Transmit Fsm Register—Mbar + 0X31C8
Tx/Rx FIFO 14-34 Table 1-1. Description Table 14-39. FEC Transmit FSM Register Reserved Description Transmission Aborted (bad CRC appended) Reset control logic dependent on reset_cntrl MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reset Value Receive activity aborted Freescale Semiconductor...
Page 500: User Initialization (Prior To Asserting Ether_En)
X_WMRK (optional) IADDR2/IADDR1 GADDR1/GADDR2 PADDR1/PADDR2 OP_PAUSE (only needed for FDX flow control) R_CNTRL X_CNTRL MII_SPEED (optional) Clear MIB_RAM (locations 200–2FC) Description Initialize BackOff random number seed Activate Receiver Activate Transmit FRAME_LENGTH MPC5200B Users Guide, Rev. 1 Initialization Sequence Table 14-41. 14-35...
Page 501: Transmit Frame Control Word
CRC (TC = 1) or not (TC = 0) for the current frame. The ABC bit defines whether the transmit block should append a bad CRC (ABC = 1), independent of the TC value. Refer to Table 14-44 Table 14-44. Transmit Frame Control Word Format 14-36 Description below for the format of the transmit frame control word. MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 502: Network Interface Options
1 = Transmit the CRC sequence after the last data byte. 0 = No affect 1 = Transmit the CRC sequence inverted after the last data bye (regardless of TC value). Table 14-1: MPC5200B Users Guide, Rev. 1 Initialization Sequence 14-37...
Page 503: Ethernet Address Recognition
MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected and the MISS bit will be cleared. In general, when a frame is rejected it is flushed from the FIFO. MPC5200B Users Guide, Rev. 1 14-38 Freescale Semiconductor...
Page 504: Ethernet Address Recognition - Receive Block Decisions
AR_HM_B - bit in RECV.AR_DONE register (address recognition hash match bar) PROM - field in R_CNTRL register (PROMiscous mode) Pause Frame - valid PAUSE frame received Figure 14-2. Ethernet Address Recognition - receive block decisions MPC5200B Users Guide, Rev. 1 Freescale Semiconductor 14-39...
Page 505: Ethernet Address Recognition - Microcode Decisions
Individual Table ar_em_b = 0 ar_hm_b = 1 True ar_em_b = 1 ar_em_b = 1 ar_hm_b = 1 ar_hm_b = 0 MPC5200B Users Guide, Rev. 1 False True Exact Match ar_em_b = 0 ar_hm_b = 1 Match False Freescale Semiconductor...
Page 506 19:ff:ff:ff:ff:ff d1:ff:ff:ff:ff:ff f1:ff:ff:ff:ff:ff b1:ff:ff:ff:ff:ff Freescale Semiconductor 6-bit hash (in hex) hash decimal value 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 MPC5200B Users Guide, Rev. 1 Initialization Sequence 14-41...
Page 507: Full-Duplex Flow Control
6-bit hash (in hex) hash decimal value 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 508: Inter-Packet Gap Time
Freescale Semiconductor 0180_c200_0001 or Physical ADDRESS 8808 0001 0000 to ffff FEC register {FDXFC_DA1[0:31], FDXFC_DA2[0:15]} {PADDR1[0:31], PADDR2[0:15]} PADDR2[16:31] OP_PAUSE[0:15] OP_PAUSE[16:31] MPC5200B Users Guide, Rev. 1 Initialization Sequence Register Contents 0180_c200_0001 physical address 8808 0001 0000 to ffff 14-43...
Page 509: Internal And External Loopback
FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO with the OV bit isset. This frame must be discarded by the driver. 14-44 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 510 Receive Frame Status Word will be set. The frame is not truncated (truncation occurs if the frame length exceeds 2047 bytes). Truncation — When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is set in the receive BD. Freescale Semiconductor MPC5200B Users Guide, Rev. 1 Initialization Sequence 14-45...
Page 511 Fast Ethernet Controller (FEC) Notes MPC5200B Users Guide, Rev. 1 14-46 Freescale Semiconductor...
Page 512 PSC supports which mode. Table 15-1. PSC Mode Overview PSC2 PSC3 slave slave Figure 15-2 Section 15.3.2, PSC in Codec Mode MPC5200B Users Guide, Rev. 1 Overview PSC4 PSC5 PSC6 slave shows a simplified PSC block diagram. In 15-1...
Page 513: Psc Functions Overview
15-2 Internal Channel Interrupt Control Logic Control Logic Serial FIFO System Communications Channel Programmable Tx/Rx Clock Generation AC97 UART Figure 15-1. PSC Functions Overview MPC5200B Users Guide, Rev. 1 Control lines External Clock Source Figure 15-1.shows the IrDA Freescale Semiconductor...
Page 514 Support “digital cell phone” interface AC97 mode: • PSC1 and PSC2 support an AC97 interface IrDA SIR mode: • Baud rate: 2400 to 115200 bps Freescale Semiconductor Section 15.3.3, PSC in AC97 Mode MPC5200B Users Guide, Rev. 1 Overview 15-3...
Page 515: Status Register (0X04) — Sr
Output Port 1 Bit Set (0x38)—OP1 Output Port 0 Bit Set (0x3C)—OP0 Serial Interface Control Register (0x40)—SICR 15-4 Table 15-2. PSC Memory Map Register Name - Reserved MPC5200B Users Guide, Rev. 1 Table 15-2 shows Register Access width Freescale Semiconductor...
Page 516: Infrared Sir Divide Register (0X4C)—Irsdr
0 RxRTS RxIRQ/FFUL RESET: Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Table 15-2. PSC Memory Map (continued) - Reserved - Reserved - Reserved - Reserved — Reserved MPC5200B Users Guide, Rev. 1 7 lsb 15-5...
Page 517 Parity Mode With parity 15-6 Reserved Reserved Description Table 15-6. PM is not used in Codec mode. Parity Type (PT=0) Even parity MPC5200B Users Guide, Rev. 1 7 lsb 7 lsb Table 15-6. Parity Type (PT=1) Odd parity Freescale Semiconductor...
Page 518 Modes—Reserved Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Low parity Data character — TxRTS TxCTS Reserved Description MPC5200B Users Guide, Rev. 1 High parity Address character 7 lsb 7 lsb 15-7...
Page 519 1000 0101 1.375 0.875 1001 0110 1.438 0.938 1010 0111 1.500 1.000 1011 — Error Error MPC5200B Users Guide, Rev. 1 5–8 Bits 5–8 Bits 1.563 1100 1.813 1.625 1101 1.875 1.688 1110 1.938 1.750 1111 2.000 15 lsb Reserved...
Page 520 1 = If MR1[PM]=0x (with parity or force parity), corresponding FIFO character was received with incorrect parity. If MR1[PM]=11 (multidrop), PE stores received A/D bit.\ other Modes—Reserved Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Error Error Description MPC5200B Users Guide, Rev. 1 15 lsb Reserved 15 lsb Reserved 15-9...
Page 521 [TC]. TFALARM value, due to data transfer from the Tx FIFO RFALARM value, due to the transfer of data from the Rx RFCNTL MPC5200B Users Guide, Rev. 1 RESET ERROR TFALARM register value, or the TFCNTL register. In UART mode register.
Page 522 A write access to the AC97Data register. A read access to the NOTE TFSTAT register will be set, but the status bit in the SR register are MPC5200B Users Guide, Rev. 1 command. TFSTAT AC97CMD AC97Data AC97Data...
Page 523 Clock Select Register (0x04) The MPC5200B supports only the internal clock as source for the UART / SIR clock generation. For the UART clock generation a prescaler by 32 or 4 is available. For the SIR clock generation only the prescaler by 32 is valid. After reset, the prescaler by 4 for the UART mode and the prescaler by 32 for the SIR mode is selected.
Page 524 Tx holding register is sent after the break. Tx must be enabled for command to be accepted. This command ignores the CTS state and has no effect in Codec mode. Causes TxD to go high (mark) within two bit-times. Any characters in the Tx buffer are sent. MPC5200B Users Guide, Rev. 1 7 lsb 15-13...
Page 525 • If the receiver is already disabled, the command has no effect. In Codec mode, if the receiver is disabled while a character is being received, reception completes before the receiver becomes inactive. Reserved, do not use. MPC5200B Users Guide, Rev. 1 become asserted. Freescale Semiconductor...
Page 526 Used by Tx Buffer RB[16:31] Used by Tx Buffer RB[0:15] Used by Tx Buffer Reserved Used by Tx Buffer RB[0:15] Used by Tx Buffer Used by Tx Buffer MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb 31 lsb Reserved 15-15...
Page 527 0 RESET: TB[16:19] RESET: 15-16 Description — NOTE Used by Rx Buffer TB[0:15] Used by Rx Buffer TB[16:31] Used by Rx Buffer TB[0:15] Used by Rx Buffer Reserved MPC5200B Users Guide, Rev. 1 31 lsb 31 lsb Freescale Semiconductor...
Page 528 PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Used by Rx Buffer TB[0:15] Used by Rx Buffer Description IPCR — D_DCD D_CTS Reserved Reserved D_DCD D_CTS Reserved Reserved MPC5200B Users Guide, Rev. 1 31 lsb Reserved 7 lsb 7 lsb 15-17...
Page 529 CTLR) has occurred at DCD input. When this bit is set, the ACR can be also clears the IPCR D_CTS bit. can be programmed to generate an interrupt to the processor. — Reserved Reserved Description MPC5200B Users Guide, Rev. 1 7 lsb IEC1 IEC0 Freescale Semiconductor...
Page 530 Error Error Description register. To clear this interrupt use the reset register. MPC5200B Users Guide, Rev. 1 sets (causing an interrupt if mask sets (causing an interrupt if mask 15 lsb Reserved 15 lsb...
Page 531 To clear this interrupt use the register. register. — that cause an interrupt. bit has no effect on the interrupt output. The IMR does not mask reading MPC5200B Users Guide, Rev. 1 register. register. register. To clear this interrupt use Freescale Semiconductor...
Page 532 0 = TxRDY has no effect on the interrupt. 1 = Enable the interrupt for TxRDY Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Reserved Error Reserved Error Reserved Description MPC5200B Users Guide, Rev. 1 15 lsb Reserved 15 lsb 15-21...
Page 533 CTUR — Reserved CTUR[0:7] Description Section 15.2.13, Counter Timer Lower Register (0x1C)—CTLR MPC5200B Users Guide, Rev. 1 Section 15.2.13, Counter Timer 7 lsb Freescale Semiconductor...
Page 534 IPB clock frequency where: CT[0:15] = {CTUR[0:7], CTLR[0:7]} CT[0:15] x “prescaler” register. where: IPB clock frequency CT[0:15] x 32 CT[0:15] = {CTUR[0:7], CTLR[0:7]} CT[0:15] + 2 Mclk frequency IPB clock frequency MPC5200B Users Guide, Rev. 1 7 lsb 15 lsb 15-23...
Page 535 Table 15-33. Codec Clock Register (0x20)—CCR for MIR/FIR Mode Reserved RESET: BitClkDiv[0:7] RESET: Table 15-34. Codec Clock Register (0x20)—CCR for other Modes RESET: RESET: 15-24 Reserved Reserved MPC5200B Users Guide, Rev. 1 BitClkDiv[8:15] 31 lsb Reserved 15 lsb BitClkDiv[8:15] 31 lsb Reserved 15 lsb 31 lsb Freescale Semiconductor...
Page 536 BitClkDiv[0:15] + 1 Mclk Frequency SCK frequency = BitClkDiv[0:15] + 1 Mclk Frequency BitClkDiv[0:15] + 1 system Mclk = MclkDiv [8:0] + 1 Section 5.5.11, PSC1 Mclock Config Register—MBAR + MPC5200B Users Guide, Rev. 1 frequency as follows: system 15-25...
Page 537 If the data was send, then the SR[CMD_SEND] bit will be cleared by the transmitter. Table 15-36. AC97 Command Register (0x28)—AC97CMD AC97 Control Register Index RESET: AC97 Command Data[7:0] RESET: 15-26 Reserved TX_Slots[3:12] Reserved RX_Slots[3:12] Description AC97 Command Data[15:8] MPC5200B Users Guide, Rev. 1 15 lsb 15 lsb Reserved Freescale Semiconductor...
Page 538 This register is not used since the MPC5200 does not use interrupt vectors supplied by the peripherals. Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description AC97 Control Register Read Data[15:8] erved erved Description MPC5200B Users Guide, Rev. 1 15 lsb Reserved 15-27...
Page 539 1 = Usual operation. other Modes—Reserved AC97 / Codec—Test usage. Toggle by FrameSync. other Modes—Reserved — Reserved 15-28 IVR[0:7] Description — Reserved Reserved Reserved Reserved Reserved Reserved Description MPC5200B Users Guide, Rev. 1 7 lsb 7 lsb 7 lsb 7 lsb Freescale Semiconductor...
Page 540 Table 15-43. Output Port 0 Bit Set Register (0x3C) for all Modes msb 0 RESET: Name — Reserved Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description — Reserved Reserved Description — Reserved Reserved Description MPC5200B Users Guide, Rev. 1 7 lsb 7 lsb 15-29...
Page 541 1 = first bit of first time slot of a new frame starts one bit clock cycle after the rising edge of FrameSync. other Modes—Reserved 15-30 Description SICR — DTS1 SHDIR ClkPol SyncPol CellSlave Cell2xClk CPOL CPHA UseEOF Disable_EOF Description MPC5200B Users Guide, Rev. 1 SIM[3:0] ESAI EnAC97 23 lsb Reserved registers to Freescale Semiconductor...
Page 542: Psc Operation Modes
Codec—Cell Phone Slave 0 = PSC is not a slave to PSC1 1 = PSC uses Bit Clock from PSC1 master as its Mclk Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description MPC5200B Users Guide, Rev. 1 15-31...
Page 543 Codec8, Codec16, Codec24 or Codec32 being selected by SICR[SIM] 1 = multiple bytes are transferred while maintaining SS low, up to and including the next byte read from the Tx FIFO that has its EOF flag set other modes—Reserved 15-32 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 544 This register controls the configuration in one of the IrDA modes (SIR/MIR/FIR). Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description Reserved Description IRCR2 Figure 15-20. MPC5200B Users Guide, Rev. 1 7 lsb Reserved SPUL 7 lsb SIPEN Reserved becomes high.
Page 545 This register set the SIR pulse width. To set the SIR mode Baud rate see register is reserved in other modes. 15-34 Reserved Reserved Description Section 15.2.12, Counter Timer Upper Register MPC5200B Users Guide, Rev. 1 7 lsb SIPREQ ABORT NXTEOF 7 lsb Figure 15-20.
Page 546 Table 15-52. Infrared MIR Divide Register (0x50) for other Modes msb 0 RESET Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 IRSTIM[0:7] Reserved Description M_FDIV Reserved MPC5200B Users Guide, Rev. 1 7 lsb 7 lsb IRCR1 is high. This value 7 lsb 7 lsb 15-35...
Page 547 Frequency of IrdaClk [MHz] 1.152 Mbps 0.576 Mbps 9.216 4.6080 13.824 6.912 18.432 9.216 23.040 11.520 27.648 13.824 147.456 73.728 Reserved MPC5200B Users Guide, Rev. 1 Section 15.3.4.2, PSC in MIR 7 lsb F_FDIV 7 lsb Freescale Semiconductor...
Page 548 PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description f IrdaClk f bit ----------------------------- - F_FDIV + 1 Frequency of IrdaClk [MHz] 32.0 40.0 48.0 56.0 64.0 72.0 80.0 88.0 MPC5200B Users Guide, Rev. 1 Table 15-56 shows several Figure Section 15.3.4.3, PSC in FIR Mode. 15-37...
Page 549 — Section 15.2.3, Status Register (0x04) — SR. NOTE register reports these errors. Table 15-59. Rx FIFO Status (0x64) Rese Error rved MPC5200B Users Guide, Rev. 1 15 lsb COUNT[0:8] Reserved 15 lsb COUNT[0:8] Reserved Section 15.2.6, Rx Buffer 15 lsb...
Page 550 Table 15-60. Rx FIFO Control (0x68) COMP FRAME Description Section 15.4, PSC FIFO System Table 15-61. Rx FIFO Alarm (0x6E) ALARM MPC5200B Users Guide, Rev. 1 Section 15.2.33, Rx 7 lsb GR[2:0] for details. 15 lsb 15-39...
Page 551 15-40 Description Table 15-62. Rx FIFO Read Pointer (0x72) Description Table 15-63. Rx FIFO Write Pointer (0x76) Description Description MPC5200B Users Guide, Rev. 1 Section 15.4, PSC FIFO System for details. 15 lsb R_PTR 15 lsb W_PTR 15 lsb...
Page 552 PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description Section 15.2.3, Status Register (0x04) — SR. NOTE register reports these errors. Table 15-66. Tx FIFO STAT (0x84) Rese Error rved Description MPC5200B Users Guide, Rev. 1 15 lsb Section 15.2.7, 15 lsb FULL 15-41...
Page 553 Description Table 15-68. Tx FIFO Alarm (0x8E) ALARM Description Section 15.4, PSC FIFO System Table 15-69. Tx FIFO Read Pointer (0x92) MPC5200B Users Guide, Rev. 1 Section 15.4, PSC FIFO 7 lsb GR[2:0] Section 15.4, PSC FIFO 15 lsb for details...
Page 554 Freescale Semiconductor PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00 Description Table 15-70. Tx FIFO Write Pointer (0x96) W_PTR Description Description Description MPC5200B Users Guide, Rev. 1 15 lsb 15 lsb 15 lsb 15-43...
Page 555: Psc In Uart Mode
Section 5.5.14, PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234. system Mclk MclkDiv[8:0] +1 Intellectual Property Clock for the internal IP bus system, 33, 66 or 132 MHz, Section 5.5, CDM Registers Chapter 2, Signal Descriptions MPC5200B Users Guide, Rev. 1 PSC5 PSC6 slave Freescale Semiconductor...
Page 556 Data carrier detect Input — In the enhanced UART mode this signal must be assert during the data transmission. Freescale Semiconductor Port Clock Control Generation Unit Logic {CTUR:CTLR} Receiver Rx FIFO Transmitter Tx FIFO NOTE Description MPC5200B Users Guide, Rev. 1 PSC Operation Modes External Interface Signals 15-45...
Page 557: Uart Clock Generation
15-3. Using a 66 MHz IPB clock and the 32 prescaler, the Baud-rate IPB Clock 32 x divider {CTUR:CTLR} 66 MHz = 215(decimal) = 0x00D7 32 x 9600 16-Bit Divider {CTUR:CTLR} Figure 15-3. Clocking Source Diagram MPC5200B Users Guide, Rev. 1 Prescaler 32 or 4 Clock Freescale Semiconductor...
Page 558 After a hardware reset, all PSCs are in UART mode. The receiver is enabled through its CR, as described in (0x08)—CR. Figure 15-5 shows the receiver functional timing. Freescale Semiconductor C1 in transmission Break Start break MPC5200B Users Guide, Rev. 1 PSC Operation Modes C4 Stop break transmitted Manually asserted Section 15.2.5, Command Register 15-47...
Page 559: Configuration Sequence For Uart Mode
FIFO configurations. PSC module registers can be accessed by word or byte operations. 15-48 C5 is lost Automatically deasserted when FIFO reached the alarm level Figure 15-5. Timing Diagram—Receiver MPC5200B Users Guide, Rev. 1 C6, C7, and C8 are lost Status Status Status Data Data Data...
Page 560: Psc In Codec Mode
MISO MISO MOSI Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228 Section 5.5.6, CDM Clock Enable Register—MBAR + 0x0214 Chapter 2, Signal Descriptions MPC5200B Users Guide, Rev. 1 PSC Operation Modes Chapter 2, Signal SICR Figure 15-6 shows a FrameSync...
Page 561: Block Diagram And Signal Definition For Codec Mode
Generation Unit BitClkDiv[0:15]+1 Rx FIFO Transmitter Tx FIFO Figure 15-6. PSC Codec Block Diagram NOTE external Codec device FRAME SSYNC0 SCLK0 SRx0 STx0 MPC5200B Users Guide, Rev. 1 Mclk BitClk Frame External Interface Signals Receiver Section 5.5.5, 0x0210. Freescale Semiconductor...
Page 562 PSC generate the clocks. system Mclk divider MclkDiv[8:0] + 1 Figure 15-8. Clock Generation Diagram for Codec Mode Freescale Semiconductor Description BitClk divider Frame divider CCR[8:23] CCR[0:7] CTUR[0:7] MPC5200B Users Guide, Rev. 1 PSC Operation Modes Mclk BitClk Frame 15-51...
Page 563 CCR[8:15] +1 BitClk CCR[0:7] +1 register must be set to one. But it’s not possible to use the transmitter without the receiver. To Generation. MPC5200B Users Guide, Rev. 1 clock see also Section 5.5.11, PSC1 Mclock Config clock as system register.
Page 564 RFALARM level to 0x00C set the TFALARM level to 0x010 enable TxRDY interrupt Select the Pin-Muxing for PSC1 Codec mode, see Enable Tx and Rx MPC5200B Users Guide, Rev. 1 PSC Operation Modes start of next Frame Chapter 2, Signal Descriptions 15-53...
Page 565 Chapter 2, Signal Descriptions 0x05 Enable Tx and Rx The different is, that the ESAI protocol allow to transmit and receive more than Figure 15-10 shows the ESAI transmission MPC5200B Users Guide, Rev. 1 Setting Section 15.3.2.3, diagram. Freescale Semiconductor...
Page 566 TFALARM level to 0x010 0x0100 enable TxRDY interrupt Select the Pin-Muxing for PSC1 Codec mode, see Descriptions 0x05 Enable Tx and Rx MPC5200B Users Guide, Rev. 1 PSC Operation Modes empty Data until the next frame starts Setting Chapter 2, Signal...
Page 567 SICR[CellSlave] = 1, use clock from PSC1 (normal or double clock) SICR[Cell2xClk] = 0, use normal clock SICR[Cell2xClk] = 1, use double clock MPC5200B Users Guide, Rev. 1 Section 15.3.2.2, Codec Clock and FrameSync Figure 15-11 — receive BitClk and Frame, —...
Page 568 TxRDY interrupt Select the Pin-Muxing for PSC12, PSC2 Codec mode, see Descriptions Enable Tx and Rx Figure 15-12 MPC5200B Users Guide, Rev. 1 PSC Operation Modes Chapter 2, Signal Chapter 2, Signal The different is, that during the I2S word shows the I2S transmission diagram.
Page 569 RFALARM level to 0x00C 0x0010 set the TFALARM level to 0x010 0x0100 enable TxRDY interrupt Select the Pin-Muxing for PSC1 Codec mode, see Descriptions 0x05 Enable Tx and Rx MPC5200B Users Guide, Rev. 1 start of Frame Setting Chapter 2, Signal Freescale Semiconductor...
Page 570 CCR register. CCR[0:7] +1 DSCKL delay = Mclk CT[0:15] +2 Mclk frequency where: CT[0:15] = {CTUR[0:7], CTLR[0:7]} MPC5200B Users Guide, Rev. 1 PSC Operation Modes register to take effect. In SPI mode, the SICR[SIM] Section 15.3.2.2, Codec Clock and 15-59...
Page 571 SCK and DSCKL delay 0x00 set the DTL delay 2us 0x84 0x000C set the RFALARM level to 0x00C 0x0010 set the TFALARM level to 0x010 0x0100 enable TxRDY interrupt MPC5200B Users Guide, Rev. 1 NEXT FRAME Setting Freescale Semiconductor...
Page 572: Psc In Ac97 Mode
Select the Pin-Muxing for PSC2 Codec mode, see Enable Tx and Rx Section 15.3.3.5, Transmitting and Receiving in “Enhanced” AC97 Mode. Chapter 2, Signal Descriptions MPC5200B Users Guide, Rev. 1 PSC Operation Modes Setting Chapter 2, Signal Chapter 2, Signal Descriptions...
Page 573: Block Diagram And Signal Definition For Ac97 Mode
Reset signal to the external AC97 device 15-62 BitClk Clock Generation Sync Unit Receiver Rx FIFO Transmitter Tx FIFO Reset Logic Figure 15-14. PSC AC97 Block Diagram Description MPC5200B Users Guide, Rev. 1 Sdata_in External Interface Signals Sdata_out Freescale Semiconductor...
Page 574: Ac97 Low-Power Mode
Slot 2 Slot 3 bit13 bit14 bit15 bit16 bits Slot 2 Slot 3 Frame NOTE MPC5200B Users Guide, Rev. 1 PSC Operation Modes Frame Sync bits bits Slot 13 Slot 1 bits bits Slot 13 Slot 1 15-63...
Page 575 Select the Pin-Muxing for AC97 mode PSC2, see Enable Tx and Rx are used. In this mode, only the used data slots (3 to 12) are in the FIFOs. MPC5200B Users Guide, Rev. 1 Mode.Therefore all data slots Chapter 2, Signal Descriptions Mode.
Page 576: Psc In Sir Mode
Choose Tx FIFO “almost empty” threshold level. select the desired interrupt Select the Pin-Muxing for AC97 mode PSC2, see Enable Tx and Rx Chapter 2, Signal Descriptions MPC5200B Users Guide, Rev. 1 PSC Operation Modes Table 15-89 Chapter 2, Signal Descriptions Figure 15-17.
Page 577: Transmitting And Receiving In Sir Mode
Figure 15-17. PSC SIR Block Diagram data bits(8 bit) 3/16 of the bit width or 1.6 µs Figure 15-18. Data Format in SIR Mode NOTE Section 15.2.25, Infrared SIR Divide Register (0x4C)—IRSDR MPC5200B Users Guide, Rev. 1 IRDA_RX External Interface Signals IRDA_TX stop...
Page 578: Configuration Sequence Example For Sir Mode
Enable Tx and Rx Section 5.5.14, PSC6 (IrDA) Mclock Config Register—MBAR + 0x0234 Section 5.5.6, CDM Clock Enable Register—MBAR + 0x0214 Chapter 2, Signal Descriptions Table 15-90. MPC5200B Users Guide, Rev. 1 PSC Operation Modes Section 15.3.4.1, PSC in SIR Mode 15-67...
Page 579: Transmitting And Receiving In Mir Mode
0x0228. If the bit GenClk cleared then the PSC use the clock from an external source NOTE character FE This zero was insert after five consecutive ones! DATA DATA MPC5200B Users Guide, Rev. 1 IR_USB_CLK IRDA_RX Receiver External Interface Signals IRDA_TX Section 15.2.27,...
Page 580: Serial Interaction Pulse (Sip)
SIP 0x07 set Baud rate to 1.152 Mbps 0x0XXX Choose Rx FIFO “almost full” threshold level. 0x0XXX Choose Tx FIFO “almost empty” threshold level. MPC5200B Users Guide, Rev. 1 PSC Operation Modes Setting Section 5.5.11, PSC1 Mclock Config 15-69...
Page 581: Psc In Fir Mode
Figure 15-19. Section 15.3.4.2.1, Block Diagram and Signal Definition for MIR Mode. Figure 15-21. Data Format in FIR Mode DATA MPC5200B Users Guide, Rev. 1 Setting Chapter 2, Signal shows the Block diagram for FIR mode. bit pair 4PPM data...
Page 582: Configuration Sequence Example For Fir Mode
Choose Tx FIFO “almost empty” threshold level. 0xXXXX select the desired interrupt 0x00F00000 Select the Pin-Muxing for IrDA mode, see Descriptions 0x05 Enable Tx and Rx MPC5200B Users Guide, Rev. 1 PSC FIFO System 0110 0000 0000 0110 last chip Setting Section 5.5.14, PSC6 (IrDA) Mclock...
Page 583 NOTE control, all receiver status bits, and interrupt requests are reset. No more MPC5200B Users Guide, Rev. 1 shows a logical OR of all characters received . In which case, the receiver automatically when a FIFO position becomes available.
Page 584 Interface Address: first received Byte last received Byte empty FIFO Space Receiver Rx Line Figure 15-22. PSC FIFO System NOTE MPC5200B Users Guide, Rev. 1 PSC FIFO System Granularity Level (example: 0x004) Alarm Level “almost Full” (example: 0x008) Figure 15-22.
Page 585: Looping Modes
PSC module channel by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations. 15-74 Figure 15-22. The “Granularity” value range is 0–7. Figure 15-23. These modes are useful for local and remote 0x2C00. Disabled Figure 15-23. Automatic Echo MPC5200B Users Guide, Rev. 1 Section 15.2, RxD Input TxD Input Freescale Semiconductor...
Page 586: Remote Loop-Back Mode
Figure 15-24. Local Loop-Back 15-25, the channel automatically transmits received data bit-by-bit on the TxD output. The local Disabled Disabled Figure 15-25. Remote Loop-Back MPC5200B Users Guide, Rev. 1 PSC FIFO System RxD Input TxD Input RxD Input TxD Input...
Page 587 MR1n[PT] = 0 MR1n[PT] = 2 Peripheral Station ADD1 ADD 1 Status Data (C0) should be programmed before enabling the transmitter and loading the corresponding data MPC5200B Users Guide, Rev. 1 ADD2 ADD 2 ADD2 Status Data (ADD 2) Freescale Semiconductor...
Page 588: Purpose
It is requesting the bus. The request must occur immediately after the required one clock de-assertion after a qualified bus grant, and It is the highest priority device, and There is no address retry assertion. Freescale Semiconductor Prioritization Bus Grant FSM Configuration, Status, and Interrupts Watchdog Slave Interface MPC5200B Users Guide, Rev. 1 Overview 16-1...
Page 589: Bus Grant Mechanism
For any TEA assertion (from a watchdog time-out, or other source), a Machine Check exception will result in the e300 core. See the XLB Arbiter interrupt enablement recommendations below for the Arbiter Interrupt Enable Register. For more information on the Machine Check exception, see the 603e Users’ Manual, Section 4.5. 16-2 NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 590: Other Tenure Ending Conditions
Arbiter Bus Activity Time-Out Register (R/W)—MBAR + 0x1F60 • Arbiter Master Priority Enable Register (R/W)—MBAR + 0x1F64 • Arbiter Master Priority Register (R/W)—MBAR + 0x1F68 • Arbiter Snoop Window Register (RW)—MBAR + 0x1F70 MPC5200B Users Guide, Rev. 1 MBAR + 0x1F00 16-3...
Page 591 Select Parked Master. These bits set the master that is used in Park on Programmed Master mode (000 = master 0, 001 = master 1, ..., 111 = master 7). — Reserved 16-4 Rsvd Rsvd Description Arbiter Snoop Window Register (RW)—MBAR MPC5200B Users Guide, Rev. 1 BSDIS 31 lsb Rsvd Rsvd Freescale Semiconductor...
Page 592: Arbiter Version Register (R)—Mbar + 0X1F44
1 until cleared by writing 1 into that bit position. Even if the causal condition is removed, the bit remains set until cleared. Freescale Semiconductor Description NOTE Table 16-2. Arbiter Version Register Version ID[0:15] Version ID[16:31] Description MPC5200B Users Guide, Rev. 1 XLB Arbiter Registers—MBAR + 0x1F00 31 lsb 16-5...
Page 593: Arbiter Interrupt Enable Register (R/W)—Mbar + 0X1F4C
MME, TTAE, TTRE, as they do not result in a TEA; in case of DTE and BAE, arbiter interrupt can be enabled, as the TEA assertion always preceeds the interrupt. 16-6 Table 16-3. Arbiter Status Register Rsvd Description NOTE MPC5200B Users Guide, Rev. 1 31 lsb Freescale Semiconductor...
Page 594: Arbiter Address Capture Register (R)—Mbar + 0X1F50
Time-Out Status). Unlocking the register does not clear its contents. Table 16-5. Arbiter Address Capture Register msb 0 RESET: RESET: Freescale Semiconductor Rsvd SEAE MME TTAE TTRE ECWE TTME BAE Description Address[0:15] Address[16:31] MPC5200B Users Guide, Rev. 1 XLB Arbiter Registers—MBAR + 0x1F00 31 lsb 31 lsb 16-7...
Page 595: Arbiter Address Tenure Time-Out Register (R/W)—Mbar + 0X1F58
The Arbiter Address Tenure watchdog can be enabled/disabled via the Arbiter Configuration Register, bit 30 (AT). Table 16-7. Arbiter Address Tenure Time-Out Register msb 0 Rsvd RESET: 16-8 Description Rsvd TSIZ[0:2] TBST Description ADRTO[4:15] MPC5200B Users Guide, Rev. 1 31 lsb TT[0:4] Freescale Semiconductor...
Page 596: Arbiter Data Tenure Time-Out Register (R/W)—Mbar + 0X1F5C
The Arbiter Bus Activity watchdog can be enabled/disabled via the Arbiter Configuration Register, bit 28 (BA). Table 16-9. Arbiter Bus Activity Time-Out Register msb 0 RESET: Freescale Semiconductor ADRTO[16:31] Description DATTO[4:15] DATTO[16:31] Description BUSTO[0:15] MPC5200B Users Guide, Rev. 1 XLB Arbiter Registers—MBAR + 0x1F00 31 lsb 31 lsb 16-9...
Page 597: Arbiter Master Priority Enable Register (R/W)—Mbar + 0X1F64
Master 1 Priority Register Enable Master 0 Priority Register Enable Table 16-11. Hardware Assignments of Master Priority Master Priority M7–M4 — 16-10 BUSTO[16:31] Description Rsvd Description Description Unused PCI Target Interface MPC5200B Users Guide, Rev. 1 31 lsb Table 16-10. 31 lsb Freescale Semiconductor...
Page 598: Arbiter Master Priority Register (R/W)—Mbar + 0X1F68
Master 0 Priority Freescale Semiconductor Description BestComm e300 Core Rsvd M6 Priority Rsvd M5 Priority Rsvd M2 Priority Rsvd M1 Priority Description MPC5200B Users Guide, Rev. 1 XLB Arbiter Registers—MBAR + 0x1F00 Rsvd M4 Priority 31 lsb Rsvd M0 Priority 16-11...
Page 599 The MPC5200B implementation of this address snooping control is shown in the figure below. At the start of a master’s address tenure, the master interface decodes the address and determines if it needs to be snooped, based on the configuration of the Arbiter Snoop Window Register.
Page 600: Arbiter Reserved Registers—Mbar + 0X1F00-1F3C, 0X1F74-1Fff
These are reserved registers and should not be accessed. msb 0 RESET: RESET: Name 0:31 — Reserved Freescale Semiconductor Description Table 16-14. Arbiter Reserved Registers Reserved Reserved Description MPC5200B Users Guide, Rev. 1 XLB Arbiter Registers—MBAR + 0x1F00 31 lsb 16-13...
Page 601 XLB Arbiter Notes MPC5200B Users Guide, Rev. 1 16-14 Freescale Semiconductor...
Page 602: Overview
Section 17.3, SPI Registers—MBAR + 0x0F00 • Section 17.4, Functional Description The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. Figure 17-1 shows the SPI block diagram.
Page 603: Spi Signal Description
(SSOE = 0) or the slave select output (SSOE = 1) when the SPI is in master mode and the associated data direction bit is set. 17-2 Function1 Master Data In/Slave Data Out Master Data Out/Slave Data In Serial Clock Slave Select MPC5200B Users Guide, Rev. 1 Reset State Freescale Semiconductor...
Page 604: Spi Registers—Mbar + 0X0F00
SPI Data Register • SPI Port Data Register • SPI Data Direction Register Table 17-2. SPI Control Register 1 SWOM MSTR CPOL (unused) Description MPC5200B Users Guide, Rev. 1 SPI Registers—MBAR + 0x0F00 (0x0F09) (0x0F0D) (0x0F10) 7 lsb CPHA SSOE LSBFE 17-3...
Page 605: Spi Control Register 2—Mbar + 0X0F01
SS input with MODF feature General-purpose input General-purpose output SS output Table 17-4. SPI Control Register 2 Reserved Description Table 17-5. MPC5200B Users Guide, Rev. 1 Slave Mode SS input SS input SS input SS input 7 lsb SPISWAI SPC0...
Page 606: Spi Baud Rate Register—Mbar + 0X0F04
Table 17-6. SPI Baud Rate Register SPPR1 SPPR0 Reserved Description × SPPR IPB CLock SPI Baud Rate = SPI module clock divisor MPC5200B Users Guide, Rev. 1 SPI Registers—MBAR + 0x0F00 MOSI2 SCK3 Slave In SCK in SS In Master Out SCK out SS I/O...
Page 607: Spi Status Register —Mbar + 0X0F05
128.9 KHz 64.45 KHz 1024 32.23 KHz 2048 16.1 KHz Table 17-8. SPI Status Register Reserved MODF Description MPC5200B Users Guide, Rev. 1 Baud Rate Baud Rate IPB 66.0 IPB 132.0 33.00 MHz 66.00 MHz 16.50 MHz 33.00 MHz 8.250 MHz 16.50 MHz...
Page 608: Spi Data Register—Mbar + 0X0F09
Table 17-9. SPI Data Register Description Table 17-10. SPI Port Data Register Description Table 17-11. SPI Data Direction Register DDR5 DDR4 DDR3 MPC5200B Users Guide, Rev. 1 SPI Registers—MBAR + 0x0F00 7 lsb Table 17-8 for more 7 lsb 7 lsb DDR2...
Page 609: Master Mode
SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and MSTR control bits. 17-8 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 610: Slave Mode
SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. Freescale Semiconductor NOTE MPC5200B Users Guide, Rev. 1 Functional Description 17-9...
Page 611: Clock Phase And Polarity Controls
The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. 17-10 MISO MISO MOSI MOSI MPC5200B Users Guide, Rev. 1 SLAVE SPI SHIFT REGISTER Freescale Semiconductor...
Page 612 Freescale Semiconductor Begin Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 MPC5200B Users Guide, Rev. 1 Functional Description Bit 1 Minimum 1/2 SCK for t Bit 6 17-11...
Page 613 Bit 2 Bit 3 Bit 4 Bit 5 for baud rate calculations for all bit conditions, based on a 40 MHz SPI module clock. The two MPC5200B Users Guide, Rev. 1 Bit 1 Minimum 1/2 SCK for t Bit 6...
Page 614: Special Features
MISO MOMI SPIDDR 6 SPI port (DDR1) pin 0 SWOM enables open drain output. SPI port pin 6 becomes general-purpose I/O. MPC5200B Users Guide, Rev. 1 Functional Description Table Slave Mode MSTR = 0 Serial In MOSI SPIDDR 7 (DDR0)
Page 615: Error Conditions
(i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). 17-14 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 616: Spi Interrupts
SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied into the SPIDR Freescale Semiconductor NOTE MPC5200B Users Guide, Rev. 1 Functional Description 17-15...
Page 617 Functional Description MPC5200B Users Guide, Rev. 1 17-16 Freescale Semiconductor...
Page 618: Overview
C) is a two-wire, bidirectional serial bus that provides a simple, efficient method for data exchange between devices. This two-wire bus minimizes the interconnection between devices. The MPC5200B contains 2 identical and independent I • I2C1 = MBAR + 0x3D00 •...
Page 619: Start Signal
C has simple bidirectional two-wire bus for efficient inter-IC control. The two wires, serial data line (SDA) and serial clock line (SCL), carry information between MPC5200B and other devices connected to the bus. Each device, including MPC5200B, is recognized by a unique address, and can operate as either transmitter or receiver, depending on the function of the device.
Page 620: Slave Address Transmission
SCL held low while Interrupt is serviced Interrupt Bit Set (Byte Complete) Bit1 Bit0(R/W) Bit2 Bit7 Bit6 Acknowledgement From Receiver MPC5200B Users Guide, Rev. 1 C Controller Master Release data Slave drives Low Bit1 Bit0(R/W) Ack Bit Slave Stop Release data...
Page 621: Timing Diagram—Receiver
Bit5 Bit3 Bit4 Bit2 Figure 18-5 shows examples of: Register Address DATA Rept 7-bit DATA Slave Address From Master to Slave From Slave to Master MPC5200B Users Guide, Rev. 1 Bit1 Bit0(R/W) DATA DATA DATA A/A SP DATA Freescale Semiconductor...
Page 622: Timing Diagram—Clock Synchronization
• C Status Register (0x3D04) • C Data I/O Register • C Interrupt Control Register • MPC5200B Users Guide, Rev. 1 C Interface Registers Start Counting High Period C modules. There is also one glitch filter control (0x3D0C) (0x3D10) (0x3D20)
Page 623 The following figure illustrates the relationship between system clock and the I2C signals. 18-6 Table 18-2. I C Address Register Reserved Description C responds to, when addressed as a slave. C Frequency Divider Register Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Reserved 31 lsb Freescale Semiconductor...
Page 624: System Clock
SCL Hold of START >= (0.004)*[SCL (in kHz)]*(SCL Period) (7) SCL Hold of STOP >= (0.004)*[SCL (in kHz)]*(SCL Period) (8) In this case, the simplest strategy for the system programmer to follow is this: MPC5200B Users Guide, Rev. 1 Freescale Semiconductor 18-7...
Page 625 FDR bits that satisfy the system programmer, because Table 18-4 has duplicated entries. Table 18-4. I2C Frequency Divider Bit Selection FDR[7,6] FDR[5,1,0] 18-8 FDR[4,3,2] SCL Period SDA Hold MPC5200B Users Guide, Rev. 1 SCL Hold SCL Hold of START of STOP Freescale Semiconductor...
Page 626 Freescale Semiconductor FDR[4,3,2] SCL Period SDA Hold 1152 2304 1280 2560 1536 3072 1920 3840 1280 MPC5200B Users Guide, Rev. 1 C Interface Registers SCL Hold SCL Hold of START of STOP 1150 1153 1278 1281 1534 1537 1918 1921...
Page 627 SDA Hold 1536 1792 1024 2048 1152 2304 4608 1280 2560 5120 1536 3072 6144 1026 MPC5200B Users Guide, Rev. 1 SCL Hold SCL Hold of START of STOP 1022 1025 1148 1154 2300 2306 1276 1282 2556 2562 1532...
Page 628 SDA Hold 1920 3840 7680 1026 1280 2560 1536 3072 1792 3584 1024 2048 4096 MPC5200B Users Guide, Rev. 1 C Interface Registers SCL Hold SCL Hold of START of STOP 1916 1922 3836 3842 1276 1282 1532 1538 1788...
Page 629 3072 6144 1028 12288 2052 1920 3840 7680 1028 15360 2052 1280 2560 5120 1536 3072 MPC5200B Users Guide, Rev. 1 SCL Hold SCL Hold of START of STOP 1144 1156 2296 2308 4600 4612 1272 1284 2552 2564 5112...
Page 630 3584 7168 1028 1024 2048 4096 8192 1028 Table 18-5. I C Control Register TXAK RSTA Reserved MPC5200B Users Guide, Rev. 1 C Interface Registers SCL Hold SCL Hold of START of STOP 3064 3076 1784 1796 3576 3588 1016...
Page 631 C module are disabled. This does not clear currently pending interrupt C module are enabled. An I C interrupt occurs, provided the status C is a receiver, not a transmitter. MPC5200B Users Guide, Rev. 1 C module losing Freescale Semiconductor...
Page 632 This bit must be cleared by software writing it low in the interrupt routine Freescale Semiconductor Table 18-6. I C Status Register AKF SRW RXAK Reserved Description MPC5200B Users Guide, Rev. 1 C Interface Registers Reserved 31 lsb C Address Register) is matched C Control Register clears this bit. 18-15...
Page 633 In Slave Mode—the same functions are available after an address match occurs. 8:31 — Reserved 18-16 Description C is in slave mode, a complete address transfer occurred with Table 18-7. I C Data I/O Register Reserved Description MPC5200B Users Guide, Rev. 1 Reserved 31 lsb Freescale Semiconductor...
Page 634 Clear by writing 0 to this bit position. Reset condition enables IE1. 8:31 — Reserved The Interrupt Control register is common to both MPC5200B I follows: • To the CPU interrupt, if IE is set to 1. • To the TX requestor at SDMA, if TE is set to 1.
Page 635 1110 - Filter glitches up to width of 14 IPBUS clock cycles 1111 - Filter glitches up to width of 15 IPBUS clock cycles 8:31 — Reserved 18-18 Table 18-9. I C Filter Register Reserved Description MPC5200B Users Guide, Rev. 1 C transaction is Reserved 31 lsb Freescale Semiconductor...
Page 636: Transfer Initiation And Interrupt
STOP signal. Freescale Semiconductor C module. The width of glitch to absorb can be specified in terms on number of IPBUS clock C interface system. MPC5200B Users Guide, Rev. 1 Initialization Sequence command bit (SRW). Writing to the 18-19...
Page 637 Special Note on AKF A new status bit has been added to MSR[4] for the MPC5200B release of this chip. The reason for this is that the legacy I2C module was found to violate, in a merely academic sense, the I2C specification by sending out a very short 9th clock pulse after losing arbitration to another master.
Page 638 Generate Set TX Stop Signal Mode Write Data To MDR Read Data Dummy Read From MDR From MDR And Store MPC5200B Users Guide, Rev. 1 Transfer Initiation and Interrupt Arbitration Lost AAS=1 Data Transfer Address TX/RX Transfer SRW=1 (Write) ACK From...
Page 639 Transfer Initiation and Interrupt MPC5200B Users Guide, Rev. 1 18-22 Freescale Semiconductor...
Page 640 MSCAN2 = MBAR + 0x0980 The Motorola Scalable Controller Area Network (MSCAN) definition is based on the MSCAN12 definition which is the specific implementation of the Motorola Scalable CAN concept targeted for the Freescale Semiconductor, Inc. (formerly Motorola) MC68HC12 Microcontroller Family.
Page 641: Rxcan — Can Receiver Input Pin
External Signals The MSCAN uses two external pins. In the MPC5200B the MSCAN pins are shared with other funtionality and can be available at two different groups of pins. The configuration of the pin-muxing is controlled by the Port Configuration Register, see Section 7.
Page 642: Can System
MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MPC5200B MCU level. The address offset is defined at the module level.
Page 643: Memory Map / Register Definition
MSCAN Identifier Mask Register 1 (CANIDMR1) MSCAN Identifier Mask Register 2 (CANIDMR2) MSCAN Identifier Mask Register 3 (CANIDMR3) MSCAN Identifier Acceptance Register 4 (CANIDAR4) MSCAN Identifier Acceptance Register 5 (CANIDAR5) MSCAN Identifier Acceptance Register 6 (CANIDAR6) MPC5200B Users Guide, Rev. 1 Access Freescale Semiconductor...
Page 644 MSCAN Identifier 6 Mask Register 6 (CANIDMR6) MSCAN Identifier Mask Register 7 (CANIDMR7) Foreground Receive Buffer (CANRXFG) Foreground Transmit Buffer (CANTXFG) Table 19-3. MSCAN Control Register 0 MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb 19-5...
Page 645 Initialization Mode Request—When the CPU sets this bit, MSCAN skips to initialization mode. Any ongoing transmission or reception is aborted and bus synchronization lost. The module indicates entry to initialization mode by setting INITAK=1 19-6 Description MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 646: Mscan Control Register 1 (Canctl1)—Mbar + 0X0901
1 = MSCAN wakes-up the CPU only in case of a dominant pulse on the bus which has a length of T Freescale Semiconductor Table 19-4. MSCAN Control Register 1 Description and WUPE=1 in CANCTL0 MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb 19-7...
Page 647 Baud Rate Prescaler—bits determine time quanta (Tq) clock used to build up individual bit timing, see BRP5 BRP4 19-8 Description SJW[1:0] BRP[5:0] Description Table 19-6. Table 19-6. Baud Rate Prescaler BRP3 BRP2 BRP1 MPC5200B Users Guide, Rev. 1 7 lsb BRP0 Prescaler Value (P) Freescale Semiconductor...
Page 648: Mscan Bus Timing Register 1 (Canbtr1)—Mbar + 0X0905
(Prescaler value) • (Number of Time Quanta) CANCLK Table 19-8. Time Segment 1 Values TSEG11 TSEG10 MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition BRP0 Prescaler Value (P) 7 lsb TSEG[13:10] Time segment 1 1 Tq clock cycle (a)
Page 649 19-10 TSEG11 TSEG10 Table 19-9. Time Segment 2 Values TSEG20 RSTAT[1:0] TSTAT[1:0] MPC5200B Users Guide, Rev. 1 Time segment 1 4 Tq clock cycles 15 Tq clock cycles 16 Tq clock cycles Time segment 2 1 Tq clock cycle (a)
Page 650 Overrun Interrupt Flag—flag is set when a data overrun condition occurs. If not masked, an Error interrupt is pending while this flag is set. 0 = No data overrun condition. 1 = data overrun detected. Freescale Semiconductor Description MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 19-11...
Page 651: Mscan Receiver Interrupt Enable Register (Canrier)—Mbar + 0X0909
10 = Generate CSCIF interrupt only if receiver enters or leaves “RxErr” or “BusOff” state. Discard other Rx state changes for generating CSCIF interrupt. 11 = Generate CSCIF interrupt on all Rx state changes. 19-12 Description RSTATE[1:0] TSTATE[1:0] Description MPC5200B Users Guide, Rev. 1 7 lsb Freescale Semiconductor...
Page 652: Mscan Transmitter Flag Register (Cantflg)—Mbar + 0X090C
Read: Anytime Write: Anytime for TXEx flags when not in Initialization Mode; write of “1” clears flag, write of ‘0’ is ignored. Freescale Semiconductor Description Reserved Description MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb TXE[2:0] 19-13...
Page 653: Mscan Transmitter Interrupt Enable Register (Cantier)—Mbar+0X090D
Write: Anytime when not in Initialization Mode; write of “1” clears flag, write of ‘0’ is ignored. Note: Software must not clear one or more bits of TXE Flag and simultaneously set the respective ABTRQ bit(s). 19-14 Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 7 lsb TXEIE[2:0] 7 lsb ABTRQ[2:0] Freescale Semiconductor...
Page 654: Mscan Transmitter Message Abort Ack(Cantaak)—Mbar +0X0911
READ: Find the lowest ordered bit set to ‘1’, all other bits will be read as ‘0’ WRITE: Anytime when not in Initialization Mode Freescale Semiconductor Reserved Description Reserved Description MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb ABTAK[2:0] 7 lsb TX[2:0] 19-15...
Page 655: Mscan Id Acceptance Control Register (Canidac)—Mbar + 0X0915
IDHIT0 IDAM0 Identifier Acceptance Mode Two 32-bit Acceptance Filters Four 16-bit Acceptance Filters Eight 8-bit Acceptance Filters Filter Closed MPC5200B Users Guide, Rev. 1 7 lsb IDHIT[2:0] Identifier Acceptance Hit Filter 0 Hit Filter 1 Hit Filter 2 Hit Filter 3 Hit...
Page 656: Mscan Receive Error Counter Register (Canrxerr)—Mbar + 0X091C
Reading this register when in any other mode other than sleep or Initialization may return an incorrect value. Writing to these registers when in special modes can alter the MSCAN functionality. Freescale Semiconductor RxERR[7:0] Description NOTE NOTE TxERR[7:0] Description NOTE NOTE MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb 7 lsb 19-17...
Page 657 Adress Offset RESET: msb 0 Adress Offset RESET: 19-18 0x920 / 0x9A0 0x921 / 0x9A1 0x924 / 0x9A4 0x925 / 0x9A5 MPC5200B Users Guide, Rev. 1 7 lsb CANIDR0 7 lsb CANIDR1 7 lsb CANIDR2 7 lsb CANIDR3 Freescale Semiconductor...
Page 658 For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1 and CANIDMR0/1) are applied. Freescale Semiconductor 0x930 / 0x9B0 0x931 / 0x9B1 0x934 / 0x9B4 0x935 / 0x9B5 Description MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb CANIDR4 7 lsb CANIDR5 7 lsb CANIDR6...
Page 659: Mscan Id Mask Register (Canidmr0-7)—Mbar + 0X0928
Adress Offset RESET: msb 0 Adress Offset RESET: 19-20 0x928 / 0x9A8 0x929 / 0x9A9 0x92C / 0x9AC 0x92D / 0x9AD MPC5200B Users Guide, Rev. 1 7 lsb CANIDMR0 7 lsb CANIDMR1 7 lsb CANIDMR2 7 lsb CANIDMR3 Freescale Semiconductor...
Page 660 — CANIDMR3 — CANIDMR5 Freescale Semiconductor 0x938 / 0x9B8 0x939 / 0x9B9 0x93C / 0x9BC 0x93D / 0x9BD Description MPC5200B Users Guide, Rev. 1 Memory Map / Register Definition 7 lsb CANIDMR4 7 lsb CANIDMR5 7 lsb CANIDMR6 7 lsb...
Page 661: Programmer's Model Of Message Storage
Time Stamp Register (Low Byte) Figure 19-28. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM ID27 ID26 ID25 ID24 = Unused MPC5200B Users Guide, Rev. 1 Bit 0 ADDR ID23 ID22 ID21 $__00 Freescale Semiconductor...
Page 662 IDE (=1) ID13 ID12 ID11 ID10 DLC3 = Unused Section 19.5.7, MSCAN Receiver Flag Register Section 19.5.9, MSCAN Transmitter Flag Register (CANTFLG)—MBAR + MPC5200B Users Guide, Rev. 1 Programmer’s Model of Message Storage Bit 0 ADDR ID17 ID16 ID15 $__01 $__04...
Page 663: Identifier Registers (Idr)
DLR register. DB7 - DB0 — Data Bits 7-0 19-24 Table 19-28. Standard Identifier Mapping IDE (=0) = Unused MPC5200B Users Guide, Rev. 1 Bit 0 ADDR $__x0 $__x1 $__x4...
Page 664: Data Length Register (Dlr)
• If more than one buffer has the same lowest priority, message buffer with lower index number wins. Freescale Semiconductor Table 19-29. Data Length Codes Data Length Code DLC1 Description MPC5200B Users Guide, Rev. 1 Programmer’s Model of Message Storage Data Byte Count DLC0 7 lsb 19-25...
Page 665: Mscan Time Stamp Register High (Tsrh)—Mbar + 0X097C
Functional Description 19.7.1 General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. 19-26 Description Description MPC5200B Users Guide, Rev. 1 7 lsb 7 lsb Freescale Semiconductor...
Page 666: Message Storage
1. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991. Freescale Semiconductor CPU bus TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO MPC5200B Users Guide, Rev. 1 Functional Description to be able to send an 19-27...
Page 667: Transmit Structures
Organization. While the background receive buffer (RxBG) is exclusively associated Section Figure 19-3., User Model for Message Buffer Storage) (Section 19.7.3, Identifier Acceptance MPC5200B Users Guide, Rev. 1 Organization. Section 19.6, Programmer’s Model of Message contains an 8-bit “Local Priority”...
Page 668: Identifier Acceptance Filter
(Section 19.5.14, MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0x0915 / Section 19.5.18, MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 / 0x09A0. These Identifier Hit flags (IDHIT2-0) clearly identify MPC5200B Users Guide, Rev. 1 Functional Description where the MSCAN treats its...
Page 669: Bit Maskable Identifier Acceptance Filter
ID10 CANIDMR1 CANIDAR1 ID Accepted (Filter 0 Hit) ID21 ID20 IDR1 ID15 ID14 IDR1 ID10 CANIDMR1 CANIDAR1 CANIDMR3 CANIDAR3 MPC5200B Users Guide, Rev. 1 IDR2 IDR3 IDR2 ID10 IDR3 CANIDMR2 CANIDMR3 CANIDAR2 CANIDAR3 IDR2 IDR3 IDR2 ID10 IDR3 Freescale Semiconductor...
Page 670: Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. Freescale Semiconductor ID21 ID20 IDR1 ID15 ID14 IDR1 ID10 MPC5200B Users Guide, Rev. 1 Functional Description IDR2 IDR3 IDR2 ID10 IDR3 19-31...
Page 671: Clock System
Figure 19-7. MSCAN Clocking Scheme Section 19.5.4, MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x981 NOTE CANCLK ------------------------------------------------------- Prescaler Þ value (reference Figure 19-8): MPC5200B Users Guide, Rev. 1 Section Mode). Time quanta clock (Tq) Prescaler (1 .. 64) Freescale Semiconductor...
Page 672: Segments Within The Bit Time
Section 19.5.6, MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0x0905 NOTE Time Segment 2 TSEG2 MPC5200B Users Guide, Rev. 1 Functional Description Þ Quanta Time Segment 2 (PHASE_SEG2) 2 ...
Page 673: Timer Link
SLPAK = 1 CSWAI = X CSWAI = X SLPRQ = X SLPRQ = 1 SLPAK = X SLPAK = 1 MPC5200B Users Guide, Rev. 1 Synchronization Jump Width 1 .. 4 0 .. 3 1 .. 4 0 .. 3 1 ..
Page 674: Cpu Run Mode
Freescale Semiconductor CAN Clock Domain SLPRQ SYNC sync. SYNC SLPAK NOTE (Figure 19-9). The application software must use SLPAK as a handshake Mode). MPC5200B Users Guide, Rev. 1 Functional Description Table 19-35. SLPRQ sync. Flag SLPRQ SLPAK MSCAN in Sleep Mode...
Page 675: Mscan Initialization Mode
Wait for Idle CAN Activity SLPRQ Idle CAN Activity Tx/Rx Message Active NOTE for a detailed description of the Initialization Mode. MPC5200B Users Guide, Rev. 1 (SLPAK & SLPRQ) Sleep (CAN Activity & WUPE) | CAN Activity Freescale Semiconductor Section...
Page 676: Mscan Power Down Mode
SYNC Flag INITAK NOTE Table 19-35 NOTE 0x980). The sensitivity to existing bus action can be modified by applying a low-pass 0x098D): MPC5200B Users Guide, Rev. 1 Functional Description CAN Clock Domain INIT sync. Flag INITRQ INITAK Section 19.5.3, MSCAN Section 19.5.4, MSCAN Control Register 1...
Page 677: Transmit Interrupt
19.7.9.3 Wake-Up Interrupt Activity on the CAN bus occurred during MSCAN internal Sleep Mode and WUPE (CANCTL0)—MBAR + 0x0900 / 0x980 enabled. 19-38 Notes Section 19.5.3, MSCAN Control Register 0 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 678: Error Interrupt
Section 19.7.2.3, Receive Structures Section 19.5.8, MSCAN Receiver Interrupt Enable 0x989). Section 19.5.7, MSCAN Receiver Flag Register Section 19.5.9, MSCAN Transmitter Flag Register (CANTFLG)—MBAR + 0x090C / NOTE MPC5200B Users Guide, Rev. 1 Functional Description occurred. Section 19.5.7, 0x98C. 19-39...
Page 679 Functional Description MPC5200B Users Guide, Rev. 1 19-40 Freescale Semiconductor...
Page 680: Overview
The BDLC module has 6 main modes of operation which interact with the power supplies, pins, and the rest of the MCU as shown below. Freescale Semiconductor network. The user’s software handles each transmitted or received message on a byte-by-byte MPC5200B Users Guide, Rev. 1 Overview ≤ 125 Kbps) Serial...
Page 681: Bdlc Operating Modes State Diagram
Disabled (WAIT instruction and WCM=0) ) is stopped to conserve power and allow the BDLC module to be configured for proper bdlc MPC5200B Users Guide, Rev. 1 > V (Min.) and No MCU reset source asserted BDLCE set in DLCSCR...
Page 682 Some aspects of BDLC module operation can be modified in special test mode. This mode is reserved for internal use only. Freescale Semiconductor NOTE Section 20.7.3.3, BDLC Control Register 2 (DLCBCR2) - MBAR + MPC5200B Users Guide, Rev. 1 Modes of Operation 0x1304. 20-3...
Page 683: Bdlc Block Diagram
RX Shift Register Protocol State Machine Control/ Status TX Data Symbol Encoder/Decoder TX Data To Physical Interface Figure 20-2. BDLC Block Diagram MPC5200B Users Guide, Rev. 1 BARD RX Data RX Data RX Data RX Data RX Digital Filter RX Data...
Page 684: Signal Description
BDLC Control Register 1 (DLCBCR1) BDLC State Vector Register (DLCBSVR) BDLC Control Register 2 (DLCBCR2) BDLC Data Register (DLCBDR) BDLC Rate Select Register (DLCBRSR) BDLC Control Register (DLCSCR) BDLC Status Register (DLCBSTAT) MPC5200B Users Guide, Rev. 1 Signal Description Access 20-5...
Page 685 VPW symbol timing for integer and for a description of BDLC State Vector Register register and how to clear interrupt requests. MPC5200B Users Guide, Rev. 1 7 lsb Section 20.7.3.4, BDLC Data Section 20.7.3.2, BDLC State Vector Section 20.3, Modes of...
Page 686: Bdlc State Vector Register (Dlcbsvr) - Mbar + 0X1300
Received IFR byte Rx data register full Tx data register empty Loss of arbitration CRC error Symbol invalid or out of range Wakeup MPC5200B Users Guide, Rev. 1 Memory Map and Registers 7 lsb Priority 0 (Lowest) 8 (Highest) 20-7...
Page 687: Bdlc Control Register 2 (Dlcbcr2) - Mbar + 0X1304
1 = When set, digital filter input is connected to the transmitter output. The BDLC module is now in Digital Loopback Mode of operation. The transmit pin (TXB) is driven low and not driven by the transmitter output. 20-8 BDLC Control Register 2 Table 20-4. NBFS TEOD MPC5200B Users Guide, Rev. 1 7 lsb TSIFR TMIFR1 TMIFR0 Freescale Semiconductor...
Page 688 Table 1-2. Transmit In-Frame Response Control Bit Priority Encoding WRITE TSIFR TMIFR1 TMIFR0 Freescale Semiconductor NOTE READ TSIFR TMIFR1 TMIFR0 MPC5200B Users Guide, Rev. 1 Memory Map and Registers Section 20.8.1.3, J1850 VPW Valid/Invalid Bits Section ACTUAL (internal register) TSIFR TMIFR1 TMIFR0 20-9...
Page 689: Types Of In-Frame Response
0 = The TMIFR1 bit will be automatically cleared once the BDLC module has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus, a transmitter underrun, or loss of arbitration. 20-10 Figure 20-3. Types of In-Frame Response NOTE MPC5200B Users Guide, Rev. 1 ID n IFR Data Field Freescale Semiconductor...
Page 690 BDLC Data Register. If loss of arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed by an active short) will be sent out. Freescale Semiconductor NOTE MPC5200B Users Guide, Rev. 1 Memory Map and Registers 20-11...
Page 691: Bdlc Data Register (Dlcbdr) - Mbar + 0X1305
This register is used to program the BDLC module so that it compensates for the round trip delays of different external transceivers. Also the polarity of the receive pin (RXB) is set in this register. 20-12 NOTE Table 20-5. BDLC Data Register MPC5200B Users Guide, Rev. 1 7 lsb Freescale Semiconductor...
Page 692 01010 01011 01100 01101 01110 Freescale Semiconductor NOTE Corresponding Expected µ Transceiver’s delays ( MPC5200B Users Guide, Rev. 1 Memory Map and Registers 7 lsb Table 20-7 for the BO[4:0] values )). Refer bdlc Transmitter Symbol Timing Adjustment ( bdlc...
Page 693: Bdlc Rate Select Register (Dlcbrsr) - Mbar + 0X1309
). Only integer multiple of the 1 MHz or 1.048576 MHz bdlc Table 20-8. BDLC Rate Select Register for example rate selects for different bus frequencies. All divisor values from divide by 1 to NOTE MPC5200B Users Guide, Rev. 1 Transmitter Symbol Timing Adjustment ( bdlc 7 lsb...
Page 694: Bdlc Control Register (Dlcscr) - Mbar + 0X130C
) enable/disable for power savings. ) and BDLC module are enabled to allow J1850 communications to take place. ) is disabled, shutting down the BDLC module for power saving. Bus clocks are still running MPC5200B Users Guide, Rev. 1 Memory Map and Registers bdlc 1.048576 MHz...
Page 695: General
See SAE J1850 - Class B Data Communications Network Interface, for more information about 1 and 3 Byte Headers. 20-16 Table 20-12. BDLC Status Register Unimplemented NOTE network. The user’s software handles each transmitted or received message on a byte-by-byte Data (Data1) MPC5200B Users Guide, Rev. 1 7 lsb IDLE Reserved Unimplemented Optional Idle Freescale Semiconductor...
Page 696: J1850 Vpw Symbols
10.4kbps baud rate), depending upon the encoding of the previous bit. The SOF, EOD, EOF and IFS symbols will always be encoded at an assigned level and length. See Freescale Semiconductor +1. The remainder polynomial is initially set to all ones, and then each Section 20.2, Features. Figure 20-5. MPC5200B Users Guide, Rev. 1 Functional Description 20-17...
Page 697: J1850 Vpw Symbols
SOF - Start of Frame Symbol 20-18 128µs Logic “0” 128µs Logic “1” 280µs Inter-Frame Seperator (IFS) Figure 20-5. J1850 VPW Symbols (Figure 20-5(a)). (Figure 20-5(b)). MPC5200B Users Guide, Rev. 1 64µs 64µs 200µs End of Data ≥ 240µs Break 20µs 300µs Freescale Semiconductor...
Page 698: J1850 Vpw Valid/Invalid Bits & Symbols
SAE J1850 transmit and receive symbol timing specifications for the BDLC module. ). The mux interface clock is a divided down version of the bus bdlc Symbol tvp1 tvp2 tva1 tva2 MPC5200B Users Guide, Rev. 1 Functional Description (Figure 20-5(c)). This allows (Figure 20-5(d)). (Figure 20-5(e)). If there (Figure 20-5(f)).
Page 699 20-20 Symbol tva3 tvp3 Symbol tvp1 tvp2 tva1 tva2 tva3 tvp3 Symbol rvp1 rvp2 rva1 rva2 rva3 rvp3 MPC5200B Users Guide, Rev. 1 Unit bdlc bdlc bdlc bdlc Unit bdlc bdlc bdlc bdlc bdlc bdlc bdlc bdlc Unit bdlc bdlc...
Page 700 Symbol rvp1 rvp2 rva1 rva2 rva3 rvp3 due to sampling considerations. bdlc MPC5200B Users Guide, Rev. 1 Functional Description Unit bdlc bdlc bdlc bdlc bdlc bdlc bdlc bdlc bdlc Unit bdlc bdlc...
Page 701: J1850 Vpw Passive Symbols
Figure 20-6(2). Figure 20-6(3). Figure 20-6(4). MPC5200B Users Guide, Rev. 1 (Figure 20-6 20-6(1). (1) Invalid Passive (2) Valid Passive Logic Zero (3) Valid Passive Logic One (4) Valid EOD Symbol and T , the current bit...
Page 702: J1850 Vpw Eof And Ifs Symbols
Freescale Semiconductor 300µs rv4(Max) rv4(Min) rv5(Min) Figure 20-7(2). All nodes must wait until a valid IFS symbol MPC5200B Users Guide, Rev. 1 Functional Description (1) Valid EOF Symbol (2) Valid EOF+ IFS Symbol rv4(Min) , the current symbol will be...
Page 703: J1850 Vpw Active Symbols
, the current bit would be invalid. See Figure 20-8(2). Figure 20-8(3). Figure 20-8(4). rv6(Min) Figure 20-9. J1850 VPW BREAK Symbol MPC5200B Users Guide, Rev. 1 (1) Invalid Active (2) Valid Active Logic One (3) Valid Active Logic Zero (4) Valid SOF Symbol Figure 20-8(1).
Page 704: J1850 Vpw Bitwise Arbitrations
“1” “0” “1” “1” Data Data Data Bit 2 Bit 3 Bit 1 MPC5200B Users Guide, Rev. 1 Functional Description Transmitter A detects an active state on the bus, and stops transmitting “0” “0” Transmitter B wins arbitration and continues “0”...
Page 705: J1850 Bus Errors
If while receiving a message the BDLC module detects a BREAK symbol, it will treat the BREAK as a reception error. 20-26 cycles, after assertion of the transmit pin, before detecting the bdlc MPC5200B Users Guide, Rev. 1 cycles before detecting an bdlc Freescale Semiconductor...
Page 706: Mux Interface
If doing so, the BDLC module will immediately cease transmitting. Symbol invalid or out of range flag set and interrupt generated if enabled.Transmission and reception will be disabled until a valid EOF symbol is detected. 20-11. MPC5200B Users Guide, Rev. 1 Functional Description Table 20-19. 20-27...
Page 707: Protocol Handler
Handler conforms to SAE J1850 - Class B Data Communications Network Interface. Refer to 20-28 4-Bit Up/Down Counter up/down ) is 1.0486MHz, then the period (t bdlc MPC5200B Users Guide, Rev. 1 Filtered Rx Data Out Edge & Count Comparator...
Page 708: Protocol Architecture
Tx Shift Register. After this transfer takes place, the Tx Shadow Register is ready to accept new data from the CPU. Freescale Semiconductor To Pad Drivers Loopback Multiplexer State Machine Tx Shift Register Tx Shadow Register MPC5200B Users Guide, Rev. 1 Functional Description BDLC 20-29...
Page 709: Transmitting A Message
Figure Section 20.8.5, Receiving A Message. Later sections will deal with (IFR). Setting the TEOD bit indicates to the BDLC module 0x1305. MPC5200B Users Guide, Rev. 1 20-12) to either the transmit signal out Section 20.7.3.4, Figure 20-13. Freescale Semiconductor...
Page 710: Transmitting Exceptions
• Error Detection Freescale Semiconductor NOTE NOTE NOTE NOTE Figure 20-13 shows the TEOD bit being set after the write to the MPC5200B Users Guide, Rev. 1 Functional Description 20-31...
Page 711: Aborting A Transmission
BDLC Data Register with $FF will also increase the probability of the transmitter losing arbitration if another node begins transmitting at the same time, also reducing the bus bandwidth needed. 20-32 MPC5200B Users Guide, Rev. 1 Section 20.8.7, Receiving An Freescale Semiconductor...
Page 712: Receiving A Message
Attempt another Is DLCBSVR = $10? transmission? (TDRE) Exit BDLC module Transmit Load next byte to be transmitted into DLCBDR (clears TDRE) (IFR). MPC5200B Users Guide, Rev. 1 Functional Description byte? Jump to Receive IFR Handling Routine Routine 20-33...
Page 713: Bdlc Reception Control Bits
CRC is detected or if an invalid or out of range symbol appears on the SAE J1850 bus. A problem can also arise if the CPU fails to service the BDLC Data Register in a timely manner during a message reception. • Receiver Overrun 20-34 NOTE Flowchart. MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 714 IFR byte(s) will be indicated in the BDLC State Vector Register before the EOF is indicated. Refer to Receiving An In-Frame Response (IFR) Freescale Semiconductor for a description of how to deal with the reception of IFR bytes. MPC5200B Users Guide, Rev. 1 Functional Description Section 20.8.7, 20-35...
Page 715: Transmitting An In-Frame Response (Ifr)
Is DLCBSVR = $04? (EOF) Routine Store received byte Jump to Transmit IFR Is an IFR to Handling Routine be transmitted? MPC5200B Users Guide, Rev. 1 Filter received byte Is this message of any interest? Set IMSG bit in DLCBCR1 Freescale Semiconductor...
Page 716: Ifr Types Supported By The Bdlc Module
As with transmitted messages, IFRs transmitted by the BDLC module will also be received by the BDLC module. For a description of how IFR bytes received by the BDLC module should be handled, refer to Section 20.8.7, Receiving An In-Frame Response Freescale Semiconductor NOTE (IFR). MPC5200B Users Guide, Rev. 1 Functional Description Table 20-20 20-37...
Page 717: Transmit Single Byte Ifr
Again, a discussion of the bytes making up any particular IFR is not within the scope of this document. For a more detailed description of the use of IFRs on an SAE J1850 network, refer to the SAE J1850 document. 20-38 ACTUAL TMIFR0 TSIFR TMIFR1 NOTE MPC5200B Users Guide, Rev. 1 TMIFR0 Freescale Semiconductor...
Page 718 Normalization Bit. If the first BDLC module loses arbitration on the first attempt, it will make repeated attempts to transmit this byte until it is successful, an error occurs or the user sets the TEOD bit. Freescale Semiconductor Section Figure 20-15., Transmitting A Type 1 MPC5200B Users Guide, Rev. 1 Functional Description IFR. 20-39...
Page 719: Transmitting A Type 1 Ifr
Once BDLC module detects, or EOF, IFR transmit attempt is complete Exit Type 1 IFR Transmit Routine Figure 20-15. Transmitting A Type 1 IFR MPC5200B Users Guide, Rev. 1 IFR byte is discarded Jump to Receive IFR Handling Routine Freescale Semiconductor...
Page 720: Transmitting A Type 2 Ifr
IFR byte is discarded Jump to Receive IFR Handling Routine Exit Type 1 IFR Transmit Routine Figure 20-16. Transmitting A Type 2 IFR MPC5200B Users Guide, Rev. 1 Functional Description Was the 11th msg byte received? Set TEOD in DLCBCR2 Figure 20-17.
Page 721: Transmitting Ifr Exceptions
TDRE interrupt in a timely fashion. For a description of how these exceptions can affect the IFR transmit process, refer to 20.8.4.2, Transmitting Exceptions. 20-42 Section 20.8.6.2, BDLC IFR Transmit Control NOTE NOTE NOTE MPC5200B Users Guide, Rev. 1 Bits, the TMIFR1 Section Freescale Semiconductor...
Page 722: Receiving An In-Frame Response (Ifr)
(Invalid Symbol) Is DLCBSVR = $14? (LOA) Is DLCBSVR = $10? (TDRE) Figure 20-17. Transmitting A Type 3 IFR MPC5200B Users Guide, Rev. 1 Functional Description Load next byte to be transmitted into DLCBDR (clears TDRE) Is this the last...
Page 723: Receiving An Ifr With The Bdlc Module
After an additional period of time the EOD symbol will transition into an EOF symbol. When the EOF is received it will be reflected in the BDLC State Vector Register, indicating to the user that the IFR, and the message, is complete. 20-44 NOTE MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 724: Receiving Ifr Exceptions
(in case of LOA) Is DLCBSVR = $04? (EOF) Store received IFR byte Exit IFR Receive Routine MPC5200B Users Guide, Rev. 1 Functional Description Filter received IFR byte Is this IFR of any interest? Set IMSG bit in DLCBCR1 Section...
Page 725: Transmitting Or Receiving A Message In 4X Mode
SAE J1850 bus when the BDLC module is in normal mode will be interpreted as noise on the network by the BDLC module. For more information on the 4XE bit, refer to Section • 4X Mode. MPC5200B Users Guide, Rev. 1 20-46...
Page 726: Bdlc Module Initialization
EOF, transmit (LOA) attempt is complete Attempt another Is DLCBSVR = $10? transmission? (TDRE) Exit BDLC module Transmit Load next byte to be Routine (clears TDRE) MPC5200B Users Guide, Rev. 1 Functional Description Jump to Receive IFR Handling Routine 20-47...
Page 727: Initializing The Configuration Bits
If the BDLC State Vector Register indicates that an interrupt is pending, the user should perform whatever actions are necessary to clear the interrupt source before enabling the interrupts. Whether any interrupts are pending will depend primarily upon how much 20-48 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 728 BDLC Control Register 1. Following this, the BDLC module is ready for operating in interrupt mode. If the user chooses not to enable interrupts, the BDLC State Vector Register must be polled periodically to ensure that state changes in the BDLC module are detected and dealt with appropriately. MPC5200B Users Guide, Rev. 1 Freescale Semiconductor 20-49...
Page 729: Resets
Read DLCBSVR Is DLCBSVR = $00? Set IE bit in DLCBCR1 to enable interrupts Proceed to remaining MCU initialization Section 20.7, Memory Map and Registers which details the registers and their bit-fields. MPC5200B Users Guide, Rev. 1 tests Freescale Semiconductor...
Page 730: Tap Link Module (Tlm) And Slave Tap Implementation
Section 21.9, e300 COP/BDM Interface The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200B's imbedded Freescale MPC603e G2_LE processor.
Page 731: Generic Tlm/Tap Architecture Diagram
TAP Link Module (TLM) and Slave TAP Implementation TRST- TRST- Figure 21-1. Generic TLM/TAP Architecture Diagram 21-2 TAP Link Module (TLM) TRST- TRST- MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 732: Generic Tap Link Module (Tlm) Diagram
TAP Link Module (TLM) and Slave TAP Implementation TLMENA & & & ShiftDR ClockDR UpdateDR ShiftDR ClockDR UpdateDR TLMSEL ShiftDR ClockDR UpdateDR ShiftIR ClockIR UpdateIR MPC5200B Users Guide, Rev. 1 ENA[0:n] Link & DeviceID BdyScan Bypass & & STRST- 21-3...
Page 733: Tlm And Tap Signal Descriptions
IR. TDI is sampled at the TCK rising edge while the active TAP state machine is in either the Shift-IR or Shift-DR state. 21-4 ShiftDR ClockDR UpdateDR ShiftDR ClockDR UpdateDR ShiftIR ClockIR UpdateIR Figure 21-3. Generic Slave TAP MPC5200B Users Guide, Rev. 1 DeviceID BdyScan Bypass Freescale Semiconductor...
Page 734: Test Data Out (Tdo)
No more than one Enable signal can be asserted at one time. Each slave TAP block gates (logical AND) TMS with a unique Enable signal. Any number of TLM:Link DR codes may activate any Enable signal. MPC5200B implements one TLM:Link DR code for each Enable signal.
Page 735: State Diagram—Tap Controller
(RunN) which controls clock execution. All IEEE 1149.1 public instructions are implemented (SAMPLE_PRELOAD, BYPASS, and EXTEST). Figure 21-5 shows the components that make up the microprocessor JTAG/COP serial interface. 21-6 Select-DR Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR MPC5200B Users Guide, Rev. 1 Select-IR Scan Capture-IR Shift_IR Exit1-IR Pause-IR Exit2-IR Update-IR Freescale Semiconductor...
Page 736: Tlm Link Dr Instructions
Long Shift Register Latch External Memory Scan RunN Counter COP_PVR Instruction/Status Register COP Controller — C A U T I O N — Table 21-1. TLM Link-DR Instructions Encoding (ENA[1:0]) MPC5200B Users Guide, Rev. 1 TLM Link DR Instructions Persistent 21-7...
Page 737: Tlm:tlmena
IDCODE The IDCODE instruction selects the 32-bit DeviceID DR to be logically connected between TDI and TDO during DR shift operations. The capture value of the DeviceID DR identifies the manufacturer (Freescale), device type (MPC5200B), and device revision level. 21.8.1.1 Device ID Register Table 21-3.
Page 738: Extest
COP/BDM Interface The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processer core through the Freescale standard COP/BDM interface. For information on the connection between COP connector and MPC5200B refer to the MPC5200B Hardware Specifications.
Page 739 Debug Support and JTAG Interface Notes MPC5200B Users Guide, Rev. 1 21-10 Freescale Semiconductor...
Page 740 ..... . . In Big-Endian architectures, the leftmost bytes (those with a lower address) are most significant. For example, consider the number 1025 stored in a 4Byte integer as shown in the table below. Addr Freescale Semiconductor 00000000 00000000 00000100 00000001 Big-Endian Little-Endian 00000000 00000001 00000000 00000100 00000100 00000000 00000001 00000000 MPC5200B Users Guide, Rev. 1...
Page 741 ..... count CODEC....COder/DECoder, or COmpression/DECommpression MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 742 DTV ....Digital TV DWPCI ....designware PCI—synopsys designware component Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 743 GPTMR ....General Purpose Timer GUI ....Graphical User Interface MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 744 IU ..... Integer Unit Freescale Semiconductor C, and USB—these individual serial controllers request service from the CPM. MPC5200B Users Guide, Rev. 1...
Page 745 MAC ....Media Access Control 00000000 00000000 00000100 00000001 Big-Endian Little-Endian 00000000 00000001 00000000 00000100 00000100 00000000 00000001 00000000 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 746 No-op ....No-operation—a single-cycle operation that does not affect registers or generate bus activity NRT....Non-Real Time Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 747 MSR (IR or DR) is 1. PSC ....Programmable Serial Controller MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 748 Rx, RX ....Receive SAR....Segment And Reassemble Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 749 SPI..... Serial Peripheral Interface—the SPI channel supports the out-of-band control channel to external physical chips. The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and peripheral devices.
Page 750 VA ..... Virtual Address—an intermediate address used in translation of an effective address to a physical address. Freescale Semiconductor MPC5200B Users Guide, Rev. 1 A-11...
Page 751 VxWorks ....From Wind River Systems, is a networked real-time operating system designed to be used in a distributed environment. A-12 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 752 GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24... 8-42 7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register —MBAR + 0x0B28... 8-43 7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register —MBAR + 0x0B2C ... 8-43 Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 753: Interrupt And Bus Errors
Chip Select Control Register—MBAR + 0x0318 ... 9-17 9.7.1.4 Chip Select Status Register—MBAR + 0x031C ... 9-18 9.7.1.5 Chip Select Burst Control Register—MBAR + 0x0328 ... 9-18 9.7.1.6 Chip Select Deadcycle Control Register—MBAR + 0x032C... 9-21 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 754: Pci Controller Type 0 Configuration Space
Tx Start Address PCITSAR(RW) —MBAR + 0x3804 ... 10-24 10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 ... 10-24 10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C... 10-26 10.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810... 10-27 Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 755 ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44...11-10 11.3.2.4 ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48...11-10 11.3.2.5 ATA Rx/Tx FIFO Read Pointer Register—MBAR + 0x3A4C...11-11 11.3.2.6 ATA Rx/Tx FIFO Write Pointer Register—MBAR + 0x3A50...11-11 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 756 SDMA Variable Pointer Register—MBAR + 0x120C... 13-5 13.15.5 SDMA Interrupt Vector, PTD Control Register—MBAR + 0x1210... 13-6 13.15.6 SDMA Interrupt Pending Register—MBAR + 0x1214 ... 13-7 13.15.7 SDMA Interrupt Mask Register—MBAR + 0x1218... 13-8 Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 757 FEC Descriptor Group Address 2 Register—MBAR + 0x3124 ... 14-25 14.5.20 FEC Tx FIFO Watermark Register—MBAR + 0x3144... 14-26 Section 14.6 FIFO Interface ... 14-27 Section 14.7 FEC Tx FIFO Data Register—MBAR + 0x31A4... 14-28 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 758 Tx FIFO Data (0x80)—TFDATA ... 15-41 15.2.39 Tx FIFO Status (0x84)—TFSTAT ... 15-41 15.2.40 Tx FIFO Control (0x88)—TFCNTL ... 15-42 15.2.41 Tx FIFO Alarm (0x8E)—TFALARM ... 15-42 15.2.42 Tx FIFO Read Pointer (0x92)—TFRPTR ... 15-42 Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 759: I 2 C Status Register (Msr)—Mbar + 0X3D0C
MSCAN Transmit Buffer Selection (CANTBSEL)—MBAR + 0x0914 /0x0991 ... 19-15 19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)—MBAR + 0x0915 / 0x0995... 19-16 19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C ... 19-17 MPC5200B Users Guide, Rev. 1 Freescale Semiconductor...
Page 760 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309 ... 20-14 20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C... 20-15 20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D... 20-15 Section 21.8.1.1 Device ID Register ... 21-8 Freescale Semiconductor MPC5200B Users Guide, Rev. 1...
Page 761 MPC5200B Users Guide, Rev. 1 B-10 Freescale Semiconductor...
Page 762 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...

Freescale Semiconductor MPC5200B User Manual

Chapter 1 Introduction

Chapter 2 Signal Descriptions

Chapter 3 Memory Map

Chapter 4 Resets and Reset Configuration

Chapter 5 Clocks and Power Management

Chapter 6 G2_LE Processor Core

Chapter 7 System Integration Unit (SIU)

Chapter 8 SDRAM Memory Controller

Chapter 9 Localplus Bus (External Bus Interface)

Chapter 10 PCI Controller

Quick Links

MPC5200B Users Guide

Related Manuals for Freescale Semiconductor MPC5200B

Summary of Contents for Freescale Semiconductor MPC5200B