Freescale Semiconductor MCF54455 Reference Manual page 94

3.3.5.1 Timing Assumptions
For the timing data presented in this section, these assumptions apply:
1. The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
2. Execution times for individual instructions make no assumptions concerning the OEP's ability to
dispatch multiple instructions in one machine cycle. For sequences where instruction pairs are
issued, the execution time of the first instruction defines the execution time of pair; the second
instruction effectively executes in zero cycles.
3. The OEP does not experience any sequence-related pipeline stalls. The most common example of
stall occurs when a register is modified in the EX engine and a subsequent instruction generates an
address that uses the previously modified register. The second instruction stalls in the OEP until
the previous instruction updates the register. For example, in the following code:
muls.l #<data>,d0
move.l (a0,d0.l*4),d1
the move.l instruction waits three cycles for the muls.l to update D0. If consecutive instructions
update a register and use that register as a base of index value with a scale factor of 1 (Xi.l*1) in
an address calculation, a 2-cycle pipeline stall occurs. If the destination register is used as an index
register with any other scale factor (Xi.l*2, Xi.l*4), a 3-cycle stall occurs.
Address register results from post-increment and pre-decrement modes are
available to subsequent instructions without stalls.
4. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
5. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 3-12.
Freescale Semiconductor
NOTE
Table 3-12. Misaligned Operand References
address[1:0] Size
01 or 11 Word
01 or 11 Long
10 Long
Bus Additional
Operations C(R/W)
Byte, Byte 2(1/0) if read
1(0/1) if write
Byte, Word, 3(2/0) if read
Byte 2(0/2) if write
Word, Word 2(1/0) if read
1(0/1) if write
ColdFire Core
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