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Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
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Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) SDRAM Controller (SDRAMC) PCI Bus Controller (PCI) PCI Bus Arbiter (PCIARB) Integrated Secuity Engine (SEC) IEEE 1149.1 Test Access Port (JTAG)
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Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support System Integration Unit (SIU) Internal Clocks and Bus Architecture General Purpose Timers (GPT) Slice Timers (SLT) Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO) System SRAM FlexBus...
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USB PLL Analog Power (USB_PLLVDD) ... 2-31 2.2.17.9 SDRAM Memory Supply (SDVDD) ... 2-31 2.2.17.10 PLL Analog Power (PLLVDD) ... 2-31 2.2.17.11 PLL Analog Ground (PLLVSS) ... 2-31 viii Contents Title MCF548x Reference Manual, Rev. 3 Page Number Freescale Semiconductor...
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SDRAM Control Register Settings and PALL command ... 18-27 18.8.6 Set the Extended Mode Register ... 18-29 18.8.7 Set the Mode Register and Reset DLL ... 18-29 18.8.8 Issue a PALL command ... 18-30 Contents Title MCF548x Reference Manual, Rev. 3 Page Number Freescale Semiconductor...
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Capabilities Pointer (Cap_Ptr) PCICPR—PCI Dword D ... 19-13 19.3.1.11 Configuration 2 Register (PCICR2)—PCI Dword F ... 19-13 19.3.2 General Control/Status Registers ... 19-13 19.3.2.1 Global Status/Control Register (PCIGSCR) ... 19-14 Freescale Semiconductor Contents Title Chapter 19 PCI Bus Controller MCF548x Reference Manual, Rev. 3 Page...
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Communication Subsystem Initiator Interface ... 19-66 19.4.6.1 Access Width ... 19-67 19.4.6.2 Addressing ... 19-67 19.4.6.3 Data Translation ... 19-68 19.4.6.4 Initialization ... 19-68 19.4.6.5 Restart and Reset ... 19-68 xxii Contents Title MCF548x Reference Manual, Rev. 3 Page Number Freescale Semiconductor...
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USB Memory Map ... 29-4 29.2.2 USB Request, Control, and Status Registers ... 29-9 29.2.2.1 USB Status Register (USBSR) ... 29-9 29.2.2.2 USB Control Register (USBCR) ... 29-10 Freescale Semiconductor Contents Title Chapter 29 USB 2.0 Device Controller MCF548x Reference Manual, Rev. 3 Page...
— Chapter 6, “Floating-Point Unit (FPU),” floating-point unit (FPU) designed for use with the ColdFire family of microprocessors. Freescale Semiconductor includes general descriptions of the modules and features incorporated in provides an alphabetical listing of MCF548x signals, including is intended for system designers who need to understand the operation of...
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PCI bus controller for the describes the MCF548x PCI bus arbiter module, MCF548x Reference Manual, Rev. 3 describes the clocking and internal buses Freescale Semiconductor...
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This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. Freescale Semiconductor describes the MCF548 implementation of the controller area network provides an overview of the MCF548x...
For example, RAMBAR[BA] identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit xliv MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode comm bus Internal communications bus Digital-to-analog conversion Direct memory access Digital signal processing Freescale Semiconductor 0x00C Table i. Example Register Diagram Meaning MCF548x Reference Manual, Rev. 3 Acronyms and Abbreviations...
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Phase-locked loop PLRU Pseudo least recently used Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Receive System integration module Start of frame Test access port Transistor-to-transistor logic Transmit xlvi Meaning MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Program counter Status register PSTDDATA Processor status/debug data port #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address Freescale Semiconductor Meaning Table iii. Notational Conventions Operand Syntax Opcode Wildcard Register Specifications Register Names Port Name Miscellaneous Operands MCF548x Reference Manual, Rev.
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Refer to the Bcc instruction description else as an example. <operations> Optional operation Identifies an indirect address Displacement value, n-bits wide (example: d xlviii Operand Syntax Operations Subfields and Qualifiers is a 16-bit displacement) MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Chapter 17 Took out FlexCan chapter. Fixed timing diagrams in FlexBus chapter. Throughout Added all documentation errata from Revision 3 of the MCF5485RMAD document as described below. Freescale Semiconductor Table iii. Notational Conventions (continued) Operand Syntax Condition Code Register Bit Names Table iv.
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Table 1. MCF548x Divide Ratio Encodings Internal XLB, SDRAM Clock CLKIN–PCI and FlexBus bus, and PSTCLK Ratio Frequency Range (MHz) Frequency Range (MHz) 41.6–50.0 25.0–41.5 25.0 MCF548x Reference Manual, Rev. 3 Core Frequency Range (MHz) 83.33–100 166.66–200 50.0–83.0 100.0–166.66 Freescale Semiconductor...
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8-bit interrupt vector. Autovectoring can optionally be configured through the system interface module (SIM).” to “Please refer to Chapter 13 ‘Interrupt Controller.’” Table 10-2/10-5 Add missing table using Freescale Semiconductor Table iv. MCF548x Revision History (continued) Substantive Changes Internal Clock 50.0...
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Table 2. System PLL Memory Map Name Byte0 CAN1 MBAR + 0x300 Figure 2. System PLL Control Register (SPCR) Table 3. SPCR Field Descriptions MCF548x Reference Manual, Rev. 3 Byte1 Byte2 Byte3 Access SPCR FEC1 FEC0 CAN0 Description Freescale Semiconductor...
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Figure 21-14 and Table 21-18 are missing. Add them as shown below and correct the cross-references to them. Syntax SYNC_SEG Transmit Point Sample Point Freescale Semiconductor Substantive Changes NRZ Signal Time Segment 1 SYNC_SEG (PROP_SEG + PSEG1 + 2) 4 ... 16 8 ...
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Change instances of I2AR to I2ADR. 28.3.2.3/28-5 Change I2ICR to I2CR throughout section. Chapter 28, “I2C After section 27.3.2.4, change instances of R/W to R/W throughout chapter. Interface” Freescale Semiconductor Substantive Changes Table 0-4. Comm Timers External Clock Timer Channel External Signal TIN0...
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Table 31-1/31-1 • Replace PPSCLn entries under the GPIO column with PPSC1PSC0n. There is no PPSCL port. • Replace PPSCHn entries under the GPIO column with PPSC3PSC2n. There is no PPSCH port. Substantive Changes MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Remove overbar from ALE at location AD6. Figure 31-7/Page 31-14 Remove overbar from ALE at location AD6. Figure 31-11/Page Remove overbar from ALE at location AD6. 31-18 Freescale Semiconductor Substantive Changes MCF548x Reference Manual, Rev. 3 Terminology and Notational Conventions lvii...
(PLL) to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple general-purpose I/O ports. Freescale Semiconductor ™ ) bus controller MCF548x Reference Manual, Rev. 3...
Timer Slice Timers x 2 Timers x 4 FlexCAN DSPI Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices. Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices. Available in MCF5485, MCF5483, and MCF5481 devices. DDR SDRAM Interface XL Bus Memory Arbiter...
OEP. The OEP includes five pipeline stages: the first stage decodes instructions and selects operands (DS), and the second stage generates operand addresses (OAG). The third and fourth stages fetch operands (OC1 and OC2), and the fifth stage executes instructions (EX). Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x Family Features...
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
MCF548x family under various core/SDRAM/PCI/Flexbus clocking options. Table 1-2. MCF548x Family Clocking Options Internal XLB, SDRAM Core Bus, and PSTCLK (MHz) 120.0–200 Freescale Semiconductor CLKIN—PCI and FlexBus Frequency (MHz) Frequency (MHz) 60.0–100 30.0–50.0 MCF548x Reference Manual, Rev. 3 MCF548x Family Features...
High-speed operation up to 480 Mbps, full-speed operation at 12 Mbps, and low-speed operation at 1.5 Mbps • Physical interface on chip • Bulk, interrupt, and isochronous transport modes. • Six programmable in/out endpoints and one control endpoint MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
DMA controller. The DSPI supports these SPI features: • Full-duplex, three-wire synchronous transfers • Master and slave mode—two peripheral chip selects in master mode Freescale Semiconductor C two-wire, bidirectional serial bus for on-board MCF548x Reference Manual, Rev. 3 MCF548x Family Features...
Flexible Local Bus (FlexBus) The FlexBus module is intended to provide the user with basic functionality required to interface to peripheral devices. The FlexBus interface is a multiplexed or non-multiplexed bus, with an operating 1-10 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
32-bit slice timers create short cycle periodic interrupts, typically utilized for RTOS scheduling and alarm functionality. A watchdog timer resets the processor if not regularly serviced, catching software hang-ups. Four 32-bit general purpose timers can perform input capture, output compare, and PWM functionality. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x Family Features...
Combinatorial path to provide wake-up from stop mode 1.4.11.3 General Purpose I/O All peripheral I/O pins on the MCF548x family are multiplexed with GPIO, adding flexibility and usability to all signals on the chip. 1-12 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The term ‘negated’ indicates that a signal is inactive. Active-low signals, such as RAS and TA, are indicated with an overbar. 2.1.1 Block Diagram Figure 2-1 displays the signals of the MCF548x. Freescale Semiconductor NOTE MCF548x Reference Manual, Rev. 3...
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PCI address/data bus PCI address/data bus PCI address/data bus PCI address/data bus PCI command/byte enables PCI device select PCI frame PCI initialization — device select Freescale Semiconductor High High High High High — Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z —...
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USB differential data — USB differential data — USB Vbus monitor input — USB bias resistor — USB crystal input — USB crystal output — QSPI data out O:I/O Freescale Semiconductor — — — — — — — — — — —...
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Debug data out / TAP data out TAP clock — Test mode pins — Reset input — Reset output Clock input — No Connect — No Connect — Freescale Semiconductor High High — — — High — — — — — —...
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This pin is a “no connect” on the MCF5481 and MCF5480 devices. This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin should be connected to the appriopriate power rail even is USB is not being used.
This pin is a “no connect” on the MCF5483 and MCF5482 devices. This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin should be connected to the appriopriate power rail even is USB is not being used.
If bursting is used, TSIZ[1:0] is driven to the size of transfer. • If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port size. Freescale Semiconductor Table 2-3. Data Transfer Size TSIZ[1:0] Transfer Size...
SDRAM bus cycles. The address multiplexing supports up to 256 Mbits of SDRAM per chip select. 2-18 Table 2-3. Data Transfer Size (Continued) TSIZ[1:0] Transfer Size 2 bytes (word) 16 bytes (line) MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
This output is the SDRAM clock enable. SDCKE is negated to put the SDRAM into low-power, self-refresh mode. 2.2.2.13 SDR SDRAM Data Strobe (SDRDQS) This signal is connected to SDDQS inputs. It is used in SDR mode only. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x External Signals 2-19...
The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines. 2.2.3.8 Parity Error (PCIPERR) The PCIPERR signal is asserted when a data phase parity error is detected if enabled. 2-20 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
2.2.4 Interrupt Control Signals The interrupt control signals supply the external interrupt level to the MCF548x device. 2.2.4.1 Interrupt Request (IRQ[7:1]) The IRQ[7:1] signals are the external interrupt inputs. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x External Signals 2-21...
Table 2-4. MCF548x Divide Ratio Encodings Internal XLB, SDRAM Bus, and PSTCLK Frequency Range Frequency Range (MHz) 41.6–50.0 83.33–100 30.0–44.4 60.0–88.8 MCF548x Reference Manual, Rev. 3 shows how the logic levels of AD[12:8] Core Frequency Range (MHz) (MHz) 166.66–200 120.0–177.66 Freescale Semiconductor...
The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. the logic level of AD3 corresponds to the byte enable mode for FBCS0 at reset. Freescale Semiconductor Internal Clock 100.0 100.0...
Boot FBCS0 AA Configuration at Reset Disabled Enabled with 63 wait states AD[1:0] Boot FBCS0 Port Size 32-bit port 16-bit port MCF548x Reference Manual, Rev. 3 Table 2-8 shows how the AD2 logic Table 2-9 shows how the logic 8-bit port Freescale Semiconductor...
MII mode operation. 2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1]) These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII mode. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x External Signals 2-25...
USBRBIAS This is the connection for external current setting resistor. It should be connected to a 9.1kΩ +/– 1% pull-down resistor. For the MCF5481 and MCF5480 devices this pin should be connected to a 9.1kΩ +/– 20% pull-down resistor. 2.2.8.4 USBCLKIN This is the input pin for 12-MHz USB crystal circuit.
Controller area network transmit data output. 2.2.10.2 FlexCAN Receive (CANRX0, CANRX1) Controller area network receive data input. 2.2.11 C I/O Signals The I C serial interface module uses the signals in this section. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x External Signals 2-27...
2.2.13.2 DMA Acknowledge (DACK[1:0]) These outputs are asserted to acknowledge that a DMA request has been recognized. 2-28 C interface. It is either driven by the I MCF548x Reference Manual, Rev. 3 C is in slave mode. C interface. Freescale Semiconductor...
JTAG controller in test logic reset state immediately. Tying it to EV JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MCF548x External Signals .
(BDM); if it is high, it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not be changed while RSTI is negated MCF548x Reference Manual, Rev. 3 2-30 Freescale Semiconductor...
This pin supplies positive power to the SDRAM module. 2.2.17.10 PLL Analog Power (PLLVDD) This pin supplies the positive power for the PLL. 2.2.17.11 PLL Analog Ground (PLLVSS) This pin is the negative supply (ground) to the PLL. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 2-31...
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• Chapter 8, “Debug Support,” MCF54 x. This revision of the ColdFire debug architecture encompasses earlier revisions. Freescale Semiconductor provides an overview of the microprocessor core of the MCF54 describes the ColdFire virtual memory describes instructions implemented in the floating-point...
Two separate stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP)—that provide the required isolation between operating modes to support the MMU. • Vector base register to relocate the exception-vector table • Optimized for high-level language constructs Freescale Semiconductor MCF548x Reference Manual, Rev. 3...
— Execute (EX) performs prescribed operations on previously fetched data operands. — Write data available (DA) makes data available for operand write operations only. — Store data (ST) updates memory element for operand write operations only. Figure 3-1 and are summarized as follows: MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
DSCLK DSI 3.2.1.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls. Freescale Semiconductor Instruction Memory (Operand) Misalignment Module...
Enhanced Multiply/Accumulate (EMAC) Unit The EMAC unit in the Version 4e provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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The floating-point unit (FPU) provides hardware support for floating point math operations. The FPU conforms to the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE) Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). Freescale Semiconductor Operand Y Operand X...
8-bit address space identifier (ASID). Conceptually, the virtual address is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address. The expansion of the virtual address affects the following two major debug functions: MCF548x Reference Manual, Rev. 3 Section 8.4.2, “Configuration/Status Freescale Semiconductor...
The user or supervisor programming model is selected based on SR[S]. The following sections describe the registers in the user, EMAC, floating point, and supervisor programming models. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Programming Model...
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Vector base register Cache control register Address space ID register Access control register 0 (data) Access control register 1 (data) Access control register 2 (instruction) Access control register 3 (instruction) MMU base address register Module base address register Freescale Semiconductor...
The CCR, Figure 3-4, occupies SR[7–0], as shown in based on results generated by arithmetic operations. Reset Addr Freescale Semiconductor Figure 3-3, consists of the following registers: Section 5.4.2, “Supervisor/User Stack Figure 3-3. The CCR[4–0] bits are indicator flags Accessed using R/W commands for the status register Figure 3-4.
Programming Model Table Table 3-4 lists register names, the CPU space location, whether the register is written from the processor using the MOVEC instruction, and the complete register name. Freescale Semiconductor 0x801 0x801 Figure 3-8. Vector Base Register (VBR) MCF548x Reference Manual, Rev. 3 Programming Model Section 7.10.2, “Access...
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32 msbs of floating-point data register 4 32 lsbs of floating-point data register 4 32 msbs of floating-point data register 5 32 lsbs of floating-point data register 5 32 msbs of floating-point data register 6 MCF548x Reference Manual, Rev. 3 Register Name Freescale Semiconductor...
The FPU also supports single- and double-precision binary floating-point formats that fully comply with the IEEE-754 standard. For more information, see Chapter 6, “Floating-Point Unit (FPU).” Freescale Semiconductor 16 15 Longword 0x0000_0000 Byte 0x0000_0001 Byte 0x0000_0002...
M68000 Family are available on ColdFire microprocessors. Table 3-6 summarizes these modes and their categories. 3-18 8-Bit Exponent Sign of Mantissa 52-Bit Fraction Figure 3-13. Floating-Point Data Formats Mantissa (integer bit).(fraction) Figure 3-14. Mantissa MCF548x Reference Manual, Rev. 3 23-Bit Fraction Single Double Freescale Semiconductor...
MOVE.W were fully supported; otherwise, only CLR (clear) and TST (test) supported these data types. Based on input from compiler writers and system users, a set of instruction enhancements was proposed to address the following: Freescale Semiconductor Mode Reg. Syntax...
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Move from FPSR Move from FPCR Move from FPIAR Move from FPSR Move Multiple Floating Point Data Registers Floating-Point Multiply Floating-Point Negate Floating-Point No Operation Restore Internal Floating Point State Freescale Semiconductor Mnemonic Source move.l mvs.{b,w} <ea>y mvz.{b,w} <ea>y sats.l tas.b...
(Xi.l*2, Xi.l*4), a 3-cycle stall occurs. Address register results from postincrement and predecrement modes are available to subsequent instructions without stalls. Freescale Semiconductor none If data is valid and modified, push cache line; invalidate line if programmed in CACR (synchronizes pipeline) FPU State Frame →...
Additional C(R/W) 2(1/0) if read 1(0/1) if write 3(2/0) if read 2(0/2) if write 2(1/0) if read 1(0/1) if write Table 3-13 shows the (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl 1(0/1) 2(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 2(1/1) 3(1/1) 2(1/1) Freescale Semiconductor...
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EMAC execution pipeline. In general, these store operations take only 1 cycle to execute, but if preceded immediately by a load, MAC, or MSAC instruction, the EMAC pipeline depth is exposed and execution time is 3 cycles. Table 3-19 lists EMAC execution times. Freescale Semiconductor Destination (Ax) (Ax)+ –(Ax)
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3-21. The table contains 256 exception vectors, the first 64 of which are defined by Freescale. The rest are user-defined interrupt vectors. Vector Numbers Vector Offset (Hex) 6–7 018–01C 16–23 040–05C 25–31 064–07C 32–47 080–0BC Freescale Semiconductor Table 3-21. Exception Vector Assignments Stacked Program Counter — — Fault Fault Fault Fault — Fault...
CF4e exceptions. Note that if a ColdFire processor encounters any fault while processing another fault, it immediately halts execution with a catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state. Freescale Semiconductor Table 3-22. Format/Vector Word Description...
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(SR[15] in the exception stack frame set) and pass control to the trace handler before returning from the original exception. 3-40 Table 3-23. Processor Exceptions Description Table MCF548x Reference Manual, Rev. 3 3-22) signal TLB misses on the following: Freescale Semiconductor...
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OEP, a non-supported instruction exception is generated (vector 0x61). Control is then passed to an exception exception handler that can then process the opcode as required by the system. Freescale Semiconductor Description for more information. MCF548x Reference Manual, Rev. 3...
Thus, every IFP access can be tagged in case an instruction fetch terminates with an error acknowledge. 3-42 # copy 4 bytes from source to destination Table 3-24. OEP EX Cycle Operations Operations MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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FS field indicates the fault occurred on an extension word, it may be necessary for the exception PC to be rounded-up to the next page address to determine the faulting instruction fetch address. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 3-43...
The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module, as shown in Figure 4-1. Multiply-Accumulate Functionality Diagram Freescale Semiconductor Figure Operand Y Operand X...
1 ( )x i 1 – – Figure 4-3. Four-Tap FIR Filter MCF548x Reference Manual, Rev. 3 Figure 4-2. k ( )x i k – b 2 ( )x i 2 b 3 ( )x i 3 – – Freescale Semiconductor...
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64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats. Product Extended Product Accumulator Extension Byte Upper [7:0] Freescale Semiconductor OperandY OperandX Accumulator [31:0] Figure 4-4. Fractional Alignment MCF548x Reference Manual, Rev. 3 Introduction “0”...
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By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator. OperandY OperandX Extension Byte Lower [7:0] MCF548x Reference Manual, Rev. 3 Accumulator [31:0] Freescale Semiconductor...
MACSR[11–8] contains one product/accumulation overflow flag per accumulator. • MACSR[7–4] defines the operating configuration of the MAC unit. • MACSR[3–0] contains indicator flags from the last MAC instruction execution. Freescale Semiconductor 4-6. MACSR MAC status register ACC0 MAC accumulator 0...
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The upper word is zero-filled. The accumulator value is not affected by this rounding procedure. PAVx OMC S/U Figure 4-7. MAC Status Register (MACSR) Table 4-1. MACSR Field Descriptions Description Section 4.2.1.1.1, MCF548x Reference Manual, Rev. 3 “Rounding.” The resulting 16-bit Freescale Semiconductor...
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48-bit accumulator. Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result. Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits. Freescale Semiconductor Description for 16-bit fractions and -1 to 1 - 2 Section 4.2.1.1.1, MCF548x Reference Manual, Rev.
Round on MAC.L and MSAC.L Round-to-32-bits on accumulator stores Unsigned, integer Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Freescale Semiconductor ; save the macsr ; zero the register to ... ; disable rounding in the macsr ; save the accumulators ; save the accumulator extensions ; save the address mask ; move the state to memory ;...
An value is also shown. Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations. 4-10 ; restore the address mask ; restore the macsr MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
EMAC execution pipeline depth, as in the following: mac.w Ry, Rx, Acc0 move.l Acc0, Rz Freescale Semiconductor Table 4-3. EMAC Instruction Summary Multiplies two signed operands yielding a signed result Multiplies two unsigned operands yielding an unsigned result Multiplies two operands and adds/subtracts the product to/from an...
To add optional virtual addressing support, demand-page support, permission checking, and hardware address translation acceleration to the ColdFire architecture, the MMU architecture features the following: • Addresses from the core to the MMU are treated as physical or virtual addresses. Freescale Semiconductor MCF548x Reference Manual, Rev. 3...
— Improved addressing of the ACRs 5.2.2 MMU Architecture Location Figure 5-1 shows the placement of the MMU/TLB hardware. It follows a traditional model in which it is closely coupled to the processor local-memory controllers. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
If the cache set address has fewer bits than the in-page address, the cache is considered physically addressed because these bits are the same in the virtual and physical addresses. If the cache set address has MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
New ACR and CACR bits, Table improvements are not necessary to implement the ColdFire MMU, but they improve functionality for physical and virtual address environments. Freescale Semiconductor Additions,” for more information. (MMUBAR).” 5-1, improve address granularity and supervisor mode protection. These MCF548x Reference Manual, Rev.
To provide the required isolation between these operating modes as dictated by a virtual memory management scheme, a user stack pointer (A7–USP) is added. The appropriate stack pointer register (SSP, USP) is accessed as a function of the processor’s operating mode. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Debugging in a Virtual Environment...
• MMUBAR defines a memory-mapped, privileged data-only space with the highest priority in effective address attribute calculation for the data (that is, the MMUBAR has priority over RAMBAR0). Freescale Semiconductor MCF548x Reference Manual, Rev. 3 MMU Definition...
MMUBAR. The default reset state is an invalid MMUBAR, so that the MMU is disabled and the memory-mapped space is not visible. Reset Reset Addr Figure 5-3. MMU Base Address Register (MMUBAR) Table 5-3 describes MMU base address register fields. 5-10 CPU + 0x008 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
5-4, has the address space mode and virtual mode enable bits. The user must force pipeline synchronization after writing to this register. Therefore, all writes to this register must be immediately followed by a NOP instruction. Freescale Semiconductor Table 5-3. MMUBAR Field Descriptions Description Table 5-4.
0 Virtual mode is disabled. 1 Virtual mode is enabled. 5.5.3.4 MMU Operation Register (MMUOR) Figure 5-5 shows the MMUOR. 5-12 MMUBAR + 0x000 Figure 5-4. MMU Control Register (MMUCR) Table 5-5. MMUCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Clear all non-locked TLB entries. Setting CNL clears all TLB entries that do not have their locked bit set. CNL always reads as zero. 0 No operation 1 Clear all non-locked TLB entries. Freescale Semiconductor STLB CA CNL CAS ITLB ADR MMUBAR + 0x004 Table 5-6. MMUOR Field Descriptions Description MCF548x Reference Manual, Rev.
ASID. The description of MMUCR[ASM] in details on supervisor mode and ASID compares. 5-16 Table 5-8. MMUAR Field Descriptions Description MMUBAR + 0x014 Table 5-9. MMUTR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Table 5-5 gives Freescale Semiconductor...
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00 1 Mbyte: VA[31–20] used for TLB hit 01 4 Kbytes VA[31–12] used for TLB hit 10 8 Kbytes VA[31–13] used for TLB hit 11 1 Kbyte VA[31–10] used for TLB hit Freescale Semiconductor Description MMUBAR + 0x014 Table 5-10. MMUDR Field Descriptions Descriptions MCF548x Reference Manual, Rev.
Each TLB entry consists of two 32-bit fields. The first is the TLB tag entry, and the second is the TLB data entry. TLB size and organization are implementation dependent. TLB entries can be read and written through MMU registers. TLB contents are unaffected by reset. 5-18 Descriptions MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
MMU. By the middle of the KC1 cycle, the memory address is available along with its corresponding access control. Freescale Semiconductor Table 5-11. Version 4 Memory Pipelines Instruction Fetch Pipeline Operand Execution Pipeline Table 5-12.
MMU’s access control Mapping register hit or special mode access To memory controllers plus bus interface KADDR_KC1 KC1 cycle access control MCF548x Reference Manual, Rev. 3 To control for TLB miss logic Untranslated address mapping register’s access control Freescale Semiconductor...
Freescale Semiconductor Table 5-13. PLRU State Bits Meaning A one indicates 31To16 is more recent than 15To00 A one indicates 31To24 is more recent than 23To16 A one indicates 15To08 is more recent than 07To00...
A one indicates 07 is more recent than 06 A one indicates 05 is more recent than 04 A one indicates 03 is more recent than 02 A one indicates 01 is more recent than 00 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Figure 5-11. Version 4 ColdFire MMU Harvard TLB MMU Instructions The MOVE to USP and MOVE from USP instructions have been added for accessing the USP. Refer to the ColdFire Programmer’s Reference Manual for more information. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 5-23...
Arithmetic multiplication ÷ Arithmetic division or conjunction symbol ∼ Invert, operand is logically complemented. An overbar, , is also used for this operation. Freescale Semiconductor Models.” Table 6-1. Notational Conventions Description MCF548x Reference Manual, Rev. 3 Section 6.7.3, “Key Differences...
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Source and destination floating-point data registers, respectively Program counter Address or data register Destination register Source register Index register Table 6-2 describes addressing modes and syntax for floating-point instructions. Description Other Operations Register Specifications MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
For not-a-numbers (NANs), the integer bit is ignored. The exponent in both floating-point formats is an unsigned binary integer with an implied bias added to it. Subtracting the bias from exponent Freescale Semiconductor Table 6-2. Floating-Point Addressing Modes Addressing Modes...
Fraction = Any bit pattern Figure 6-3. Normalized Number Format Fraction = 0 Figure 6-4. Zero Format Fraction = 0 Figure 6-5. Infinity Format MCF548x Reference Manual, Rev. 3 Figure 6-3, never uses the maximum or Figure 6-4. Freescale Semiconductor...
Parameter Data Format Sign (s) Freescale Semiconductor Fraction = Any nonzero bit pattern Figure 6-6. Not-a-Number Format Fraction = Any nonzero bit pattern Figure 6-7. Denormalized Number Format Table 6-3.
6-9, contains an exception enable byte (EE) and a mode control byte (MC). Each EE bit corresponds to a floating-point exception class. The user can separately enable traps for each class of floating-point exceptions. The MC bits control FPU operating modes. Freescale Semiconductor Single-Precision Approximate Ranges 3.4 ×...
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01 To zero (RZ) 10 To minus infinity (RM) 11 To plus infinity (RP) 3–0 — Reserved, should be cleared. INEX CPU + 0x824 Table 6-4. FPCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Mode Control Byte (MC) PREC Freescale Semiconductor...
The ColdFire OEP can execute integer and floating-point instructions simultaneously. As a result, the PC value stacked by the processor in response to a floating-point exception trap may not point to the instruction that caused the exception. 6-10 Table 6-5. FPSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
If the destination is a floating-point data register, the result is in double-precision format but may be rounded to single-precision, if required by the rounding precision, before being stored. If the single-precision mode is selected, the exponent value is in the correct range even if it is stored in Freescale Semiconductor 56-Bit Intermediate Mantissa 52-Bit Fraction...
If the destination is memory or an integer data register, the destination data format determines the rounding boundary. If the rounded result of an operation is inexact, INEX is set in FPSR[EXC]. MCF548x Reference Manual, Rev. 3 6-12 Freescale Semiconductor...
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The specified rounding produces a number as close as possible to the infinitely precise intermediate value and still representable in the selected precision. The tie case in how the 56-bit mantissa allows the FPU to meet the error bound of the IEEE specification. Freescale Semiconductor Select Rounding Mode Check Intermediate Result...
The FPU can test for these conditions and 28 others at the end of any operation affecting condition codes. For floating-point conditional branch instructions, the processor logically combines the 4 bits of the FPCC condition codes to form 32 conditional tests, 16 of which cause an exception if an Freescale Semiconductor NOTE Table 6-8. FPCC Encodings Data Type MCF548x Reference Manual, Rev.
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NAN | (Z | N) Z | (N & NAN) NAN | (N | Z) NAN | Z NAN | Z MCF548x Reference Manual, Rev. 3 Predicate EXC[BSUN] Set 000001 001110 010010 011101 010011 011100 010100 011011 010101 011010 010110 011001 010111 Freescale Semiconductor...
If the exception is taken pre-instruction, the PC contains the address of the next floating-point instruction (nextFP). If the exception is taken post-instruction, the PC contains the address of the faulting instruction (fault). Freescale Semiconductor Equation Predicate...
BSUN exception before executing the conditional instruction. A BSUN exception occurs if the conditional predicate is an IEEE non-aware branch and FPCC[NAN] is set. When this condition is detected, FPSR[BSUN] is set. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Floating-Point Exceptions...
The result written to the destination is the same as the exception disabled case unless the enabled exception occurs on a FMOVE OUT, in which case the destination is unaffected. FPSR[INEX] is not set to allow the handler to set it appropriately. 6-20 Description Description Table 6-14. Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Even if the intermediate result is small enough to be represented as a double-precision number, an overflow can occur if the magnitude of the intermediate result exceeds the range of the selected rounding precision format. See Table 6-17. Freescale Semiconductor Table 6-15. Possible Operand Errors Condition Causing Operand Error Description MCF548x Reference Manual, Rev. 3...
Description Zero, with the sign of the intermediate result. For negative underflow, smallest negative normalized number. For negative underflow, - 0 Table 6-19 shows results when the exception is enabled or MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
After FSAVE executes, the handler should use FMOVEM to access floating-point data registers, because it cannot generate further exceptions or change the FPSR. Freescale Semiconductor Description Table 6-20. Inexact Rounding Mode Values...
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FPU (using FRESTORE) into a different state than that saved by using FSAVE. 6-24 19 18 0000_0 Vector Exception operand upper 32 bits Exception operand lower 32 bits Status register (FPSR) Table 6-22. Format Word Field Descriptions Description MCF548x Reference Manual, Rev. 3 Control Register (FPCR) Freescale Semiconductor...
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(d8,a1,d7),fp5 fcmp.l (d8,pc,d2),fp3 The M68000 FPU allows floating-point instructions to directly specify immediate values; the ColdFire FPU does not support these types of immediate constants. It is recommended that floating-point immediate Freescale Semiconductor Feature M68000 (PC,Xi),FPx 6-28, and...
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M68000-compatible text and the equivalent ColdFire program. 6-30 Table 6-29. ColdFire Equivalent fadd.l (imm1_label,pc),fp3 fsub.s (imm2_label,pc),fp3 fdiv.d (imm3_label,pc),fp3 align 4 imm1_label: long imm1 ;integer longword imm2_label: long imm2 ;single-precision imm3_label: long imm3_upper, imm3_lower ;double-precision MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The following summarizes features of the MCF548x SRAM implementation: • Two 4-Kbyte SRAMs, organized as 1024 x 32 bits • Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle. Freescale Semiconductor NOTE for more information. MCF548x Reference Manual, Rev. 3 Chapter 16,...
The valid bits, RAMBARn[V], are cleared at reset, disabling the SRAM modules. All other bits are unaffected. RAMBARn is read/write by the debug module. NOTE MCF548x Reference Manual, Rev. 3 Section 7.4.1, “SRAM Figure 7-1. Each RAMBAR holds Freescale Semiconductor...
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Data/instruction bus. Indicates whether SRAM is connected to the internal data or instruction bus. 0 Data bus 1 Instruction bus — Reserved, should be cleared. Freescale Semiconductor CPU space + 0xC04 (RAMBAR0), 0xC05 (RAMBAR1) Table 7-1. Table 7-1. RAMBARn Field Description Description MCF548x Reference Manual, Rev.
Section 7.6, “Power & (RAMBAR[7] = 0))) Read the SRAM and return the data if (RAMBAR[8] = 0) Write the data into the SRAM else Signal a write-protect access error MCF548x Reference Manual, Rev. 3 Management.” In particular, C/I is Freescale Semiconductor...
The MCF548x implements a special branch instruction cache for accelerating branches, enabled by a bit in the cache access control register (CACR[BEC]). The branch cache is described in “Branch Acceleration.” RAMBAR[5–0] 0x2B 0x35 0x21 MCF548x Reference Manual, Rev. 3 Section 3.2.1.1.1, Freescale Semiconductor...
Entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for the cache line to be valid. Figure 7-3 shows data cache organization as well as terminology used. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Longword 0 Longword 1 Table 7-3. Valid and Modified Bit Settings Description Operation.” MCF548x Reference Manual, Rev. 3 Way 2 Way 3 • • • • • • Longword 2 Longword 3 Figure 7-4 (D). This process is described Freescale Semiconductor...
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CACR[DCINVA] before the cache is enabled. Figure 7-4. Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern Freescale Semiconductor B: Cache after invalidation, C: Cache after loads in before it is enabled Way 0...
Figure 7-5. Data Caching Operation MCF548x Reference Manual, Rev. 3 Way 3 Way 2 Way 1 • • • • • • • • • • • • Data Line Select Hit 3 Hit 2 Logical OR Hit 1 Hit 0 Freescale Semiconductor...
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In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can service additional read accesses from this buffer until either another fill or a cache-invalidate-all operation occurs. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Cache Operation...
The cache supplies data to data-read accesses that hit in the cache; read misses cause a new cache line to be loaded into the cache. 7-12 Figure MCF548x Reference Manual, Rev. 3 7-4, reset does not automatically Freescale Semiconductor...
Precise operation forces data-read accesses for an instruction to occur only once by preventing the instruction from being interrupted after data is fetched. Otherwise, if the processor is not in precise mode, Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Cache Operation...
Exception processing proceeds immediately. Note that unlike Version 2 and Version 3 access errors, the program counter stored on the exception stack frame points to the faulting instruction. See “Processor Exceptions.” Freescale Semiconductor Chapter 17, “FlexBus.” MCF548x Reference Manual, Rev. 3...
Note that the NOP instruction should be used only to synchronize the pipeline. The preferred no-operation function is the TPF instruction. See the ColdFire Programmer’s Reference Manual for more information on the TPF instruction. 7-16 MCF548x Reference Manual, Rev. 3 Section 3.2.1.2, “Operand Freescale Semiconductor...
Ways 0 and 1 are still updated on write hits (D in Figure 7-7) and may be pushed or cleared only explicitly by using specific cache push/invalidate instructions. However, new cache lines cannot be allocated in ways 0 and 1. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 7-17...
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1 update cache lines. Way 0Way 1Way 2Way 3 While the cache is locked, ways 0 and 1 can be updated by write hits. In this example, memory is configured as copyback, so updated cache lines are marked modified. Freescale Semiconductor...
1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers pending imprecise-mode, write-through or cache-inhibited writes. Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise modes are described in Freescale Semiconductor NOTE DDCM DCINVA DDSP...
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Enable instruction cache 0 Instruction cache disabled. All instructions and tags in the cache are preserved. 1 Instruction cache enabled. — Reserved, should be cleared. 7-20 Description Section 7.9.1.2, “Cache-Inhibited MCF548x Reference Manual, Rev. 3 Accesses.” Figure 7-4. Freescale Semiconductor...
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1 USP enabled. Core uses separate supervisor and user stack pointers. Disable FPU. Determines whether the FPU is enabled. See 0 FPU enabled. 1 FPU disabled 3–0 — Reserved, should be cleared. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3 Cache Register Definition Section 6.1.1, “Overview.” 7-21...
(a total of 512 lines for the data cache and 1024 lines for the instruction cache). The state of CACR[DEC,IEC] does not affect the operation of CPUSHL or CACR[DCINVA,ICINVA]. Disabling a cache by setting CACR[IEC] or CACR[DEC] makes the cache nonoperational without affecting tags, state information, or contents. Freescale Semiconductor Description Section 7.9.1.2, “Cache-Inhibited Accesses.”...
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;increment set index by 1 ;increment set counter ;are sets for this way done? ;set counter to zero again ;increment to next way ;set = 0, way = d0 ;flushed all the ways? MCF548x Reference Manual, Rev. 3 Way Index Way Index Freescale Semiconductor...
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; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it! move.l #0xa2088800,d0;set the instruction cache lock bit movec d0,cacr ;in the CACR Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Cache Management 7-25...
IV6 No action; go to invalid state. IV7 No action; stay in valid state. MCF548x Reference Manual, Rev. 3 IV1—CPU read miss IV2—CPU read hit IV7—CPUSHL & IDPI Valid V = 1 Figure 7-12. Valid (V = 1) Freescale Semiconductor...
WI6—CPUSHL & DDPI Invalid V = 0 Figure 7-14. Data Cache Line State Diagram—Write-Through Mode Table 7-7 describes data cache line transitions and the accesses that cause them. Freescale Semiconductor Table 7-7. CI1—CPU read miss CV5—DCINVA CV6—CPUSHL & DDPI CI3—CPU write miss CD1—CPU...
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CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes. CD5 No action (modified data lost); go to invalid state. CD6 Push modified line to memory; go to invalid state. CD7 Push modified line to memory; go to valid state. Freescale Semiconductor...
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Write miss (write-through) Write hit (copyback) Write hit (write-through) Cache invalidate Cache push Cache push Freescale Semiconductor Response (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. (C,W)I2 Not possible Read line from memory and update cache;...
The following example sets up the cache for FLASH or ROM space only. move.l #0xA30C8100,D0 movec D0, CACR move.l #0xFF00C000,D0 movec D0,ACR0 7-30 Response //enable cache, invalidate it, //default mode is cache-inhibited imprecise //cache FLASH space, enable, //ignore FC2, cacheable, writethrough MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
See Support.” The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding Freescale Semiconductor Figure 8-1. ColdFire CPU Core...
All ColdFire debug signals are unidirectional and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in Section 8.9, “Freescale-Recommended BDM Pinout.” MCF548x Reference Manual, Rev. 3 Section 8.4.2, “Configuration/Status Freescale Semiconductor...
CSR controls capturing of data values to be presented on PSTDDATA. Executing the WDDATA instruction captures data that is displayed on PSTDDATA too. These signals are updated each processor cycle and display two values at a time for two processor clock cycles. Freescale Semiconductor Table 8-1. Debug Module Signals Description Table 8-4 describes PST values.
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{PST for mov.l, PST marker for captured operand) = {0x1, 0xB} {0x1, 0xB} {Operand[3:0], Operand[7:4]} {Operand[3:0], Operand[7:4]} {Operand[11:8], Operand[15:12]} {Operand[11:8], Operand[15:12]} {Operand[19:16], Operand[23:20]} {Operand[19:16], Operand[23:20]} {Operand[27:24], Operand[31:28]} {Operand[27:24], Operand[31:28]} (PST for next instruction) (PST for next instruction,...) MCF548x Reference Manual, Rev. 3 8-3. {E, F} Freescale Semiconductor...
• Whenever the current ASID is loaded by the privileged MOVEC instruction, the ASID is displayed on PSTDDATA. The resulting PSTDDATA sequence for the MOVEC instruction is then {0x1, 0x8, ASID}, where the 0x8 is the data marker for the ASID. Freescale Semiconductor NOTE 0x5).” Four 32-bit storage elements form a FIFO Table 8-4.
Breakpoint state changed to level-1 breakpoint triggered Breakpoint state changed to waiting for level-2 trigger Breakpoint state changed to level-2 breakpoint triggered Stopped mode. Section 8.5.1, “CPU Halt”). Because this encoding defines a NOTE NOTE MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and Freescale Semiconductor 8-5, are treated as 32-bit quantities, regardless of the number of...
CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. It can be read from and written to through the BDM port. Freescale Semiconductor Table 8-7.
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— Reserved, should be cleared. 8-12 FOF TRG HALT BKPT CPU + 0x00 Table 8-8. CSR Field Descriptions Description command clear HALT. command clear BKPT. MCF548x Reference Manual, Rev. 3 BKD0 PCD0 IPW0 SSM OTE command clear TRG. Freescale Semiconductor...
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10 Lower 3 bytes of the target address 11 Entire 4-byte target address Section 8.3.1, “Begin Execution of Taken Branch (PST = — Reserved, should be cleared. Freescale Semiconductor Description Mode.” MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition 0x5).”...
PBR3AC, PBR2AC, PBR1AC, and PBRAC apply to PBR3, PBR2, PBR1, and PBR, respectively, and are functionally identical. They enable or disable ASID, supervisor mode, and user mode breakpoint 8-14 Description PBR2AC PBR1AC CPU + 0x0A MCF548x Reference Manual, Rev. 3 command, the processor executes the PBRAC Freescale Semiconductor...
Table 8-10. BAAR Field Descriptions Description Table Table 8-9, define address attributes and a mask to be matched in the trigger. The ASIDCTRL CPU + 0x06 (AATR), 0x16( AATR1) Description MCF548x Reference Manual, Rev. 3 8-11. 8-11. ATTRASID Freescale Semiconductor...
8-10, configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. In conjunction with the XTDR and its associated debug registers, TDR controls the actions Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
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If both TDL[EBL] and XTDL[EBL] are cleared, all breakpoints are disabled. 8-18 command. WDMREG NOTE Second Level Triggers EDWL EDWU EDLL EDLM EDUM First Level Triggers EDWL EDWU EDLL EDLM EDUM CPU + 0x07 Table 8-12. TDR Field Descriptions Description MCF548x Reference Manual, Rev. 3 EDUU EDUU Freescale Semiconductor...
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EAR1 Address enable bit: Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR. Trigger if address Š ABHR or if address ð ABLR. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition...
Identically the value in ABLR • Inside the range bound by ABLR and ABHR inclusive • Outside that same range XTDR determines the same for ABLR1 and ABHR1. Freescale Semiconductor Description WDMREG CNTRMSK CNTRMSK CPU + 0x09 Table 8-14. PBMR Field Descriptions...
DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the WDEBUG instruction and through the BDM port using the 8-22 Description Description Figure 8-14), specify data patterns used as part of the trigger RDMREG MCF548x Reference Manual, Rev. 3 commands. WDMREG Freescale Semiconductor...
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Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBRn bit allows the corresponding DBRn bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMRn bit causes that bit to be ignored. Freescale Semiconductor DATA (DBR/DBR1) DATA (DBR/DBR1) CPU + 0x0E (DBR), 0x1E (DBR1) Table 8-17.
Section 8.4.11.1, “Resulting Set of Possible Trigger breakpoint conditions. EDLW Reset EDLW — Reset Addr Figure 8-17. Extended Trigger Definition Register (XTDR) Freescale Semiconductor Description NOTE Combinations,” describes how to handle multiple Second Level Triggers EDWL EDWU EDLL EDLM EDUM...
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Address enable bit: Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR1 and ABHR1. Trigger if address > ABHR or if address < ABLR. 8-26 Table 8-21. XTDR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a instruction after HALT. 8-28 {&& Data1_breakpoint}) command into the debug module. Execution continues at the MCF548x Reference Manual, Rev. 3 Section 8.6.1, Freescale Semiconductor...
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0xFF count). Thus, a count of either nine or more sequential single 0xF values or five or more sequential 0xFF values signifies the HALT condition. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Background Debug Mode (BDM)
The basic receive packet, Figure 8-30 Table 8-1. The development system serves as the serial Current Current State Past NOTE 8-19, consists of 16 data bits and 1 status bit MCF548x Reference Manual, Rev. 3 Next Next State Current Freescale Semiconductor...
BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. Freescale Semiconductor Data Field [15:0] Figure 8-19. Receive BDM Packet Description 8-20, consists of 16 data bits and 1 control bit.
BDM command set, the optional set of extension words is defined as address, data, or operand data. 8.5.3.2 Command Sequence Diagrams The command sequence diagram in represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system Freescale Semiconductor Figure 8-21. Op Size Extension Word(s) Figure 8-21.
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Command Code ’NOT READY’ NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Sequence taken if bus error occurs on memory access High- and low-order 16 bits of result in this example). The debug module READ Freescale Semiconductor...
Write A/D Register ( The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Freescale Semiconductor Table NOTE Interface,”...
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Command/Result Formats: 8-36 D[31:16] D[15:0] WDREG Command Format MS DATA LS DATA ’NOT READY’ ’NOT READY’ NEXT CMD BERR ’NOT READY’ WDREG Command Sequence READ MCF548x Reference Manual, Rev. 3 Register NEXT CMD ’CMD COMPLETE’ Freescale Semiconductor...
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Figure 8-27. Command Sequence: READ (B/W) MS ADDR ’NOT READY’ READ (LONG) MS ADDR ’NOT READY’ Operand Data The only operand is the longword address of the requested location. Freescale Semiconductor A[31:16] A[15:0] A[31:16] A[15:0] D[15:0] A[31:16] A[15:0] D[31:16] D[15:0]...
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The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent commands use this address, perform the memory read, increment it by the DUMP current operand size, and store the updated address in the temporary register. Freescale Semiconductor DATA LS ADDR ’NOT READY’ ’NOT READY’...
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’NOT READY’ Figure 8-32. Command Sequence DUMP MCF548x Reference Manual, Rev. 3 D[7:0] ’NOT READY’ NEXT CMD RESULT NEXT CMD BERR ’NOT READY’ ’NOT READY’ NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Freescale Semiconductor...
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The size field is examined each time a dynamically. Command Formats: Byte Word Longword Freescale Semiconductor FILL command to access large blocks of memory. An initial WRITE commands use this address, perform the FILL command, the illegal command response is...
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Figure 8-35. Command Format NEXT CMD ’CMD COMPLETE’ Figure 8-36. Command Sequence MCF548x Reference Manual, Rev. 3 ’NOT READY’ NEXT CMD ’CMD COMPLETE’ NEXT CMD BERR ’NOT READY’ ’NOT READY’ NEXT CMD ’CMD COMPLETE’ NEXT CMD BERR ’NOT READY’ Freescale Semiconductor...
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SYNC execution of this command is considerably less obtrusive to the real-time operation of an application than command sequence. HALT READ RESUME Command Formats: Freescale Semiconductor Figure 8-37. Command Format NEXT CMD ’CMD COMPLETE’ Figure 8-38. Command Sequence command is pending.
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SYNC FORCE serial BDM command to resolve a hung bus condition. FORCE Figure 8-41. Command FORCE MCF548x Reference Manual, Rev. 3 forces generation of FORCE commands until the FORCE command may be FORCE commands, because the BDM FORCE Freescale Semiconductor...
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Control register contents are returned as a longword, most-significant word first. The implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are undefined. Rc encoding: See Table 8-26. Freescale Semiconductor FORCE_TA NEXT CMD “CMD COMPLETE” Figure 8-42. Command Sequence...
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32 msbs of floating-point data register 4 32 lsbs of floating-point data register 4 32 msbs of floating-point data register 5 32 lsbs of floating-point data register 5 32 msbs of floating-point data register 6 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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#0,macsr; rcreg ACCx; wcreg #saved_data,macsr; Freescale Semiconductor Register Name 32 lsbs of floating-point data register 6 32 msbs of floating-point data register 7 32 lsbs of floating-point data register 7 Floating-point instruction address register Floating-point status register Floating-point control register...
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EMAC and FPU programming models. Command/Result Formats: 8-48 // read current macsr contents & save // disable all rounding modes // write the desired accumulator // restore the original macsr RCREG WCREG WCREG MCF548x Reference Manual, Rev. 3 . However, certain hardware Freescale Semiconductor...
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CSR (DRc = 0x00). Note that this read of the CSR clears the trigger status bits RDMREG (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled. Command/Result Formats: Freescale Semiconductor D[31:16] D[15:0] Command/Result Formats WCREG...
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Reserved — RDMREG MS RESULT ’ILLEGAL’ Figure 8-48. Command Sequence RDMREG WDMREG BDM Command Format WDMREG D[31:16] D[15:0] MCF548x Reference Manual, Rev. 3 Initial State Page p. 8-11 — — NEXT CMD LS RESULT NEXT CMD ’NOT READY’ Freescale Semiconductor...
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to either TDR or XTDR to disable trigger options. Freescale Semiconductor MS DATA LS DATA ’NOT READY’...
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3. It passes control to the appropriate exception handler. 8-52 Table 8-29. Exception Vector Assignments Stacked Program Counter Next Next Combinations”), the vector taken is determined by Section 3.8.1, “Exception Stack Frame Definition.” MCF548x Reference Manual, Rev. 3 Assignment Non-PC-breakpoint debug interrupt PC-breakpoint debug interrupt Freescale Semiconductor...
The debug module supports concurrent operation of both the processor and most BDM commands. BDM commands may be executed while the processor is running, except the following: • Read/write address and data registers Freescale Semiconductor Table 5-2. Implementation of this debug interrupt handling fully Section 8.5.1, “CPU MCF548x Reference Manual, Rev.
Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. Freescale Semiconductor describes the SIU programming model, bus describes the clocking and internal buses of describes the functionality of the four general...
• System protection and reset status and control Memory Map/Register Definition Table 9-1 shows the programming model for the SIU. Freescale Semiconductor Chapter 13, “Interrupt Controller,” Section 10.3.2.3, “Watchdog Functions.” Chapter 12, “Slice Timers (SLT).” Chapter 15, “GPIO.” MCF548x Reference Manual, Rev. 3...
RESERVED SECSACR RESERVED RESERVED JTAGID 9-1, specifies the base address and allowable access types for all Chapter 8, “Debug Support.” NOTE MCF548x Reference Manual, Rev. 3 Byte2 Byte3 Access Chapter 18, “SDRAM Controller Only the debug module can Freescale Semiconductor...
Pin control of the multichannel DMA breakpoint. This bit controls whether the BKPT pin can halt the DMA. 0 The assertion of BKPT will not halt the DMA. 1 The assertion of BKPT will halt the DMA. Freescale Semiconductor CPU + 0xC0F PIN2 DSPI MBAR + 0x0010 Table 9-2.
0 SEC Sequential Access is disabled. 1 SEC Sequential Access is enabled. Note: Setting this bit is recommended when the SEC is in use. Description MBAR + 0x38 Table 9-3. SECSACR Field Descriptions Description MCF548x Reference Manual, Rev. 3 SEQEN Freescale Semiconductor...
External reset (PLL Lock qualification) asserted. Cleared by writing a 1 to this bit position. 9.3.1.4 JTAG Device Identification Number (JTAGID) Reset Reset Addr Figure 9-5. JTAG Device ID Register (JTAGID) Freescale Semiconductor MBAR + 0x44 Figure 9-4. Reset Status Register (RSR) Table 9-4. RSR Field Descriptions Description JTAGID Table 9-5...
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ID number for the MCF548x. Its value is hard coded and cannot be modified. Values for the MCF548x are the following: MCF5485 0x0800c01d MCF5484 0x0800d01d MCF5483 0x0800e01d MCF5482 0x0800f01d MCF5481 0x0801001d MCF5480 0x0801101d MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Timers x 2 Timers x 4 FlexCAN DSPI *Available in MCF5485, MCF5484, MCF5483, and MCF5482 devices. **Available in MCF5485, MCF5484, MCF5481, and MCF5480 devices. ***Available in MCF5485, MCF5483, and MCF5481 devices. Figure 10-1. MCF548x Internal Bus Architecture Freescale Semiconductor DDR SDRAM...
The data transfer phase can either be one beat or four, depending on whether or not the transaction is a burst. Freescale Semiconductor Figure 10-3. It shows that the transaction consists MCF548x Reference Manual, Rev.
10-4 Transfer Termination Data Tenure Transfer Arbitration Figure 10-3. Address and Data Tenures MCF548x Reference Manual, Rev. 3 Termination Freescale Semiconductor...
Crypto Clock Enable B - Controls the fast clock to the SEC CRYENA Crypto Clock Enable A - Controls the slow clock to the SEC CAN1EN CAN1 Clock Enable — Reserved, should be cleared. Freescale Semiconductor Table 10-2. System PLL Memory Map Name Byte0 Byte1 CAN1 FEC1 MBAR + 0x300 Table 10-3.
(XARB_PRIEN), depending on the arbiter master priority enable bit for each master. Secondly, masters at the same level of priority will be further sorted by a least recently used 10-6 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
In park on last master mode, the arbiter will assert a bus grant to the last master granted the bus when no masters are asserting a bus request and the one level pipeline will not be violated. Freescale Semiconductor MCF548x Reference Manual, Rev. 3...
Parking Mode. Parking modes are detailed in 00 No parking (default) 01 Reserved 10 Park on most recently used master 11 Park on programmed master as specified by the Select Parked Master bits 21:23 above. Freescale Semiconductor Byte0 Byte1 XARB_ADRTO XARB_DATTO...
10.3.3.2 Arbiter Version Register (XARB_VER) Reset Reset Addr Figure 10-6. Arbiter Version Register (XARB_VER) Name 31–0 Hardware Version ID. The current version number is 0x0001. 10-10 Description MBAR + 0x0244 Table 10-6. VER Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Normally, an interrupt service routine would read the status register Freescale Semiconductor MBAR + 0x0248 Table 10-7. XARB_SR Field Descriptions Description MCF548x Reference Manual, Rev.
(XARB_ADRCAP) or arbiter bus signal capture register (XARB_SIGCAP). These values are also unlocked by writing a 1 to either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does not clear its contents. Freescale Semiconductor Description ADRCAP...
— Reserved, should be cleared. 27–0 DATTO Upper 28-bits fo the Data time-out counter value. This field is prepended to 0xF to generate the full 32-bit time-out counter value. Freescale Semiconductor Description DATTO DATTO MBAR + 0x025C Description MCF548x Reference Manual, Rev. 3...
5. CPU Timer—The I/O signal is not used in this mode. Once enabled, the counters run until they reach a programmed terminal count. When this occurs, an interrupt can be generated to the CPU. This timer mode can be used simultaneously with the simple GPIO mode. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 11-1...
01 IC event occurs at input rising edge. 10 IC event occurs at input falling edge. 11 IC event occurs at any input pulse (i.e., at the second input edge). Freescale Semiconductor Table 11-2. GMSn Field Descriptions Description MCF548x Reference Manual, Rev. 3...
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Open drain. 0 Normal I/O 1 Open Drain emulation—affects all modes that drive the I/O pin (GPIO, OC, and PWM). Any output “1” is converted to a tri-state at the I/O pin. 11-4 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
ON time. 0 PWM output is low during OFF time 1 PWM output is high during OFF time 11-6 Table 11-3. GCIRn Field Descriptions Description WIDTH Table 11-4. GPWMn Field Descriptions Description MCF548x Reference Manual, Rev. 3 LOAD Freescale Semiconductor...
Reserved. Should be cleared. TEXP Timer expired in internal timer mode. Cleared by writing 1 to this bit position. Also cleared if TMS is 000 (i.e., timer not enabled). Freescale Semiconductor Description CAPTURE Figure 11-4. GPT Status Register (GSRn) Table 11-5. GSRn Field Descriptions Description MCF548x Reference Manual, Rev.
This bit controls the counter for CPU timer or watchdog timer modes only. See to understand the operation of these bits across the various modes. 11-8 Description Table 11-2 for precise operation. Table 11-2 for more detail. MCF548x Reference Manual, Rev. 3 Table 11-2 Freescale Semiconductor...
Timer count. GPIO output bit set. Provides the current state of the timer counter. This register does not change while a read is in progress, but the actual timer counter continues unaffected. Freescale Semiconductor Table 12-3. SCRn Field Descriptions Description MBAR + 0x908 (SCNT0), + 0x918 (SCNT1) Figure 12-3.
1 to its bit position. If interrupts are enabled, clearing this status bit also clears the interrupt. 23–0 — Reserved, should be cleared. 12-4 MBAR + 0x90C (SSR0), + 0x91C (SSR1) Figure 12-4. SLT Status Register (SSRn) Table 12-5. SSRn Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2 longwords in length and contain 32 bits of vector Freescale Semiconductor MCF548x Reference Manual, Rev. 3...
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Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since the interrupt controller completely services the acknowledge. This means the interrupt source must be Freescale Semiconductor then vector_number = then vector_number = then vector_number =...
(1 = active request, 0 = no request). The state of the interrupt mask register does not affect the IPR. The IPR is cleared by reset. Freescale Semiconductor Byte0...
INTFRC register is not affected by the interrupt mask register. The INTFRC register is cleared by reset. 13-8 Table 13-5. IMRH Field Descriptions Description INT_MASK[31:16] INT_MASK[15:1] MBAR + 0x70C Table 13-6. IMRL Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor MASK...
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Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes. 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source — Reserved, should be cleared. Freescale Semiconductor INTFRC[63:48] INTFRC[47:32] MBAR + 0x710 Table 13-7. INTFRCH Field Descriptions Description...
000b represents the lowest priority and 111b represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as 000b. Freescale Semiconductor Description Table 13-2 for register offsets Table 13-11.
End of queue interrupt Write ‘1’ to DSR[EOQF] PSC3 interrupt Cleared when service complete PSC2 interrupt Cleared when service complete PSC1 interrupt Cleared when service complete PSC0 interrupt Cleared when service complete MCF548x Reference Manual, Rev. 3 Flag Clearing Mechanism Freescale Semiconductor...
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives in the interrupt controller, the controller examines all the currently-active level-n interrupt requests, Freescale Semiconductor Source Description Combined interrupts from comm Write ‘1’...
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A read from one of the LnACK registers returns the highest priority unmasked interrupt source within the level. 13-14 VECTOR Table 13-2 for register offsets Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset. Freescale Semiconductor Figure 14-1.
— Reserved, should be cleared. 14.3.2.6 Edge Port Flag Register (EPFR) EPF7 EPF6 Reset Addr Figure 14-7. EPORT Port Flag Register (EPFR) Freescale Semiconductor Table 14-5. EPDR Field Descriptions Description EPPD5 EPPD4 EPPD3 Current pin state MBAR + 0xF09 Table 14-6. EPPDR Field Descriptions...
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(EPPARn = 00), pin transitions do not affect this register. 0 Selected edge for IRQx pin has not been detected. 1 Selected edge for IRQx pin has been detected. — Reserved, should be cleared. MCF548x Reference Manual, Rev. 3 14-6 Freescale Semiconductor...
Figure 15-1 is a block diagram of the MCF548x GPIO module. The actual signals and functions available vary for different members of the MCF548x family. See Freescale Semiconductor NOTE Chapter 2, “Signal Descriptions,” MCF548x Reference Manual, Rev. 3 for more details.
PFBCTL[5:4] PFBCTL3 PFBCTL2 PFBCTL1 PFBCTL0 FBCS[5:1] PFBCS[5:1] DACK1 PDMA3 Freescale Semiconductor Alternate Alternate Function 1 Function 2 Flexbus Control BE / BWE[3:2] TSIZ[1:0] Byte write strobes for external data transfer / Port FBCTL[7:4] / Byte enables for external data transfer /...
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Ethernet Controller 1 receive data [3:1] / Port FEC1L[3:1] — — Ethernet Controller 1 receive error / Port FEC1L0 CANRX0 Ethernet Controller 1 management data control / I serial data / FlexCAN 0 receive data MCF548x Reference Manual, Rev. 3 Description Freescale Semiconductor...
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PPSC3PSC24 PSC2CTS PPSC3PSC23 PSC2RTS PPSC3PSC22 PSC2RXD PPSC3PSC21 PSC2TXD PPSC3PSC20 PSC1CTS PPSC1PSC07 Freescale Semiconductor Alternate Alternate Function 1 Function 2 CANTX0 Ethernet Controller 1 management data clock / I clock / FlexCAN 0 transmit data C Serial Control — — C serial data / Port FECI2C1 —...
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GP timer in 2 / Port TIM5 / Interrupt 1 / FlexCAN 2 receive data CANTX1 — GP timer out 2 / Port TIM4 / FlexCAN 1 transmit data MCF548x Reference Manual, Rev. 3 Description Section 15.3.2.5, “Port Freescale Semiconductor...
Table 15-3. MCF548x GPIO Module Memory Map MBAR 31–24 Offset 0xA00 PODR_FBCTL 0xA04 PODR_FEC0H Freescale Semiconductor that there are several cases where a function is mapped to more than Table 15-2. MCF548x Multiple-Pin Functions Direction TIN3, PCIBR3 TIN2, PCIBR2 TIN1, PCIBR1, DREQ1 TIN0, PCIBR0, DMA_REQ0...
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0 Drive 0 when PORT x pin is general purpose output 1 Drive 1 when PORT x pin is general purpose output 15.3.2.1.2 7-Bit PODR_x Register The 7-bit PODR_DSPI register is the output data register for the PDSPIn port. 7-bit PODR_x register. Freescale Semiconductor Figure PODRx5 PODRx4 PODRx3 Description MCF548x Reference Manual, Rev.
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The 4-bit PODR_x registers are the output data registers for PDMAn (PODR_DMA) and PFECI2Cn (PODR_FECI2C). Figure 15-3 15-10 MBAR + 0xA0E (PODR_DSPI) Description PODRx4 PODRx3 MBAR + 0xA09 (PODR_PCIBG), 0xA0A (PODR_PCIBR) Description displays the 4-bit PODR_x registers. MCF548x Reference Manual, Rev. 3 PODRx2 PODRx1 PODRx0 Freescale Semiconductor...
Reserved, should be cleared 15.3.2.2 Port x Data Direction Registers (PDDR_x) The PDDR registers control the direction of the port x pin drivers when the pins are configured for general purpose I/O. Freescale Semiconductor PODRx3 MBAR + 0xA02 (PORT_DMA), 0xA08 (PORT_FECI2C) Description...
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The 7-bit PDDR_DSPI register sets the data direction for the PDSPIn port. PDDR_DSPI register. 15-12 DDx5 DDx4 DDx3 Table 15-9. 8-Bit PDDR_x Field Descriptions Description MCF548x Reference Manual, Rev. 3 Figure 15-7. The remaining Figure 15-8, Figure 15-9, DDx2 DDx1 DDx0 Figure 15-8 displays the 7-bit Freescale Semiconductor...
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0 PPCIBGn or PPCIBRn pin is configured as input 1 PPCIBGn or PPCIBRn pin is configured as output 15.3.2.2.4 4-Bit PDDR_x Registers The 4-bit PDDR_x registers are for data direction of PDMAn (PDDR_DMA) and (PDDR_FECI2C). Figure 15-10 Freescale Semiconductor DDDSP5 DDDSP4 DDDSPI3 MBAR + 0xA1E (PDDR_DSPI) Description DDx4...
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Port set data. 0 No effect 1 Corresponding PODR_x bit is set 15.3.2.3.2 7-Bit PPDSDR_x Register The 7-bit PPDSDR_x register is for pin data and set data for PDSPIn. PPDSDR_DSPI register. Freescale Semiconductor Figure 15-16. PPDx5 PPDx4 PPDx3 PSDx5 PSDx4...
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1 Corresponding PODR_DMA or PODR_FECI2C bit is set 15.3.2.3.5 FBCS Register (PPDSDR_FBCS) The 5-bit PPDSDR_FBCS register is for pin data and set data for PFBCSn. PPDSDR_FBCS register. Freescale Semiconductor Description Figure 15-15 displays the 4-bit PPDSDR_DMA and PPDSDR_FECI2C PPDx3 PSDx3 Description MCF548x Reference Manual, Rev.
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0 Corresponding PODR_DSPI bit is cleared 1 No effect 15.3.2.4.2 5-Bit PCLRR_x Registers The 5-bit PCLRR_x registers are the pin data and set data registers for PPCIBGn (PCLRR_PCIBG) and PPCIBRn (PCLRR_PCIBR). Figure 15-19 Freescale Semiconductor CLRx5 CLRx4 CLRx3 Description CLRDSP5 CLRDSP4...
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The 5-bit PCLRR_FBCS register is the clear output data register for PFBCSn. 5-bit PCLRR_FBCS register. 15-20 PCLRRx4 PCLRRx3 Description Figure 15-20 displays the 4-bit PCLRR_x registers. PCLRRx3 Description MCF548x Reference Manual, Rev. 3 PCLRRx2 PCLRRx1 PCLRRx0 PCLRRx2 PCLRRx1 PCLRRx0 Figure 15-21 displays the Freescale Semiconductor...
0 BE3/BWE3 pin configured for general purpose I/O (PFBCTL7) 1 BE3/BWE3 pin configured for FlexBus BE3/BWE3 or TSIZ1 function. The function chosen depends on the reset configuration. — Reserved, should be cleared. Freescale Semiconductor CLRFB5 CLRFB4 CLRFB3 MBAR + 0xA31 (PCLRR_FBCS)
11 = DREQ0 pin configured for DREQ0 function 15.3.2.8 FEC/I2C/IRQ Pin Assignment Register (PAR_FECI2CIRQ) The PAR_FECI2CIRQ register controls the functions of the FEC0, FEC1, I2C, and IRQ pins. The PAR_FECI2CIRQ register is read/write Freescale Semiconductor Table 15-25. PAR_FBCS Field Descriptions Description PAR_DACK0...
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11 E1MDC pin configured for FEC1 E1MDC function 5–4 — Reserved, should be cleared. 15-24 PAR_ PAR_ PAR_E1MDIO PAR_E1MDC E1MII MBAR + 0xA44 (PAR_FECI2CIRQ) Table 15-27. PAR_FEC/I2C/IRQ Field Descriptions MCF548x Reference Manual, Rev. 3 PAR_ Description Freescale Semiconductor PAR_ PAR_ PAR_ IRQ6 IRQ5...
PCIBG3 pin assignment. Configures the PCIBG3 pin for one of its primary functions or GPIO. PCIBG3 0X PCIBG3 pin configured for general purpose I/O (PPCIGNT3) 10 PCIBG3 pin configured for GP timer TOUT3 function 11 PCIBG3 pin configured for PCIBG3 function Freescale Semiconductor Description PAR_ PAR_ PCIBG4...
Every general purpose I/O pin is individually configurable as an input or an output via a data direction register (PDDR_x). Every GPIO port has an output data register (PODR_x) and a pin data register 15-32 Table 15-35. PAR_TIMER Descriptions Description NOTE MCF548x Reference Manual, Rev. 3 Chapter 2, “Signal Descriptions,” Freescale Semiconductor...
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I/O, regardless of whether the pins are inputs or outputs. Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing individual bits in the PODR_x register. The MCF548x GPIO module does not generate interrupt requests. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 15-33...
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Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” MCF548x JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. Freescale Semiconductor describes the MCF548x on-chip system SRAM describes data transfer operations, error conditions, and reset operations.
0x1_4008 Long Word 6143 0x1_5FFC Long Word 6144 0x1_6000 Long Word 6145 0x1_6004 Long Word 6146 0x1_6008 Long Word 8191 0x1_7FFC Linear Organization Freescale Semiconductor Byte Address 0x1_0000 0x1_0010 0x1_0020 Bank 0 0x1_7FF0 0x1_0004 0x1_0014 0x1_0024 Bank 1 0x1_7FF4 0x1_0008...
0 The four SRAM banks are not interleaved (linear). 1 The four SRAM banks are interleaved. SRAM bank # contains data for long word address modulo {bank #} 15–0 — Reserved. Should be cleared. Freescale Semiconductor Name Byte 0 MBAR + 0x1_FFC0 16-2. Description MCF548x Reference Manual, Rev.
4 * {field value} 32-bit transfers to/from bank 0 before it must wait for other masters to complete their transfers. If this field is programmed to “0” the master can “own” bank 0 for arbitrarily long transfers. 16-4 BANK3_TC BANK1_TC MBAR + 0x1_FFC4 16-3. Description MCF548x Reference Manual, Rev. 3 BANK2_TC BANK0_TC Freescale Semiconductor...
4 * {field value} 32-bit transfers from bank 0 before it must wait for other masters to complete their transfers. If this field is programmed to “0” the DMA read channel can “own” bank 0 for arbitrarily long transfers. Freescale Semiconductor BANK3_TC BANK1_TC...
If this field is programmed to “0” the DMA write channel can “own” bank 0 for arbitrarily long transfers. 16-6 BANK3_TC BANK1_TC MBAR + 0x1_FFCC Description MCF548x Reference Manual, Rev. 3 BANK2_TC BANK0_TC Freescale Semiconductor...
SEC can make at most 4 * {field value} 32-bit transfers to/from bank 0 before it must wait for other masters to complete their transfers. If this field is programmed to “0” the SEC can “own” bank 0 for arbitrarily long transfers. Freescale Semiconductor BANK3_TC BANK1_TC...
This section describes the external signals that are involved in data transfer operations. summarizes the MCF548x FlexBus signals. Signal Name Direction FBCS[5:0] AD[31:0] BE/BWE[3:0] TBST TSIZ[1:0] Freescale Semiconductor Address AD[31:0] Latch Logic Table 17-1. FlexBus Signal Summary Description General purpose chip-selects Address / Data bus...
32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] = 01), a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (TSIZ[1:0] = 01). 17-4 NOTE MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
TA input. If the external TA is used, the peripheral has total control on the number of wait states. External devices should only assert TA while the FBCSn signal to the external device is asserted. Freescale Semiconductor Table 17-2. Data Transfer Size TSIZ[1:0]...
AD[31:0] used for data. PCIAD[31:0] used for address PCIAD[31:0] used for PCI bus. AD[31:0] used for both address and data. MCF548x Reference Manual, Rev. 3 Section 17.5.2.3, Figure 17-6 for graphical connection. 17-3, Table 17-4, and Table 17-5 Freescale Semiconductor list the...
Reset clears each CSMRn[V]. At reset, no chip-select other than FBCS0 can be used until the CSMR0[V] is set. At which point FBCS[5:0] functions as configured. 0 chip-select invalid 1 chip-select valid Freescale Semiconductor 0x528 (CSMR3); 0x534 (CSMR4); 0xr540 (CSMR5) Table 17-8. CSMRn Field Descriptions Description ;...
11 Assert chip-select on fourth rising clock edge after address is asserted.(Reset FBCS0) 17-10 AD[1:0] MBAR + 0x508 (CSCR0); 0x514 (CSCR1); 0x520 (CSCR2); 0x52C (CSCR3); 0x538 (CSCR4); 0x544 (CSCR5) Table 17-9. CSCRn Field Descriptions Description MCF548x Reference Manual, Rev. 3 — ASET RDAH WRAH BEM BSTR BSTW Freescale Semiconductor...
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8-bit port is broken into four 8-bit reads. 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports and word reads from 8-bit ports. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
AD[31:24], starting with the MSB and going to the LSB. A longword transfer through a 32-bit port requires one transfer on each of the four byte lanes of the FlexBus. 17-12 Description MCF548x Reference Manual, Rev. 3 Section 17.5.2.3, Freescale Semiconductor...
FBCSn negates. For a read transfer, data is also returned at this cycle. External slave asserts TA at this clock edge. 3. Read data and TA are sampled on the third clock edge. TA can be negated after this edge and read data can then be tristated. Freescale Semiconductor BE/BWE0 BE/BWE1 BE/BWE2...
Address, data, and R/W go invalid off the rising edge of CLK at the end of S3, terminating the read or write cycle. 17-14 Figure 17-7. Wait States Table 17-11. Bus Cycle States Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
FBCSn timing when internal termination is used (CSCR[AA] = 1). The external and internal TA assert at the same time; however, TA is not driven externally for internally terminated bus cycles. Freescale Semiconductor NOTE 1. Decode address. 1. Select the appropriate slave device.
The MCF548x tristates AD[31:16] on the second clock and continues to drive address on AD[15:0] throughout the bus cycle. The external device returns the read data on AD[31:16] and may tristate the data line or continue to drive the data one clock after TA is sampled asserted. Freescale Semiconductor Figure 17-11.
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Figure 17-13. Single Word Write Transfer with Muxed 32-A / 16-D 17-18 A[31:24] D[15:8] A[23:16] D[7:0] ADDR[15:8] ADDR[7:0] or Non-Muxed 16-A / 16-D A[31:24] DATA[15:8] A[23:16] DATA[7:0] ADDR[15:8] ADDR[7:0] or Non-Muxed 16-A / 16-D MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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FBCSn, BE/BWEn Figure 17-14. Single Byte Read Transfer with Muxed 32-A / 8-D Figure 17-15 shows the similar configuration for a write transfer. The data is driven from the second clock on AD[31:24]. Freescale Semiconductor A[31:24] D[7:0] ADDR[23:16] ADDR[15:8] ADDR[7:0] or Non-Muxed 24-A / 8-D MCF548x Reference Manual, Rev.
Figure 17-18 Figure 17-19 Figure 17-11). This is the default case with no wait states. Freescale Semiconductor A[31:24] DATA[31:24] A[23:16] DATA[23:16]...
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TA is recognized as asserted. Figure 17-21 show a read and write cycle with one wait state. 17-22 ADDR[X:0] A[31:Y] DATA TSIZ[1:0] ADDR[X:0] A[31:Y] DATA TSIZ[1:0] MCF548x Reference Manual, Rev. 3 Figure 17-20 Freescale Semiconductor...
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The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip select basis. Each chip select can be programmed to assert one to four clocks after address latch enable (ALE) is asserted. two clocks of address setup. Freescale Semiconductor ADDR[X:0] A[31:Y] DATA...
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Figure 17-24 Figure 17-25 17-24 ADDR[X:0] A[31:Y] DATA TSIZ[1:0] ADDR[X:0] A[31:Y] TSIZ[1:0] show read and write bus cycles with two clocks of address hold. MCF548x Reference Manual, Rev. 3 DATA Freescale Semiconductor...
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AD[X:0] AD[31:Y] TSIZ[1:0] FBCSn, BE/BWEn Figure 17-25. Write Cycle with Two Clock Address Hold (No Wait States) Figure 17-26 shows a bus cycle that uses address setup, wait states, and address hold. Freescale Semiconductor ADDR[X:0] A[31:Y] DATA TSIZ[1:0] ADDR[X:0] A[31:Y]...
A[31:Y] TSIZ[1:0] Two Clock Hold (One Wait State) Transfer Size Burst-inhibited: number of transfers TSIZ[1:0] Burst enabled: number of beats 10 (word) 00 (longword) 11 (line) 00 (longword) 11 (line) 11 (line) MCF548x Reference Manual, Rev. 3 DATA Freescale Semiconductor...
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8-bit device programmed for burst enable. The transfer results in a 4-beat burst and the data is driven on AD[31:24]. Notice that the transfer size is driven at longword (2’b00) throughout the bus cycle. Freescale Semiconductor NOTE ADDR[23:0]...
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A[31:24] DATA TSIZ[1:0] FBCSn, BE/BWEn TBST Figure 17-29. Longword Read Burst-Inhibited from 8-Bit Port (No Wait States) 17-28 ADDR[23:0] DATA DATA DATA ADDR[23:0] A[31:24] A[31:24] DATA 01 01 MCF548x Reference Manual, Rev. 3 DATA DATA A[31:24] DATA DATA Freescale Semiconductor...
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AD[23:0] AD[31:24] A[31:24] TSIZ[1:0] FBCSn, BE/BWEn TBST Figure 17-31. Longword Read Burst from 8-Bit Port 4-2-2-2 (One Wait State) Freescale Semiconductor ADDR[23:0] A[31:24] A[31:24] DATA DATA 01 01 WS/SWS WS/SWS...
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Figure 17-33. Longword Read Burst from 8-Bit Port 4-1-1-1 (Address Setup and Hold) Figure 17-34 shows a write cycle with one clock of address setup and address hold. 17-30 WS/SWS WS/SWS ADDR[23:0] DATA DATA ADDR[23:0] DATA DATA DATA MCF548x Reference Manual, Rev. 3 WS/SWS DATA DATA DATA Freescale Semiconductor...
Figure 17-35. Example of a Misaligned Longword Transfer (32-Bit Port) If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. The example in Figure 17-36 word-sized and the transfer takes only two bus cycles. Freescale Semiconductor ADDR[23:0] DATA DATA DATA...
If it is required that the MCF548x handle a bus error differently, an interrupt handler can be invoked by asserting an interrupt to the core along with TA when the bus error occurs. 17-32 24 23 16 15 –– –– –– –– –– MCF548x Reference Manual, Rev. 3 A[2:0] Byte 0 — Freescale Semiconductor...
DDR SDRAM. 18.3.11 SDRAM Write Enable (SDWE) The SDRAM write enable (SDWE) is asserted to signify that a DRAM write cycle is underway. A read cycle is indicated by the negation of SDWE. Freescale Semiconductor Byte Lane SDDQS SDDQS3...
SDRAM’s data bus. For example, if 16-bit wide devices are used, then you must use two 16-bit devices connected as a 32-bit port. 18-4 NOTE MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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• x8 and x16 data width memory devices can be mixed (but not in the same space). • x32 data width memory devices cannot be mixed with any other width. Freescale Semiconductor Table 18-2. SDRAM Address Multiplexing Number Total SDCR...
There is a JEDEC standard for a 100-pin DDR DIMM with a 32-bit wide data bus. This DIMM standard was designed specifically to support 32-bit processors. The MCF548x can support current DIMM configurations up to 512 Mbytes. Figure shows a block diagram of the connections between the MCF548x and DDR SDRAM DIMMs. Freescale Semiconductor SDBA[1:0] SDCSn SDWE SD_CKE MCF548x Reference Manual, Rev.
The parallel termination at end of the signal line (close to the SDRAM). • 0.1 uF decoupling for every termination resistor pack. 18-8 SDWE SDCKE SDVDD MCF548x Reference Manual, Rev. 3 DDR SDRAM A[12:0] BA[1:0] DQ[31:0] S[1:0] CLK[1:0] CLK[1:0] DM[3:0] DQS[3:0] Freescale Semiconductor...
Row and Bank Active Read Write Precharge All Banks Load Mode Register Load Extended Mode Register CBR Auto Refresh Freescale Semiconductor 50 Ω 25 Ω Table 18-3 lists SDRAM commands supported by the memory Table 18-3. SDRAM Commands Symbol ACTV...
18-10 Table 18-3. SDRAM Commands (Continued) Symbol SREF H→L PDWN H→L H = High L = Low V = Valid X = Don’t care NOTE Management” for more information. MCF548x Reference Manual, Rev. 3 AP/C BA[1:0] Other A Freescale Semiconductor...
3. Write the desired mode register value to the SDMR[ADDR]. Don’t overwrite the SDMR[BA] values. 4. Set the SDMR[CMD] bit. 5. For DDR, repeat from step 2 for the extended mode register. 6. Clear the SDCR[MODE_EN] bit. Freescale Semiconductor NOTE NOTE MCF548x Reference Manual, Rev. 3 SDRAM Overview...
SDRAMs have a prescribed initialization sequence. The following sections detail the memory initialization steps for both SDR and DDR SDRAM. The sequence might change slightly from device-to-device. Refer to the device datasheet as the most relevant reference. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
7. Pause for the DLL lock time specified by the memory. 18-14 LEMR)” for more instruction on issuing an LEMR)” for instructions on issuing an LEMR MCF548x Reference Manual, Rev. 3 Section 18.5.1.5, “Load Section 18.5.1.5, “Load LEMR)” for more Freescale Semiconductor...
In the MCF548x, the internal data bus is 64 bits wide, while the SDRAM external interface bus is 32 bits wide. Therefore, each XLB data beat requires two memory data beats. The SDRAM controller manages the size translation (packing/unpacking) between 64- and 32-bit buses. Freescale Semiconductor LEMR)” for more instruction on issuing an MCF548x Reference Manual, Rev. 3 Functional Overview Section 18.5.1.5, “Load...
Controls the drive strength of SDDATA[31:0], SDDM[3:0], and SDQS[3:0]. See Table 18-8 Table 18-8. SDRAM Drive Strength Bit Encodings SB_x[1:0] 3.3V is for SDR mode, 2.5V is for DDR mode Freescale Semiconductor SB_E SB_C MBAR + 0x04 Table 18-7. SDRAMDS Field Descriptions...
1 Generate an LMR/LEMR command 0 Do not generate any command 15–0 — Reserved. Should be cleared. Freescale Semiconductor 18-10, is used to write to the mode and extended mode registers that Initialization” for more information on the initialization Uninitialized MBAR +0x0100 Table 18-10.
All other fields govern the relative timing from one command to another, they have minimum values but any larger value is also legal (but with decreased performance). Freescale Semiconductor Description / (SDCLK x 64)) - 1, rounded down to the next integer value.
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Note: CASL=2.5 is not supported for SDR. 18-22 SWT2RD Uninitialized REF2ACT Uninitialized MBAR + 0x0108 Table 18-12. SDCFG1 Field Descriptions Description /SDCLK + 1, suggested value = 0x3 , suggested value = 0x2 MCF548x Reference Manual, Rev. 3 RDLAT ACT2RW WTLAT Freescale Semiconductor...
The burst length (BL) field must be exact. All other fields govern the relative timing from one command to another, they have minimum values, but any larger value is also legal (but with decreased performance). All delays in this register are expressed in SDCLK. Freescale Semiconductor Description /SDCLK - 1 (Round up to nearest integer)
For this example, the SDRAM will be connected to SDCS0 with a base address of 0x0. All other chip selects are unused and do not need to be initialized. The CS0CFG should be programmed as shown in Figure 18-15. Freescale Semiconductor Parameter command (t ACTV...
The SDCR should be programmed as shown in the MODE_EN and IPALL bits are set to issue a PALL command to the SDRAM and enable writing of the mode register. Freescale Semiconductor Description 0x6 is the recommended value for DDR memory with a CASL of 2 Reserved.
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0 indicates that a buffered memory module is not being used. Reserved. Should be cleared. Do not initiate a REF command. Initiate a PALL command. Reserved. Should be cleared. MCF548x Reference Manual, Rev. 3 RCNT — BUFF — IREF IPALL Table 18-19. Table 18-2. Freescale Semiconductor —...
(hex) Field Setting (hex) Figure 18-20. SDRAM Mode/Extended Mode Register Settings (SDMR) This configuration results in a value of SDMR = 0x048D_0000, as described in Freescale Semiconductor Figure 18-19. This step enables the DDR memory’s DLL. OPTION 0100_0000_0000_0001 — 0000_0000_0000_0000 Table 18-20.
01 is the MUX setting for a 13 x 9 x 4 memory. See 0 sets the auto precharge control bit to A10. MCF548x Reference Manual, Rev. 3 RCNT BUFF — IREF IPALL Table 18-22. Table 18-2. Freescale Semiconductor —...
Table 18-23. SDCR + MODE_EN and IREF Field Descriptions Bits Name Setting MODE_EN Freescale Semiconductor Description Data and DQS lines are only driven for a write cycle. RCNT = (t / (SDCLK x 64)) - 1 = (7800ns/(8.3ns x 64)) - 1 = 13.62,...
MODE_EN 27–26 — 25–24 DRIVE 21–16 RCNT 001101 Freescale Semiconductor Description Sequential burst type. Burst length of eight. Reserved. Should be cleared. Initiate the LMR command. Reserved. Should be cleared. Figure 18-24. Along with the base settings for the SDCR —...
Reserved. Should be cleared. 0 indicates that a buffered memory module is not being used. Reserved. Should be cleared. Initiate a REF command. Do not initiate a PALL command. Reserved. Should be cleared. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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#0x008D0000, d0//Write LMR and clear reset DLL move.l d0, SDMR Enable Auto Refresh and Lock SDMR: move.l #0x710D0F00, d0//Enable auto refresh and clear MODE_EN move.l d0, SDCR Freescale Semiconductor MCF548x Reference Manual, Rev. 3 SDRAM Example 18-35...
19.1.3 Features The following PCI features are supported in the MCF548x: • Supports system clock: PCI clock frequency ratios 1:1, 2:1, and 4:1 • Uses external CLKIN as clock reference Freescale Semiconductor Arbiter PCI Controller Block Controller Configuration Configuration Interface...
The PCISERR signal, if enabled, is asserted active low when an address phase parity error is detected. 19.2.12 Stop (PCISTOP) The PCISTOP signal is asserted active low by the currently addressed target to indicate that it wishes to stop the current transaction. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 External Signal Description 19-3...
—Only PCI configuration cycles can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is currently a 0 or writing a 0 to any rwc bit has no effect. Figure 19-3. PCI Status/Command Register (PCISCR) Freescale Semiconductor Device ID Vendor ID MBAR + 0xB00 Table 19-3.
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Address and data stepping. Fixed to 0. This bit indicates that the PCI controller never uses address/data stepping. Initialization software should write a 0 to this bit location. 19-8 Table 19-4. PCISCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Cache line size [3:0] Specifies the cache line size in units of DWORDs. 19-10 Table 19-5. PCICCRIR Field Descriptions Description Lat Timer [2:0] Cache Line Size [7:4] MBAR + 0xB0C Table 19-6. PCICR1 Field Descriptions Description MCF548x Reference Manual, Rev. 3 Header Type Cache Line Size [3:0] Freescale Semiconductor...
IO or memory space. Fixed to 0. This bit indicates that BAR0 is for memory space. Configuration software should write a 0 to this bit location. 0 Memory 1 I/O Freescale Semiconductor BAR 0 MBAR + 0xB10 Table 19-7. PCIBAR0 Field Descriptions Description MCF548x Reference Manual, Rev.
Subsystem Vendor and Subsystem ID associated with the device. If used, software must write to these registers before any PCI bus master reads them. 19-12 MBAR + 0xB14 Table 19-8. PCIBAR1 Field Descriptions Description MCF548x Reference Manual, Rev. 3 PREF RANGE Freescale Semiconductor IO/M#...
General Control/Status Registers The general control/status registers primarily address the configurability of the XL bus initiator and target interfaces, though some also address global options which affect the multichannel DMA interface. These Freescale Semiconductor MBAR + 0xB3C Table 19-9. PCICR2 Field Descriptions Description MCF548x Reference Manual, Rev.
— Reserved, should be cleared. 18–16 CLKINReser This field is reserved. 15–14 — Reserved, should be cleared. 19-14 XLB2CLKIN — MBAR + 0xB60 Table 19-10. PCIGSCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Section 19.5.2, Reserved Uninitialized Freescale Semiconductor...
Enable 0 This bit enables a transaction in BAR0 space. If this bit is zero and a hit on MCF548 PCIBAR0 occurs, the target interface gasket will abort the PCI transaction. Freescale Semiconductor Description Base Address Translation 0 MBAR + 0xB64 Table 19-11.
Figure 19-14. Initiator Window 1 Base/Translation Address Register (PCIIW1BTAR) The field descriptions for this register are the same as for PCIIW0BTAR, except that they apply to Window 19-18 Description MBAR + 0xB74 MCF548x Reference Manual, Rev. 3 Window 1 Address Mask Freescale Semiconductor...
The field descriptions for this register are the same as for PCIIW0BTAR, except that they apply to Window 19.3.2.8 Initiator Window Configuration Register (PCIIWCR) Reset Reset Addr Figure 19-16. Initiator Window Configuration Register (PCIIWCR) Freescale Semiconductor MBAR + 0xB78 Window 0 Control Window 2 Control MBAR + 0xB80 MCF548x Reference Manual, Rev. 3...
Figure 19-17. Initiator Control Register (PCIICR) 19-20 Table 19-15. PCIIWCR Field Descriptions Description Table 19-57. If bit[3] is set to “1”, the value of these bits is meaningless. MBAR + 0xB84 MCF548x Reference Manual, Rev. 3 Maximum Retries Freescale Semiconductor...
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is currently a 0 or writing a 0 to any rwc bit has no effect. Figure 19-18. Initiator Status Register (PCIISR) Freescale Semiconductor Table 19-16. PCIICR Field Descriptions Description MBAR + 0xB88 MCF548x Reference Manual, Rev.
Reserved, should be cleared. 19-22 Table 19-17. PCIISR Field Descriptions Description Function Number MBAR + 0xBF8 Table 19-18. PCICAR Field Descriptions Description (Section 19.4.4.2, “Configuration MCF548x Reference Manual, Rev. 3 Bus Number DWORD Mechanism”). When disabled, a read or write Freescale Semiconductor...
Register addresses are relative to this offset. 19.3.3.1.1 Tx Packet Size Register (PCITPSR) Reset Reset Addr Figure 19-20. Tx Packet Size Register (PCITPSR) Freescale Semiconductor Description for more information. Packet_Size[15:2] MBAR + 0x8400 MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition bus.Section 19.4.4.2, “Configuration...
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PCITTCR[DI] bit is set. This register will not increment as the PCI packet proceeds. 19-24 Table 19-19. PCITPSR Field Descriptions Description Start_Add Start_Add MBAR + 0x8404 Table 19-20. PCITSAR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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— Reserved, should be cleared. Disable address incrementing. The user writes this register to disable PCI address incrementing between transactions. The default setting is 0, increment address by 4 (4 byte data bus). Freescale Semiconductor PCI_cmd Max_Beats MBAR + 0x8408 Table 19-21.
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Packets_Done status counter. 23–22 — Reserved, should be cleared. 19-26 MBAR + 0x840C Figure 19-23. Tx Enables Register (PCITER) Table 19-22. PCITER Field Descriptions Description Section 19.3.3.1.8, “Tx Status Register (PCITSR),” MCF548x Reference Manual, Rev. 3 for bus error Freescale Semiconductor...
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DMA or the processor core. 15–0 — Reserved, should be cleared. 19.3.3.1.5 Tx Next Address Register (PCITNAR) Reset Reset Addr Figure 19-24. Tx Next Address Register (PCITNAR) Freescale Semiconductor Description Next_Address Next_Address MBAR + 0x8410 MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition 19-27...
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Normal termination. This bit is set when any packet terminates normally. It is not set for abnormally terminated packets. An interrupt will be generated by this condition if the PCITER[NE] bit is set. This bit is cleared by writing ‘1’ to it. Freescale Semiconductor Table 19-25. PCITDCR Field Descriptions Description ×...
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‘1’ to it. 15–0 — Reserved, should be cleared. Registers MBAR + 0x8420 through MBAR + 0x843C are reserved for future use. Accesses to these registers will result in undefined behavior. 19-30 Description NOTE MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is currently a 0 or writing a 0 to any rwc bit has no effect. Figure 19-29. Tx FIFO Status Register (PCITFSR) Freescale Semiconductor FIFO_Data_Word FIFO_Data_Word MBAR + 0x8440 Table 19-27.
19.3.3.2 Comm Bus FIFO Receive Interface PCI Rx is controlled by 13 32-bit registers. These registers are located at an offset from MBAR. Register addresses are relative to this offset. Freescale Semiconductor MBAR + 0x8454 Table 19-32. PCITFWPR Field Descriptions Description MCF548x Reference Manual, Rev.
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Setting Max_Retries to 0x00 will not generate an interrupt but will permit re-arbitration of the PCI bus between each disconnect. 15–13 — Reserved, should be cleared. Freescale Semiconductor Table 19-34. PCIRSAR Field Descriptions Description PCI_cmd Max_Beats MBAR + 0x8488 Table 19-35.
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The user writes this register to disable PCI address incrementing between transactions. The default setting is 0, increment address by 4 (4 byte data bus). 19.3.3.2.4 Rx Enables Register (PCIRER) Reset Reset Addr Figure 19-37. Rx Enables Register (PCIRER) 19-38 Description MBAR + 0x848C MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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It may be desirable to mask CPU interrupts in the case that Multi-Channel DMA is controlling operation, but in such a case software should poll the status bits to prevent a possible lock-up condition. Freescale Semiconductor Table 19-36. PCIRER Field Descriptions Description Section 19.3.3.2.7, “Rx Status Register (PCIRSR),”...
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Start_Add value when Start_Add is reloaded. This register is intended to be accurate even if an abnormal PCI bus termination occurs. 19-40 Description Next_Address Next_Address MBAR + 0x8490 Table 19-37. PCIRNAR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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At any point in time the total number of bytes received can be calculated as: This assumes Packet_Size is the same for all restart sequences and the Packets_Done register has not been cleared. Freescale Semiconductor Bytes_Done Packets_Done MBAR + 0x8498 Table 19-38.
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The only recovery is to assert the reset controller bit, PCIRER[RC], and clear this flag by writing ‘1’ to it. 19-42 MBAR + 0x849C Figure 19-40. Rx Status Register (PCIRSR) Table 19-39. PCIRSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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FIFO. During normal operation the Multi-Channel DMA controller pops data here. The receive controller pushes data. Therefore, user programs should not write here. Only full 32-bit accesses are allowed. If all FIFO byte enables are not asserted when accessing this location, FIFO data will be corrupted. Freescale Semiconductor Description NOTE FIFO_Data_Word...
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The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the state of the FIFO. 19-44 MBAR + 0x84C4 Table 19-41. PCIRFSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Full Alarm Empty Freescale Semiconductor...
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RXW bit from generating an error. (To help with backward compatibility, this bit is asserted at reset.) UF_MASK Underflow mask. When this bit is set, the FIFO controller masks the Status Register’s UF bit from generating an error. Freescale Semiconductor Description FAE_ MASK MASK MBAR + 0x84C8 Table 19-42.
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FIFO for it to write a burst of Max_Beats * 4 bytes before it will request data from the PCI bus. For a Max_Beats value of 0(8 beats), Alarm should be programmed to 32 or greater. 19-46 Description MBAR + 0x84CC Table 19-43. PCIRFAR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Alarm Freescale Semiconductor...
PCI burst read transaction (2-beat). The signal PCIFRAME is driven low to initiate the transfer. Cycle 1 is the address phase with valid address information driven on the AD bus and a PCI Freescale Semiconductor Command Type Reserved...
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PCITRDY is negated, it is considered a target disconnect without a transfer. See the PCI specification for more details. 19-50 BYTE ENABLES (Wait) Data Phase 1 MCF548x Reference Manual, Rev. 3 Figure BYTE ENABLES (Wait) Data Phase 2 Freescale Semiconductor 19-47. A...
I/O write 0100 Reserved 0101 Reserved 0110 Memory-read 0111 Memory-write 1000 Reserved Freescale Semiconductor BYTE ENABLES Data Phase 1 Table 19-47. PCI Bus Commands MCF548x MCF548x Supports Initiator as Target The interrupt acknowledge command is a read (implicitly addressing an external interrupt controller). Only one device on the PCI bus should respond to the interrupt acknowledge command.
The memory write and invalidate functions the same as the memory write command. Cache line wrap is not implemented. MCF548x Reference Manual, Rev. 3 Definition — Section 19.4.1.5.4, “Address Decoding). Freescale Semiconductor...
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AD bus and the configuration command on the PCICXBE[3:0] bus. A Type 0 configuration transaction is indicated by setting AD[1:0] to 0b00 during the address phase. The bit pattern Freescale Semiconductor Table 19-48. PCI I/O Space Byte Decoding...
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If the bus number matches, it should claim and pass the configuration access onto 19-54 Target Configuration Doubleword Number 11 10 Function Number Doubleword Number in the Device’s Configuration Space 16 15 11 10 Device Number Function Number MCF548x Reference Manual, Rev. 3 Dword Number Dword Number Freescale Semiconductor...
There are three possible internal initiator sources: comm bus transmit, comm bus receive, or the XL bus (from the internal system arbiter). Custom interface logic arbitrates and provides multiplex selection control for these sources to the PCI controller. Freescale Semiconductor Device 0.1 Secondary Bridge Device 1.1...
Arbiter rx_req Initiator rx_gnt Section 19.5.2, “Address Maps,” MCF548x Reference Manual, Rev. 3 Request/Grant (to PCI Arbiter) Controller External PCI Bus Initiator Interface are primarily intended to be read or Accesses to this area are for examples on Freescale Semiconductor...
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After the XL bus write data is latched internally, the bus is available for subsequent transactions without having to wait for the write to the PCI target to complete. If a subsequent XL bus write MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 19-57...
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OP0 OP1 OP2 OP3 OP4 OP5 OP6 The byte lane translation will be similar for other types of transactions. However, the PCI address may be different as explained in Section 19.4.1.5, “Addressing.” Freescale Semiconductor Data Bus Byte Lanes — —...
19-50. It allows for 21 different devices. Device Number Decimal 0–9 MCF548x Reference Manual, Rev. 3 (PCIIWCR)”. Section 19.3.2.11, “Configuration Address Section 19.4.4.3, “Interrupt for more information. If 11 10 Function Number Dword 11 10 Function Number/Dword IDSEL AD31 Freescale Semiconductor Rsvd...
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Asserting IDSEL is the only way the MCF548x can clear its own status register (PCISCR) bits (read-write-clear). For Type 0 translations, the function number and Dword fields are copied without modification onto the AD[10:2] signals, and AD[1:0] are driven low during the address phase. Freescale Semiconductor Device Number Decimal NOTE MCF548x Reference Manual, Rev.
Target Base Address Translation Registers 0 and 1 allow the user to map PCI address hits on MCF548x PCI Base Address Registers to areas in the internal address space. All of these registers must be enabled for this interface to operate. Freescale Semiconductor PCIAD[15:0] Message...
The XL bus supports misaligned operations, however, it is strongly recommended that software attempt to transfer contiguous code and data where possible. Non-contiguous transfers degrade performance. PCI-to-XL bus transaction data translation is shown in Table 19-53 Table 19-54. MCF548x Reference Manual, Rev. 3 19-64 Freescale Semiconductor...
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0000 0000 Table 19-54. Non-Contiguous PCI to XL Bus Transfers (Requires Two XL Bus Accesses) PCI Bus BE[3: AD[2:0] 31:24 23:16 1010 1010 Freescale Semiconductor 15:8 A[29:31] 15:8 A[29:31] MCF548x Reference Manual, Rev. 3 Functional Description XL Bus Data Bus Byte Lanes...
PCI address at the beginning of each successive burst for packet transfers. If the Disable Increment bit is set, the PCI controller will present the same address during the address phase of each PCI transaction throughout the entire packet transmission. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 19-67...
(Packet_Size must be last) and not toggle the Master Enable bit. The Reset bit should remain negated. 19-68 Data Bus PCIAD [1:0] 31:24 23:16 15:8 MCF548x Reference Manual, Rev. 3 PCI Data Bus Data Bus [3:0] 31:24 23:16 15:8 0000 Freescale Semiconductor...
FIFO size(128 bytes) or else the controller’s request to the DMA may immediately deassert. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 19-69...
100-200 MHz for more information. For the comm bus Initiator interface, an Section 19.3.3.1, “Comm Bus FIFO Transmit Interface,” Table 19-57 MCF548x Reference Manual, Rev. 3 XL Bus Multiplier 200 MHz Section 19.3.2.10, shows how the PCI Controller accepts Freescale Semiconductor...
. The internal CPU writes the base address value to module base address register MBAR. MBAR holds the base address for the 256-Kbyte space allocated to internal registers. Freescale Semiconductor Section 19.3.2.6, “Initiator Window 1 Base/Translation Address Section 19.3.2.8, “Initiator Window Configuration Register...
MCF548x’s internal bus and request PCI bus access as the PCI Initiator. The PCI arbiter could see the PCI bus as busy (target read transaction in progress) and only a time-out would free the PCI bus. MCF548x Reference Manual, Rev. 3 19-72 Freescale Semiconductor...
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XL Bus Initiator Window configurations. Overlapping the inbound memory window (MCF548x Memory) and the outbound translation window is not supported and can cause unpredictable behavior. Figure 19-55 does not show the configuration mechanism. Freescale Semiconductor TBATR0 Address Translation Recommended...
Note that the default priority setting uses the programmed priority settings where the G2 Core is set to highest. If the Priority Register Enable is disabled for PCI (Master 3), the arbiter uses the hardware priority values. The PCI hardwired priority is 0, highest. See Freescale Semiconductor PCI Bus Configuration Access Section 20.3, “Register Definition,”...
The bus is then immediately available to the selected bus master if it should require the use of the bus (and no other higher-priority request is pending). The selected master can immediately initiate a transaction as long as the PCI bus is idle. It need not assert its REQ. Freescale Semiconductor INT REQ INT GNT...
0x0C00. Refer to for module offsets. 20.3.1 PCI Arbiter Control Register (PACR) R DS Reset Reset Addr Figure 20-2. PCI Arbiter Control Register (PACR) Freescale Semiconductor MBAR + 0xC00 MCF548x Reference Manual, Rev. 3 Register Definition EXTMINTEN INTMINTEN EXTMPRI INTMPRI...
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External master priority levels. Bit 1 controls the priority for the device using REQ[0] and GNT0 pins, bit 2 for REQ1 and GNT1, etc. 0 Low 1 High INTMPRI Internal master priority level. 0 Low 1 High 20-4 Table 20-2. PACR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
An external PCI master may target the MCF548x or external slaves. The request/grant handshake always precedes any PCI bus operation. The PCI arbiter must service access requests for an external master-to-external target transactions as well as external master-to-MCF548x transactions. Freescale Semiconductor MBAR + 0xC04 Table 20-3. PASR Field Descriptions Description MCF548x Reference Manual, Rev.
(including now device 1), the arbiter will assign GNT to device 1 since it has been the longest since device 1 has used the bus. (It has highest priority.) Once all requests are serviced, the priority resets to the initial state. MCF548x Reference Manual, Rev. 3 20-6 Freescale Semiconductor...
Three master devices are used to illustrate how an arbiter may alternate bus accesses. (Assume device 0, device 1, and device 2 are assigned the same priority group and no other masters are requesting use of the bus.) Freescale Semiconductor Device 0 (1/12)
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ADDR Access 0 Access 1 GRANT ACTIVE GRANT Figure 20-5. Alternating Priority with the bus parked with device 2 and both device 0 and device MCF548x Reference Manual, Rev. 3 DATA ADDR DATA Access 0 ACTIVE GRANT ACTIVE Freescale Semiconductor...
If a master does not initiate a transaction after its GNT has been asserted, but deasserts REQ before the 16 clock timer expires, the arbiter deasserts GNT and rearbitrates for the next transaction. The master is not Freescale Semiconductor DATA...
An alternate way to force the interrupt to a level low is to disable the interrupt enable that corresponds to the asserted status bit. The status bit, however, remains set. 20-10 (PCIGSCR)”). During the MCF548x system reset, this MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Buffer 0 • • Data • • Buffer 13 Data Buffer 14 Data Length Data Buffer 15 • Time Stamp • Data Length • • Data Time Stamp Data Length Time Stamp CAN Station n Freescale Semiconductor • • •...
FlexCAN waits for the completion of all internal activity like arbitration, matching, move-in, and move-out. When this happens, the following events occur: • The FlexCAN stops transmitting/receiving frames. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Introduction 21-3...
Because the module does not influence the CAN bus in this mode, the host device is capable of functioning like a monitor or for automatic bit-rate detection. 21-4 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
0xA028 0xA828 Interrupt mask register 0xA02C 0xA82C 0xA030 0xA830 Interrupt flag register Freescale Semiconductor “GPIO”) prior to configuring a FlexCAN channel. Map.” Out of the lower 128 bytes, only part is Table 21-1. FlexCAN Memory Map Byte0 Byte1 CANMCR CANCTRL...
MAXMB field, which should only be changed while the module is in freeze mode. R MDIS HALT Reset Addr Figure 21-4. FlexCAN Module Configuration Register (CANMCR) 21-6 Byte0 Byte1 Reserved NOTE SOFT SUPV MBAR + 0xA000 (CANMCR0); 0xA800 (CANMCR1) MCF548x Reference Manual, Rev. 3 Byte2 Byte3 MAXMB Freescale Semiconductor Access —...
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0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor privilege mode. 1 Registers with access controlled by the SUPV bit are restricted to supervisor mode. Freescale Semiconductor Table 21-2. CANMCR Field Descriptions Description Mode”...
R BOFF Reset Addr Figure 21-5. FlexCAN Control Register (CANCTRL) 21-8 Description Maximum MBs in Use = MAXMB + 1 SAMP BOFF MBAR + 0xA004 (CANCTRL0); 0xA804 (CANCTRL1) MCF548x Reference Manual, Rev. 3 PSEG1 PSEG2 TSYNC LBUF LOM PROPSEG Freescale Semiconductor...
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1 Three samples are used to determine the value of the received bit. The samples are taken at the normal sample point and at the two preceding periods of the S-clock; a majority rule is used. Freescale Semiconductor Table 21-3. CANCTRL Field Descriptions Description Section 21.4.9, “Bit...
When there is no message on the bus, it counts using the previously programmed baud rate. During freeze mode, the timer is not incremented. 21-10 Description Propagation segment time (PROPSEG + 1) time-quanta MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MBAR + 0xA010 (RXGMASK0); 0xA810 (RXGMASK1) Table 21-5. RXGMASK Field Descriptions Description MCF548x Reference Manual, Rev. 3 Extended ID Match 15 that have their – Freescale Semiconductor...
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FlexCAN Rx 15 Mask Register (RX15MASK) The RX15MASK register has the same structure as the Rx global mask register and is used to mask message buffer 15. Access to this register is unrestricted. Freescale Semiconductor Description MBAR + 0xA014 (RX14MASK0); (0xA814 (RX14MASK1) Figure 21-8.
If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset 21-14 MBAR + 0xA018 (RX15MASK0); 0xA818 (RX15MASK1) Table 21-7. RX15MASK Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Most bits in this register are read only, except for BOFFINT, WAKINT, and ERRINT, which are interrupt sources that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to “Interrupts.” Freescale Semiconductor MBAR + 0xA01C (ERRCNT0); 0xA81C (ERRCNT1) MCF548x Reference Manual, Rev. 3...
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Transmit error status flag. The TXWARN status flag reflects the status of the FlexCAN transmit error counter. 0 Transmit error counter < 96 1 TXErrCounter ≥ 96 21-16 IDLE TXRX MBAR + 0xA020 (ERRSTAT0); 0xA820 (ERRSTAT1) Table 21-8. ERRSTAT Field Descriptions Description MCF548x Reference Manual, Rev. 3 BOFF CONF Freescale Semiconductor...
The interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0 (IMASK_L). The register can be accessed by the master as a 16-bit register, or each byte can be accessed individually using an 8-bit (byte) access cycle. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
A standard frame is represented by the 11-bit standard identifier, and an extended frame is represented by the combined 29-bits of the standard identifier (11 bits) and the extended identifier (18 bits). Freescale Semiconductor Table 21-12. IFLAG Field Descriptions Description Table 21-15).
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21-15. See Figure MCF548x Reference Manual, Rev. 3 TIME STAMP Extended ID [17:0] Data Byte 2 Data Byte 3 Data Byte 6 Data Byte 7 Section 21.4, “Functional Overview” for 21-12). In reception, this field is written by Freescale Semiconductor...
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MB with a new receive frame. The CPU should not try to access the MB. Note that for transmit message buffers (see Freescale Semiconductor Description Rx Code AFTER Rx New Frame — MB does not participate in the matching process.
The data frame will be transmitted unconditionally once, and then the code will automatically return to 1010. The CPU can also write this code with the same effect. MCF548x Reference Manual, Rev. 3 Description Freescale Semiconductor...
CAN bus is sensed as free by the receiver or at the inter-frame space, and there is at least one MB ready for transmission. This internal arbitration process is intended to select the MB from which the next frame is transmitted. Freescale Semiconductor Control/Status Identifier...
ID value to the newly received one, and if a match occurs, the frame is transferred (move in) to the first (lowest entry) matching MB. The value of the free-running timer (which 21-24 NOTE Section 21.4.6.1, “Serial Message Buffers NOTE MCF548x Reference Manual, Rev. 3 (SMBs)” for more Freescale Semiconductor...
The match/arbitration processes are performed only during one period by the FlexCAN. Once a winner or match is determined, there is no re-evaluation whatsoever, in order to ensure that a receive frame is not Freescale Semiconductor (IFLAG)”), and not by the control/status word CODE field for Table 21-14.
MB with ID that may not be the lowest at the time, because a lower ID might be present in one of the MBs that it had already scanned before the deactivation. 21-26 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The remote frame is a message frame which is transmitted to request a data frame. The FlexCAN can be configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote frame and then wait for the responding data frame to be received. Freescale Semiconductor NOTE MCF548x Reference Manual, Rev. 3...
“time quantum” used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. A bit time is subdivided into three segments 21-28 (reference Figure 21-14 MCF548x Reference Manual, Rev. 3 Table 21-16): Freescale Semiconductor...
(IPT) equals three time quanta, otherwise it equals two time quanta. 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. Freescale Semiconductor Bit Rate -------------------------------------------------------------...
ACKERR. A transition to bus state error passive should be executed as described, while this device never enters the bus off state. 21-30 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The bus off and error interrupt mask bits are located in the CANCTRL register, and the wake-up interrupt mask bit is located in the CANMCR. Freescale Semiconductor for more information.
The ColdFire core accesses the SEC primarily through data packet descriptors using system memory for data storage. When an application requires cryptographic functions, it simply creates descriptors that Freescale Semiconductor NOTE MCF548x Reference Manual, Rev. 3...
2. Fetch context and other parameters as indicated in the data packet descriptor buffer and use these to program the EU. 3. Fetch data as indicated and place in either the EU input FIFO or the EU itself (as appropriate). Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Overview...
DES module in the recipient’s system. The same key is used, and the DES block manages the key processing internally so that the plaintext blocks are recovered. 22-4 Figure 22-2. DES is a symmetric algorithm, so MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
S-box contents are modified with every byte processed. The AFEU applies the input stream from and collects the output stream into 8-byte (64-bit) buffers, providing an interface consistent with other EUs on the SEC. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 22-5...
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MDEU module, and at the end, the hash value is read as the 160-bit output for SHA-160, 256-bit output for SHA-256, or 128-bit output for MD5. Plaintext blocks 512-bit 512-bit 512-bit block n block n-1 block 2 Freescale Semiconductor 256-bit constant SHA256 160-bit constant 512-bit block 1 SHA160 128-bit constant Figure 22-6. MDEU Hashing Process MCF548x Reference Manual, Rev.
EU Assignment Control Register High EU Assignment Control Register Low MCF548x Reference Manual, Rev. 3 Type — Resource Control Data Control Data Control — Crypto EU Crypto EU Crypto EU Crypto EU Crypto EU Page p. 22-11 p. 22-11 Freescale Semiconductor...
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AFRCR 0x28028 AFSR 0x28030 AFISR 0x28038 AFIMR Freescale Semiconductor Table 22-3. SEC Register Map (Continued) Name SEC Interrupt Mask Register High SEC Interrupt Mask Register Low SEC Interrupt Status Register High SEC Interrupt Status Register Low SEC Interrupt Control Register High...
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MCF548x Reference Manual, Rev. 3 Page p. 22-34 p. 22-35 p. 22-37 p. 22-39 p. 22-41 p. 22-41 p. 22-43 p. 22-44 p. 22-46 p. 22-47 p. 22-48 p. 22-49 p. 22-50 p. 22-51 p. 22-53 p. 22-54 Freescale Semiconductor...
These registers are used to make a static assignment of a EU to a particular crypto-channel. When assigned in this fashion, the EU is inaccessible to any other crypto-channel. The EU assignment control registers (EUACRH and EUACRL) are used to make, and therefore will reflect, only static assignments. Freescale Semiconductor NOTE MCF548x Reference Manual, Rev. 3 Controller Table 22-14.
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Table 22-5. Channel Assignment Value Channel No channel assigned Channel 0 Channel 1 MCF548x Reference Manual, Rev. 3 — — 1111 0000 — AFEU 1111 0000 — AESU 1111 0000 — 0000 Table 22-5. to any of the fields in the EUACR Freescale Semiconductor...
1111 Field — Reset 1111 Addr Figure 22-10. EU Assignment Status Register Low (EUASRL) Freescale Semiconductor Channel Reserved EU is not statically assigned to any channel and is not allowed to be dynamically assigned to a channel. Figure 22-9 Figure...
SICR. 22-14 Description Figure 22-11 Figure 22-12 shows the bit positions of each potential interrupt NOTE MCF548x Reference Manual, Rev. 3 Table 22-5. Figure 22-12 show the bit positions Freescale Semiconductor...
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Assignment Error bit. This bit indicates that a static assignment of a EU was attempted on a EU which is currently in use. 0 No error detected. 1 EU Assignment Error detected. 26–0 — Reserved, should be cleared. Freescale Semiconductor AERR 0x0000 — 0x0000 Description MCF548x Reference Manual, Rev. 3 —...
SEC. The value of this register is always 0x0900_0000. 22-16 0x0000 — — 0x0000 Description exact cause of the error. Figure 22-13, contains a 32-bit value that uniquely identifies MCF548x Reference Manual, Rev. 3 — AFEU — — Freescale Semiconductor MDEU...
0000 - No Channel is currently in use. 0001 - Channel 0 is in use. 0010 - Channel 1 is in use. Reserved Address Address MBAR + 0x 21038 Table 22-10. MEAR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
• Fetch register (FRn) • Data packet descriptor buffer (CFBUFn) 22.7.1.1 Crypto-Channel Configuration Registers (CCCRn) This register contains five operational bits permitting configuration of the crypto-channel as shown in Figure 22-16. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Channels 22-19...
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NULL upon completion of the descriptor currently being processed will that descriptor be considered the end of the chain. 22-20 BURST_SIZE MBAR + 0x2200C (CCCR0), 0x2300C (CCCR1) Table 22-11. CCCRn Field Descriptions Description MCF548x Reference Manual, Rev. 3 CDIE RST Table 22-12 Freescale Semiconductor...
22.7.1.2 Crypto-Channel Pointer Status Registers (CCPSRHn and CCPSRLn) These registers contain status fields and counters which provide the user with status information regarding the channel’s actual processing of a given descriptor. Freescale Semiconductor Description Table 22-12. Burst Size Definition Value Number of Longwords in Burst MCF548x Reference Manual, Rev.
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Figure 22-18. Crypto-Channel Pointer Status Register Low (CCPSRLn) 22-22 MBAR + 0x22010 (CCPSRH0), 0x23010 (CCPSRH1) Table 22-13. CCPSRHn Field Descriptions Description STAT DERR SERR EUERR MBAR + 0x22014 (CCPSRL0), 0x23014 (CCPSRL1) MCF548x Reference Manual, Rev. 3 STATE Table 22-15 shows the PAIR_PTR Freescale Semiconductor...
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0 The assigned primary EU reset done signal is inactive. 1 The assigned primary EU reset done signal is active indicating its reset sequence has completed and it is ready to accept data. Freescale Semiconductor Table 22-14. CCPSRLn Field Descriptions Description MCF548x Reference Manual, Rev.
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Static assignment error. Either the EU is statically assigned to a different channel or the dynamic assignment request cannot be filled because all suitable EUs are otherwise statically assigned. 0 No error. 1 Static assignment error. 22-24 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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0x5 Processing length/pointer pair 5. 0x6 Processing length/pointer pair 6. 0x7 Complete (or not yet begun) processing of header and length/pointer pairs 0x8-0xFF Reserved Table 22-15 shows the values of crypto-channel states. Freescale Semiconductor Description Table 22-15. STATE Field Values Value Crypto-Channel State 0x00...
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Write primary EU go multi EU out 0x2E Write secondary EU go multi EU out 0x2F Write primary EU go multi EU in 0x30 Write secondary EU go multi EU in 0x31 Write datasize primary delay Reserved MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
In summary, a channel is initiated by a direct write to the FR, and the channel always checks the FR before determining if it has truly reached the end of a chain. Freescale Semiconductor 22-19, contains the address of the data packet descriptor which the...
This status register, shown in Figure signals. The AFEU status register is read-only. Writing to this location will result in address error being reflected in the AFEU interrupt status register. Freescale Semiconductor MBAR + 0x 21018 Table 22-18. AFRCR Field Descriptions Description 22-22, contains 6 bits which reflect the state of the AFEU internal MCF548x Reference Manual, Rev.
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0 AFEU is not signaling error 1 AFEU is signaling error 22-30 MBAR + 0x28028 Figure 22-22. AFEU Status Register (AFSR) Table 22-19. AFSR Field Descriptions Description (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
1 Mode error Address error. An illegal read or write address was detected within the AFEU address space. 0 No error detected 1 Address error Freescale Semiconductor Description (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and Figure 22-23, tracks the state of possible errors, if those errors are not MBAR + 0x28030 Table 22-20.
Interrupt status register • Interrupt mask register 22.9.2 DEU Reset Control Register (DRCR) This register, shown in Figure bits. 22-34 Description 22-25, allows 3 levels reset of just DEU, as defined by three self-clearing MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
This status register, displayed in signals. The DEU status register is read-only. Writing to this location will result in address error being reflected in the DEU interrupt status register. Freescale Semiconductor MBAR + 0x2A018 Table 22-22. DRCR Field Descriptions Description...
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0 DEU is not signaling error 1 DEU is signaling error 22-36 MBAR + 0x2A028 Figure 22-26. DEU Status Register (DSR) Table 22-23. DSR Field Descriptions Description (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
1 Mode error Address error. An illegal read or write address was detected within the DEU address space. 0 No error detected 1 Address error Freescale Semiconductor Description (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and Figure 22-27, tracks the state of possible errors, if those errors MBAR + 0x2A030 Table 22-24.
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Data Size Error (DSE): A value was written to the DEU data size register that is not a multiple of 64 bits. 0 No error detected 1 Data size error 15-0 — Reserved 22-38 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Note: When operating as a master, the implements flow-control, and FIFO size is not a limit to data input. When operated as a target, the cannot accept FIFO inputs larger than 512 bytes without overflowing. Freescale Semiconductor (DISR)”), if the corresponding bit in this register is set, AFEU 0x2A038 Table 22-25.
The device drivers and the on-chip controller will abstract register level access from the user. The MDEU contains the following registers: • Reset control register • Status register • Interrupt status register • Interrupt control register 22-40 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
This status register, as seen in signals. The MDEU status register is read-only. Writing to this location will result in an address error being reflected in the MDEU interrupt status register. Freescale Semiconductor MBAR + 0x2C018 Table 22-26. MDEURCR Field Descriptions...
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0 MDEU is not signaling done 1 MDEU is signaling done 22-42 MBAR + 0x2C028 Table 22-27. MDSR Field Descriptions Description (Section 22.6.4.4, “SEC Interrupt Status Registers SISRL)”). (Section 22.6.4.4, “SEC Interrupt Status Registers SISRL)”). MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
0 No overflow detected 1 Input FIFO has overflowed Note: When operating as a master, the implements flow-control, and FIFO size is not a limit to data input. Freescale Semiconductor Description MBAR + 0x 21038 Table 22-28. MDISR Field Descriptions Description MCF548x Reference Manual, Rev.
RNG interrupt mask register. The definition of each bit in the interrupt status register is shown in Figure 22-35. R ME Reset Reset Addr Figure 22-35. RNG Interrupt Status Register (RNGISR) 22-48 Table 22-31. RNGSR Field Descriptions Description (Section 22.6.4.4, “SEC Interrupt Status Registers (SISRH and MBAR + 0x2E030 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
• Interrupt control register 22.12.2 AESU Reset Control Register (AESRCR) This register allows three levels reset of just AESU, as defined by the three self-clearing bits. 22-50 Table 22-33. RNGIMR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The AESU status register is a read-only register that reflects the state of six status outputs. Writing to this location will result in an address error being reflected in the AESU interrupt status register. Freescale Semiconductor Advanced Encryption Standard Execution Units (AESU) MBAR + 0x32018 Table 22-34.
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(SISRH and 0 AESU is not signaling error 1 AESU is signaling error 22-52 MBAR + 0x32028 Table 22-35. AESSR Field Descriptions Description (Section 22.6.4.4, “SEC Interrupt Status Registers SISRL)”). MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
1 Reserved or invalid mode selected Address Error. An illegal read or write address was detected within the AESU address space. 0 No error detected 1 Address error Freescale Semiconductor Advanced Encryption Standard Execution Units (AESU) Description (Section 22.6.4.4, “SEC Interrupt Status Registers SISRL)”).
The AESU interrupt mask register, shown in given error, if the corresponding bit in this register is set, then the error is ignored; no error interrupt occurs 22-54 Description Figure 22-39, controls the result of detected errors. For a MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Output FIFO Underflow. The AESU Output FIFO has been read while empty. 0 Output FIFO underflow error enabled 1 Output FIFO underflow error disabled 24–21 — Reserved Freescale Semiconductor Advanced Encryption Standard Execution Units (AESU) MBAR 0x32038 Table 22-37. AESIMR Field Descriptions Description MCF548x Reference Manual, Rev. 3...
32 Kbytes. The data pointer refers to the address of the data which the SEC fetches. Data in this case is broadly interpreted to mean keys, context, additional pointers, or the actual plaintext to be permuted. 22-56 Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Field PEUSEL Field SMODE Addr Table 22-38 defines the header bits. Freescale Semiconductor Descriptor Header +0x04 Data Field Length 1 +0x08 Data Field Pointer 1 +0x0C Data Field Length 2...
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Table 22-38. Header Bit Definitions Description Section 22.14, “ EU Specific Data Packet Section 22.14, “ EU Specific Data Packet lists the valid types of descriptors. MCF548x Reference Manual, Rev. 3 Descriptors” for descriptions of the Descriptors” for descriptions of the Freescale Semiconductor...
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1100 hmac_snoop_aesu_ctr 1101 non_hmac_snoop_aesu_ctr 1110 hmac_snoop_afeu_ key_in 1111 hmac_snoop_afeu_ctx_in Freescale Semiconductor Description Formats” for more information on the data length and pointer pairs Table 22-39. Descriptor Types AESU CTR nonsnoooping Common, nonsnooping,, non-AFEU Snooping, HMAC, non-AFEU Snooping, non-HMAC, non-AFEU Non-snooping, non HMAC, AESU, expanded key out...
The data pointer field contains the address, in global memory, of the first byte of the data packet for either read or write back. Transfers from the bus with the pointer address set to zero will be skipped. MCF548x Reference Manual, Rev. 3 DATA LENGTH Description Freescale Semiconductor...
It is possible to insert a descriptor into an existing chain; however, great care must be taken when doing so. Figure 22-45 shows a conceptual chain, or ‘linked list’ of descriptors. Freescale Semiconductor Section 22.13.2, “Descriptor Descriptor Pointer + 0x3C Figure 22-44. Next Descriptor Pointer Field...
Bytes to be written (should be equal to length of data in) Address where final data is written Number of bytes of IV to be written to memory (optional) MCF548x Reference Manual, Rev. 3 L/P 6 L/P 7 Description Freescale Semiconductor...
Data In Pointer LEN_5 Data Out Length PTR_5 Data Out Pointer LEN_6 IV Out Length Freescale Semiconductor Value/Type Address where IV is to be written (optional) NULL NULL NOTE Table 22-46 shows the format for a TYPE 0001 data packet Table 22-46.
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Bytes to be written (should be equal to length of data in) Address where final data is written NULL NULL NULL NULL shows the format for a TYPE 0001 data packet descriptor that TYPE 0001 NULL MCF548x Reference Manual, Rev. 3 Description Description Description Freescale Semiconductor...
22.14.1 AFEU Mode Options and Data Packet Descriptors The AFEU implements an acceleration of a stream cipher compatible with RC4. There are several different usage modes available. Field Reset Table 22-49 describes AFEU mode option fields. Freescale Semiconductor Description NULL NULL NULL NULL NULL...
Number of bytes of data after ciphering Pointer to location where cipher output is to be written Number of bytes in context (259 bytes) Location where AFEU context output is to be written MCF548x Reference Manual, Rev. 3 Description Freescale Semiconductor...
AFEU and perform the initial context-permutation. Table 22-52. First Descriptor for a Statically Assigned AFEU Using a Key Field Name Header 0x1000_0050 LEN_1 Length (not used) Freescale Semiconductor Value/Type NULL NULL Value/Type Don’t permute, context from FIFO, and dump context (TYPE 0101)
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Don’t permute; context from FIFO (TYPE 0101) NULL NULL Number of bytes in context (259 bytes) Address of context to be loaded into AFEU NULL NULL NULL NULL NULL NULL NULL NULL NULL MCF548x Reference Manual, Rev. 3 Description Description Freescale Semiconductor...
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Value/Type Header 0x1030_0050 LEN_1 Length (not used) PTR_1 Pointer (not used) LEN_2 IV Length PTR_2 IV Pointer Freescale Semiconductor Value/Type NULL Value/Type Don’t permute, context in AFEU (TYPE 0101) NULL NULL NULL NULL NULL NULL Number of bytes of data to be ciphered.
Pointer to location where cipher output is to be written Number of bytes in context (259 bytes) Address where AFEU context output is to be written NULL NULL — 0000_0000 PMODE Field in DPD Header Figure 22-47. DEU Mode Options Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Header Value 0x20500010 0x20400010 0x20700010 0x20600010 0x20100010 0x20000010 Freescale Semiconductor Value/Type Header common to several descriptors (TYPE 0001) NULL NULL Number of bytes of IV to be written (always 8) (not used in ECB mode) Pointer to context to be written into DEU (not used in ECB mode) Number of bytes in Key (8 for SDES;...
Address of data to be ciphered Bytes of output data (should be equal to length of data in) Address to write output data NULL NULL NULL NULL Single DES Single DES MCF548x Reference Manual, Rev. 3 Encrypt Decrypt Description Table 22-59. Encrypt Decrypt Freescale Semiconductor...
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Table 22-62. Typical Header Values for Middle Static DEU Descriptor Format Header Value 0x20500010 0x20400010 0x20700010 Freescale Semiconductor Triple DES Triple DES Single DES Single DES Triple DES Triple DES...
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Number of bytes of output IV to be written (always 8) (optional) Address where output IV is to be written (optional) NULL NULL Single DES Single DES Triple DES MCF548x Reference Manual, Rev. 3 Decrypt Encrypt Decrypt Encrypt Decrypt Description Table 22-63. Encrypt Decrypt Encrypt Freescale Semiconductor...
1 Initialize the selected algorithm’s starting registers HMAC HMAC enable. Identifies the hash operation to execute: 0 Perform standard hash 1 Perform HMAC operation. This requires a key and key length information. Freescale Semiconductor Triple DES Single DES Single DES Triple DES...
(the exact number of bytes used depends on the security protocol) of the HMAC generated by the SEC into the packet header 22-78 Description Continue Initialize MCF548x Reference Manual, Rev. 3 HMAC Freescale Semiconductor...
0x31E00010 0x31C00010 22.14.3.3 Statically Assigned MDEU Table 22-69 shows the first descriptor for a statically assigned MDEU. Freescale Semiconductor Value/Type Header common to several descriptors (TYPE 0001) NULL NULL Number of bytes of IV to be written (optional) (40 bytes)
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Number of bytes in intermediate hash output (16, 20, or 32 bytes) Pointer to location where intermediate hash output is to be written NULL NULL Algorithm HMAC SHA256 SHA256 Description Header common to several descriptors (TYPE 0001) NULL NULL MCF548x Reference Manual, Rev. 3 Table 22-69. Freescale Semiconductor...
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PTR_2 IV Pointer LEN_3 Key Length Freescale Semiconductor Number of bytes in intermediate hash input (16, 20, or 32 bytes) Pointer to location of intermediate hash input Number of bytes of key (only used for HMAC mode) Pointer to key (only used for HMAC mode)
Number of bytes of data after hashing (16, 20, or 32 bytes) Pointer to location where hash output is to be written NULL NULL Algorithm HMAC SHA256 SHA256 NOTE Table 22-75. RNG Descriptor Format RNG descriptor (TYPE 0001) NULL NULL MCF548x Reference Manual, Rev. 3 Description Description Freescale Semiconductor...
1 Extended Cipher Mode. Indicates AES-Counter Mode with CBC-MAC (AES-CCM) is in use. Note: CM must be set to 00 when Extend Cipher Mode is set, otherwise an error will be generated. — Reserved, should be cleared. Freescale Semiconductor Description NULL NULL NULL...
Address of data to be ciphered Bytes of output data (should be equal to length of data in) Address to write output data Number of bytes of output IV to be written (56 bytes) (optional) MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
LEN_5 Data Out Length PTR_5 Data Out Pointer LEN_6 IV Out Length PTR_6 IV Out Pointer LEN_7 MAC Out Length Freescale Semiconductor Address where output IV is to be written (optional) NULL NULL Header Value Mode 0x6030010 0x60200010 0x6010010 0x60000010...
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Address of data to be ciphered Bytes of output data (should be equal to length of data in) Address to write output data NULL NULL NULL NULL MCF548x Reference Manual, Rev. 3 Description Table 22-79. Encrypt Decrypt Encrypt Decrypt — Description Table Freescale Semiconductor 22-81.
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Next Descriptor Pointer Pointer to next data packet descriptor Table 22-84 lists several different descriptors that use the middle descriptor format shown in Table 22-84. Typical Header Values for Using Final Static AESU Descriptor Format Freescale Semiconductor Header Value Mode 0x6030010...
Address to write output data Number of bytes of output IV to be written (24 or 32 bytes) Address where output IV is to be written NULL NULL MCF548x Reference Manual, Rev. 3 Decrypt — AES-CCM processing Description Freescale Semiconductor generic...
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Data In Length PTR_4 Data In Pointer LEN_5 Data Out Length PTR_5 Data Out Pointer Freescale Semiconductor Length 16 bytes This is the session specific IV parameter 16 bytes These 16 bytes are loaded with zeroes to serve as a placeholder...
Compared to the MAC tag to determine if the frame passes its integrity check. 8 bytes If the MAC is larger than 16 bytes, this is the continuation of the decrypted MAC. MCF548x Reference Manual, Rev. 3 Description Description Description Freescale Semiconductor...
(IV). The number of bytes to be ciphered and starting address will be an offset of the number of bytes being HMAC’d. The data to be decrypted and HMAC’d is only brought in the SEC a single time, with the Freescale Semiconductor NOTE...
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Number of bytes HMAC output (16, 20 or 32 bytes) Address where hash output is to be written Single DES Decrypt Single DES Decrypt Single DES Decrypt Triple DES Decrypt Triple DES Decrypt Triple DES Decrypt MCF548x Reference Manual, Rev. 3 Description Algorithm HMAC SHA256 SHA256 Freescale Semiconductor...
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SEC to the packet as the authentication trailer. Common practice in IPSec ESP with TDES-CBC is to use the last 8 bytes of the ciphertext as the IV for the next packet. If this is the case, software should Freescale Semiconductor Single DES...
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Single DES Encrypt Single DES Encrypt Triple DES Encrypt Triple DES Encrypt Triple DES Encrypt Single DES Encrypt Single DES Encrypt Single DES Encrypt Triple DES Encrypt MCF548x Reference Manual, Rev. 3 Description Algorithm HMAC SHA256 SHA256 SHA256 SHA256 Freescale Semiconductor...
As the decryption/encryption continues, the output data fills the DEU/AEU output FIFO, and this data is written back to system memory as needed. Because it has been told to expect more data (continue on), the descriptor must not attempt to output the HMAC. Freescale Semiconductor Triple DES Encrypt...
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Decrypt Single DES Encrypt Triple DES Decrypt Triple DES Encrypt Triple DES Decrypt Triple DES Encrypt Triple DES Decrypt Triple DES Encrypt Single DES Decrypt MCF548x Reference Manual, Rev. 3 Description Algorithm HMAC SHA256 SHA256 SHA256 SHA256 SHA256 Freescale Semiconductor...
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0x60939A20 0x60839822 0x60939820 0x60A39922 0x60B39920 0x60A39A22 0x60B39A20 0x60A39822 0x60B39820 0x60E39922 0x60E39920 0x60E39A22 0x60E39A20 0x60E39822 0x60E39820 Freescale Semiconductor Single DES Encrypt Single DES Decrypt Single DES Encrypt Single DES Decrypt Single DES Encrypt Triple DES Decrypt Triple DES Encrypt Triple DES...
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Bytes of output data (should be equal to length of data in) Address where output data is to be written NULL NULL Single DES Decrypt Single DES Encrypt Single DES Decrypt MCF548x Reference Manual, Rev. 3 Description Algorithm HMAC SHA256 SHA256 Freescale Semiconductor...
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AESU/HMAC multi-function descriptor header values. Table 22-102. Typical Header Values for Middle Static Multi-Function AESU Descriptors Header Value 0x60838122 0x60938120 0x60838222 0x60938220 0x60838022 0x60938020 0x60A38122 0x60B38120 Freescale Semiconductor Single DES Encrypt Single DES Decrypt Single DES Encrypt Triple DES Decrypt Triple DES Encrypt...
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SHA256 Encrypt SHA256 Decrypt Encrypt Decrypt Encrypt Value/Type Header common to several descriptors (TYPE 0010) NULL NULL Number of bytes to be HMAC’d Address of data to be HMAC’d NULL NULL MCF548x Reference Manual, Rev. 3 HMAC Description Freescale Semiconductor...
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0x20338D20 0x20238E22 0x20338E20 0x20238C22 0x20338C20 0x20638D22 0x20738D20 Freescale Semiconductor Value/Type NULL NULL Bytes of input data Address of ciphertext to be decrypted Bytes of output data (should be equal to length of data in) Address where output data is to be written...
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IV Out Pointer LEN_7 MAC Out Length PTR_7 MAC Out Pointer PTR_NEXT Next Descriptor Pointer Pointer to next data packet descriptor Freescale Semiconductor Value/Type Header common to several descriptors (TYPE 0001) NULL NULL NULL NULL Number of bytes of HMAC key...
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Number of bytes of data to be ciphered Pointer to data to perform cipher upon Number of bytes of data after ciphering Pointer to location where cipher output is to be written NULL NULL NULL NULL NOTE MCF548x Reference Manual, Rev. 3 Description Freescale Semiconductor...
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The descriptor header does not designate a secondary EU, so the setting of the snoop type bit is ignored. Table 22-110. Inbound TLS Descriptor Two Format Field Name Header Table 22-111 LEN_1 Length (not used) Freescale Semiconductor Value/Type Perform permute (TYPE 0101) NULL NULL NULL NULL Number of bytes in key (5–16 bytes)
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Pointer to data to perform hash upon NULL NULL Number of bytes of data after hashing (16, 20, or 32) Pointer to location where hash output is to be written NULL NULL Algorithm HMAC SHA256 MCF548x Reference Manual, Rev. 3 Description Freescale Semiconductor...
JTAG Test data output / BDM Development serial output Table 23-2 summarizes the pin function selected depending MCF548x Reference Manual, Rev. 3 Chapter 8, “Debug Support.”) Table 23-1. Reset State Pull up — — — Active — Active — Active — Active Hi-Z / 0 — Freescale Semiconductor...
The TDI pin is the LSB-first data and instruction input. TDI is sampled on the rising edge of TCK. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. Freescale Semiconductor Table 23-2. Pin Function Selected MTMOD0 = 0...
TCK. The MSB of the IR is the bit closest to the TDI pin, and the LSB is the bit closest to the TDO pin. 23.3.2.2 IDCODE Register The IDCODE is a read-only register; its value is chip dependent. For more information, see Section 23.4.3.2, “IDCODE Instruction.” 23-4 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
MCF5485 0x0800c01d MCF5484 0x0800d01d MCF5483 0x0800e01d MCF5482 0x0800f01d MCF5481 0x0801001d MCF5480 0x0801101d 23.3.2.3 Bypass Register The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS instruction is selected. 23.3.2.4 JTAG_CFM_CLKDIV Register The JTAG_CFM_CLKDIV register is a 7-bit clock divider for the CFM that is used with the LOCKOUT_RECOVERY instruction.
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As Figure 23-3 shows, holding TMS at logic 1 while clocking TCK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. 23-6 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
However, since there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Initialization/Application Information...
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MII (Media Independent Interface) and 7-wire serial interfaces. It also provides describes operation and the programming model. Freescale Semiconductor provides an overview of the multichannel DMA controller contains a detailed description of the communications...
TaskBAR Read Arbiter Priority Task Decode (PTD) Debug Unit System Bus Interface IP Bus Freescale Semiconductor Comm Bus Read Engine Arbitration Write Arbiter Data In SRAM Interface Line Buffers 32 Kbyte XL Bus...
Support for up to 32 separate DMA initiators at a time • Simultaneous 32-bit reads and writes for many sources and targets • Checksum generation • Endian conversion • Chaining/scatter-gather capability • Support for packet-based I/O protocols 24-2 Model.” MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Data Routing Descriptors (DRD) and Loop Control Descriptors (LCD). The pointers in the task table define the beginning and end of each task descriptor table; see Task descriptor tables must be aligned to a longword (32 bit) boundary. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 External Signals for more information.
Each of these memory regions may exist in any addressable storage, such as internal system SRAM or external memory (internal system SRAM is recommended). Figure 24-2 illustrates the memory regions that are programmer maintained. MCF548x Reference Manual, Rev. 3 24-4 Freescale Semiconductor...
Reset Addr Bits Name 31–0 Descriptor Descriptor pointer. Pointer to the address of the DMA descriptor that is currently executing. Pointer Freescale Semiconductor Task Base Address Uninitialized Task Base Address Uninitialized MBAR + 0x8000 Table 24-2. TaskBAR Field Descriptions Description...
DRD to obtain the initiator number. These bits are cleared by system reset. These bits can be written by the programmer when the HLDINITNUM bit is set or being set and the task is not enabled. Freescale Semiconductor Table 24-8. DIMR Field Descriptions Description...
24.3.3.14 Debug Control (DBGCTL) Reset Comparator 1 Type Comparator 2 Type AND/ Reset Addr Figure 24-17. Debug Control Register (DBGCTL) 24-16 Comparator Value Comparator Value MBAR + 0x8070 Description Block Tasks[15:0] MBAR + 0x8078 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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1 type bits. These bits are set to 000 at reset signifying an uninitialized state. Table 24-14. Comparator 1 Type Bit Encoding Freescale Semiconductor Description for the bit encodings. for the bit encodings...
PTDDBG[15:0] reflects the state of the V bit (initiator is valid) in each of the Task Control Registers (TCRs). hold PTDDBG[15:0] reflects the state of the HLD bit in the priority registers for the corresponding task. Freescale Semiconductor Description PTDDBG[31:16] PTDDBG[15:0] MBAR + 0x8080 Description MCF548x Reference Manual, Rev.
SRAM, external memory, or comm bus peripherals. This register can be read or written at any time. The reset state of this register is set to all zeros. 24-20 Description Name Byte0 Byte1 Reserved Reserved MCF548x Reference Manual, Rev. 3 Byte2 Byte3 Access EREQBAR0 EREQMASK0 EREQCTRL0 EREQBAR1 EREQMASK1 EREQCTRL1 Freescale Semiconductor...
(DACK) signals. This register can be read or written at any time. The reset state of this register is set to all zeros. Reset Reset Addr Figure 24-22. External Request Control Register (EREQCTRL) Freescale Semiconductor Base Address MBAR + 0x0D00 (EREQBAR0); 0x0D10 (EREQBAR1) Address Mask MBAR + 0x0D04 (EREQMASK0); 0x0D14 (EREQMASK1) MBAR + 0x0D08 (EREQCTRL0); 0x0D18 (EREQCTRL1) MCF548x Reference Manual, Rev.
DMA supports 16 simultaneously enabled tasks (one task per channel). By dynamically swapping task pointers in the task table, an unlimited number of tasks can be supported. 24-22 Table 24-19. EREQCTRL Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
A coprocessor initiator could indicate the completion of some algorithmic processing, whereupon data could be read from the coprocessor. See the description of the Initiator Mux Control Register for a more complete description of available initiators. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Functional Description...
It can be used while transferring I/O data and also to perform logical operations that allow for descision making within task code. The operation codes for the execution units are stored in the 24-24 NOTE MCF548x Reference Manual, Rev. 3 Section 24.1.2.2, “Address and Freescale Semiconductor...
Ethernet module is such an example. For these cases, it is most efficient to use the CRC in the communication module. The DMA’s checksum engine is targeted toward computing higher-level protocol checksums, such as those at the TCP or IP layers. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Functional Description...
XL read/write requests and the DMA is reading from an address that is already buffered in the read queue. If the RL bit is not asserted for the task, the SP bit has no effect. 24-26 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
2. PTD Control register - The PTD control register defines global operation options of the DMA, those which apply to all tasks. This will typically only be set during initialization. 3. DMA Interrupt Mask register Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Programming Model...
24-23. Control bits 7 through 0 are for precise increment, save all registers, integer mode, speculative prefetch, read line, and combine writes. 24-28 Figure 24-23, should reside at the address specified by TaskBAR. MCF548x Reference Manual, Rev. 3 Section 24.3.1, Freescale Semiconductor...
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Save all internal registers 0 Save only those internal registers currently used when doing a context save 1 Save all internal registers when doing a context save — Reserved Freescale Semiconductor Task Descriptor Start Pointer Task Descriptor End Pointer Variable Table Pointer Status...
DMA request is asserted on the rising edge of clock 2 after the falling edge of DREQ. When the DMA transfer completes, the active high internal acknowledge is asserted (clock 4). This causes the external 24-30 Function MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
DREQ (during clock 7) causes the assertion of the internal request of the following rising clock edge (clock 8). Note that DACK is not deasserted until the new internal request asserts. DREQ Internal DMA Request Internal DMA Acknowledge DACK Freescale Semiconductor Figure 24-26. Pipelined External Requests MCF548x Reference Manual, Rev. 3 Timing Diagrams 24-31...
These diagrams are more detailed than earlier diagrams but should still be considered a conceptual illustration of the actual hardware implementations. Freescale Semiconductor cAcknowledge[7:0] Fixed TimerChannel[0]...
Details are given regarding register mapping, programming notes, bit definitions, and operating modes. 25.2.1 Timer Module Register Map Table 25-2 shows the register mapping of the timer module. Freescale Semiconductor Table 25-1. Comm Timers External Clock Timer Channel External Signal TIN0 TIN1...
25.2.2.2 Comm Timer Configuration Register (CTCRn)—Variable Timer Channel This register provides programming options for each variable timer channel. These channels can also be programmed as a baud clock generator or initiator. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition...
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Counter reference value. These 24 bits define the period of the timer i.e.: 0004 written into these bits signifies that the period is 4 timer clock cycles long. The counter reference value is set to 0xFF_FFFF at reset. 25-6 NOTE Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
At the rising edge of the clock in cycle 9 the cAcknowledge signal is asserted for the second time, and the percent counter begins to count again. At the rising edge of the clock in cycle 10 the cAcknowledge signal Freescale Semiconductor MCF548x Reference Manual, Rev. 3...
PSCnRXD are the receiver serial data inputs for the PSC modules. When the PSC clock is stopped for power-down mode, any transition on the signals restarts them. 26-2 Section 26.3.3.5, “Command Register (PSCCRn),” MCF548x Reference Manual, Rev. 3 for information Freescale Semiconductor...
0x8700 0x8800 0x8900 0x8604 0x8704 0x8804 0x8904 0x8608 0x8708 0x8808 0x8908 Freescale Semiconductor (PSCCRn),” for information about how to program this Table 26-1. PSC Signal Properties Modem8 AC97 Modem16 Bit clock Sync — Serial transmit data Serial receive data —...
Even parity Force parity Low parity No parity Multidrop mode Data character MCF548x Reference Manual, Rev. 3 command for the channel was issued. See Parity Type Parity Type (PT= 0) (PT= 1) Odd parity High parity Address character Freescale Semiconductor...
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1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears PSCOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are completely sent, including the programmed number of stop bits. Freescale Semiconductor TXRTS TXCTS...
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SIR mode, this bit becomes asserted only when the transmitter is enabled. On the contrary, in modem mode and MIR and FIR IrDA mode, this bit becomes asserted even if the transmitter is disabled. Freescale Semiconductor Table 26-5. PSCSRn Field Descriptions Description MCF548x Reference Manual, Rev.
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TxFIFO, they are transmitted. This command has no effect in modem, MIR, and FIR mode. 26-12 Table 26-7. PSCCRn Field Descriptions Description MISC Field (This field selects a single command.) MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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(data with EOF mark) in the current frame. — Reserved, do not use. Freescale Semiconductor Description TXC Field (This field selects a single command) MCF548x Reference Manual, Rev. 3...
Section 26.3.3.22, “Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn)” for more information. 26-14 Description RXC Field (This field selects a single command) Figure 26-11 shows the registers for AC97 mode. NOTE MCF548x Reference Manual, Rev. 3 Figure 26-10 shows the Freescale Semiconductor...
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#0 (TAG slot) are 20 bits. Timeslot #0 data is only 16 bits. The SORF bit indicates the start of a frame 26-16 RB[19:4] TB[19:4] Modem 8, SIR, MIR, and FIR Modes Description Description Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Reserved, should be cleared. Current state of PSCnCTS port. This input is double latched. 0 The current state of the PSCnCTS input port is low. 1 The current state of the PSCnCTS input port is high. Freescale Semiconductor Description D_CTS D_CTS Table 26-11.
If the corresponding bit in the PSCIMR is zero, the state of the bit in the PSCISR has no effect on the interrupt output. The PSCIMR does not mask the reading of the PSCISR. Freescale Semiconductor Table 26-13. PSCISRn Field Descriptions Descriptions MCF548x Reference Manual, Rev.
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— Reserved, should be cleared. 26-20 RXRDY_FU TXRDY DEOF ERR RXRDY_FU TXRDY DB RXRDY_FU TXRDY DB RXRDY_FU TXRDY DEOF ERR Table 26-14. PSCIMRn Field Descriptions Description Table MCF548x Reference Manual, Rev. 3 26-13. Freescale Semiconductor Mode MIR / Modem UART...
1 Usual operation In UART and IrDA modes this bit is reserved. In AC97 and modem modes, this bit signifies test usage. Toggle by frame sync. Freescale Semiconductor CT[15:8] Table 26-15. PSCCTURn Field Descriptions Description Table 26-16. PSCCTLRn Field Descriptions Description Table 26-17.
Reserved, should be cleared. 2–0 PSC/IrDA operation mode. When the operating mode change occurs, all receiver, transmitter, and error statuses are reset and the receiver and transmitter are disabled. Freescale Semiconductor Table 26-20. PSCSICRn Field Descriptions Descriptions SeeTable 26-21., “SIM[2:0] Table 26-21. SIM[2:0]...
1 If the transmitter becomes idle state, the transmitter starts to send one SIP pulse. This bit keeps high until the transmitter finishes sending a SIP and becomes low automatically when the transmitter finishes sending a SIP. 26-24 Table 26-22. PSCIRCR1n Field Descriptions Description Table 26-23. PSCIRCR2n Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
IRCR2 is high. This value should be set so that system clock period * IRSTIM = 1.6 µs The default value is 54 (decimal) and this is for the 33-MHz bus clock. 26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn) This register sets the baud rate in MIR mode. Freescale Semiconductor Descriptions Table 26-24. PSCIRSDRn Field Descriptions Descriptions MCF548x Reference Manual, Rev.
Reserved, should be cleared. 8–0 Number of bytes in the FIFO 26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn) These registers provide access to the internal Rx and Tx FIFOs. Freescale Semiconductor Table 26-27. PSCIRFDRn Field Descriptions Description bit_clk ----------------------------- -...
MBAR + 0x8664 (PSCRFSR0); 0x8764 (PSCRFSR1); 0x8864 (PSCRFSR2); 0x8964 (PSCRFSR3) Addr and MBAR + 0x8684 (PSCTFSR0); 0x8784 (PSCTFSR1); 0x8884 (PSCTFSR2); 0x8984 (PSCTFSR3) Figure 26-20. RxFIFO (PSCRFSR) and TxFIFO (PSCTFSR) Status Register 26-28 DATA DATA MCF548x Reference Manual, Rev. 3 (PSCTBn)”, for more ALARM EMT Freescale Semiconductor...
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FIFO to clear this alarm. This alarm will only be set while in frame mode. 0 No complete frames exist in the FIFO. 1 One or more complete frames exist in the FIFO. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
This register applies to all modes. 26-30 Description Section 26.3.3.25, “Rx and Tx FIFO Alarm Register (PSCRFARn, Section 26.3.3.25, “Rx and Tx FIFO Alarm Register (PSCRFARn, Figure 26-21, and the fields are further defined in the field MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Illegal pointer mask. When this bit is set, the FIFO controller masks the status register’s IP bit from generating an error. FAE_MSK Frame accept error mask. When this bit is set, the FIFO controller masks the status register’s FAE bit from generating an error. Freescale Semiconductor FAE_ CNTR Description MCF548x Reference Manual, Rev.
The read pointer is a FIFO-maintained pointer that points to the next FIFO location to be read. The physical address of this FIFO location is actually the combination of the read pointer and the FIFO base, which is 26-32 Description Description MCF548x Reference Manual, Rev. 3 ALARM Freescale Semiconductor...
The LRFP updates on FIFO read data accesses to a frame boundary. The LRFP can be read and written for debug purposes. For the frame retransmit function, the LRFP indicates which point to begin retransmission of the data frame. The LRFP carries validity information, however, Freescale Semiconductor Description Description MCF548x Reference Manual, Rev.
PSCnRTS is asserted by writing to the PSCOPSET register. The PSCnCTS input is used to control the transmitter. When PSCnCTS is negated, to start new serial transmission is disabled until the PSCnCTS is asserted again. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3 Functional Description...
The character is interpreted as an address character if the 26-36 Write Write Write Start Break Enable Figure 26-29. Modem Control and Receiver MCF548x Reference Manual, Rev. 3 Break Write Write Disable Break Read Read Read Status Status Status Read Read Read Data Data Data Freescale Semiconductor...
One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 26.4.3 Modem8 Mode Figure 26-30 shows an example waveform in 8-bit modem mode. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 26-37...
In AC97 mode, the PSCBCLK is the bit clock input and, different from 8/16 bit modem mode, the PSCnRTS is the frame sync output. PSC_BIT_CLK Figure 26-33. An Example Connection to AC97 CODEC Freescale Semiconductor D12 D11 D10 D9 D8 D7...
Description CODEC ready Slot #1 data valid Slot #2 data valid Slot #3 data valid Slot #4 data valid 18:12 Control register number 19:4 Control register read data 19:0 PCM record data left 19:0 PCM record data right Freescale Semiconductor...
Binary Data 1/4 of the bit width The packet format is similar to HDLC packet format 01111110 01111110 Freescale Semiconductor PSCFSYNC PSCBCLK Figure 26-34. AC97 Cold and Warm Reset is an example of data stream of UART and SIR. Data Bits (8-bit) 3/16 of the bit width or 1.6 µs...
Figure 26-38. Serial Interaction Pulse (SIP) Figure 26-39. Data Format in FIR Mode Figure 26-40. FIR Mode Packet Format DATA Table 26-38. MCF548x Reference Manual, Rev. 3 Bit Pair 4 PPM Data 1000 0100 0010 0001 Freescale Semiconductor Eqn. 26-3 Eqn. 26-4...
FIFO is completely full, a new character is held in the Rx shift register until space is available. However, if a second new character is received, contents of the character in the Rx shift register is lost. The FIFOs Freescale Semiconductor Table 26-38. Chip Patterns for FIR Fields...
The requestor to the Multichannel DMA to filling the TX FIFO becomes active if the amount of data in the FIFO is less then 16 data. The requester became inactive if less than 20 (5 × 4) bytes space in the FIFO. Freescale Semiconductor NOTE Figure 26-41.
CPU-to-receiver communications continue normally in this mode. While in this mode, the RxD input data 26-46 PSCnRXD disabled PSCnTXD Automatic echo disabled PSCnRXD PSCnTXD Local loop back disabled PSCnRXD disabled PSCnTXD Remote loop back MCF548x Reference Manual, Rev. 3 Figure 26-42. These modes Freescale Semiconductor...
Writing the RESET TRANSMITTER command to the command control register PSCCR resets the transmitter. 26.5.2.4 CRSES Writing the RESET ERROR STATUS command to the command control register PSCCR resets the error status held in the status register PSCSR. Freescale Semiconductor Table 26-39. Reset Summary Priority Source High...
There is one or more data in the RxFIFO The number in the RxFIFO is more than the threshold TXRDY The number in the TxFIFO is less than the threshold MCF548x Reference Manual, Rev. 3 Description certain time. Freescale Semiconductor...
Granularity is 4 byte Not EOF Enable frame mode Granularity is 16 byte Bit is always 0. Enable transmitter Enable receiver Meaning MSB first modem8 mode Reset all error status Not EOF Enable frame mode Granularity is 4 byte Freescale Semiconductor...
Table 26-43. A Sample Initialization Sequence for AC97 Mode Step Register Value PSCSICR PSCCR PSCIMR 0300 PSCRFCR PSCTFCR Freescale Semiconductor Details WRITE TAG=00 FRMEN=1 GR[2:0]=100 ALARM[8:0]=0F0 Request is asserted if # of data >= 240 ALARM[8:0]=0F0 Request is asserted if # of empty >= 240 TC=01...
Disable state change of PSCnCTS RxRTS=0 Receiver has no effect on PSCnRTS RxIRQ=0 Receiver interrupt is from RxRDY (one byte) ERR=1 (fixed) Block error mode PM[1:0]=10, PMT=0 No parity BC[1:0]=11 8 bit MCF548x Reference Manual, Rev. 3 Meaning Meaning Freescale Semiconductor...
MHz x 16). Table 26-45. A Sample Initialization Sequence for MIR Mode Step Register Value PSCSICR PSCIRMFD PSCCR Freescale Semiconductor Details CM[1:0]=00 Normal mode (not test mode) TxRTS=0 PSCnRTS is not controlled by transmitter TxCTS=0 PSCnCTS does not control transmitter...
Request is asserted if # of empty >= 240 TC=01 Enable transmitter RC=00 receiver remains at disabled state. Details SIM[2:0]=110 FIR mode F_FDIV[3:0]=0111 Frequency divide ratio is 8. So f(PSCBCLK) should be 64 MHz. MCF548x Reference Manual, Rev. 3 Meaning Meaning Freescale Semiconductor...
PSCnRXD, the receiver decodes the input and stores the data in the FIFO. 26.7.3.1 MIR Mode After initialization, writing data to the transmit buffer and enabling the transmitter sends data via the PSCnTXD port. The STA, CRC (option), and STO are automatically added. Freescale Semiconductor Details MISC=010 Reset receiver and RxFIFO...
PA, STA, and STO, and these flags are not written into the FIFO. After receiving enough data, PSC asserts request/interrupt to prompt the processor to read the received data. MCF548x Reference Manual, Rev. 3 26-56 Freescale Semiconductor...
— Attempt to transmit with an empty Tx FIFO (TFUF) — Rx FIFO is not empty (RFDF) — Frame received while Rx FIFO is full (RFOF) • Modified SPI transfer formats for communication with slower peripheral devices Freescale Semiconductor MCF548x Reference Manual, Rev. 3 27-1...
DSPISCK signal and the DSPICS0/SS signal are configured as inputs and provided by a bus master. 27-2 CommBus RX FIFO Data Data Shift Register Figure 27-1. DSPI with Queues and DMA MCF548x Reference Manual, Rev. 3 DSPI DSPISOUT DSPISIN DSPISCK DSPICSn/SS/PCSS Freescale Semiconductor...
When the DSPI is in master mode and DMCR[PCSSE] is set, the PCSS provides the appropriate timing for the decoding of the DSPICS[0,2,3] signals that prevents glitches from occurring. This signal is not used in slave mode. Freescale Semiconductor Table 27-1. Signal Properties Function...
Modified timing format enable. Enables a modified transfer format to be used. See “Modified SPI Transfer Format (MTFE = 1, CPHA = 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled Freescale Semiconductor FRZ MTFE PCSSE ROOE SMPL_PT MBAR + 0x8A00 Table 27-3.
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10 2 system clocks between DSPISCK edge and DSPISIN sample 11 Reserved 27-6 Description Section 27.7.6.6, “Receive FIFO Overflow Interrupt Operation” for details. Operation” for details. Figure 27-17 shows where the master can sample the DSPISIN pin. MCF548x Reference Manual, Rev. 3 (PCSS)” for more information. Freescale Semiconductor...
In master mode, the DCTAR registers define combinations of transfer attributes such as transfer size, clock phase and polarity, data bit ordering, baud rate, and various delays. When the DSPI is thus configured as Freescale Semiconductor Description Transfers” for details on the operation of this bit.
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11 7 clock DSPICS to DSPISCK delay prescaler 27-8 CPOL CPHA LSBFE PCSSCK Table 27-5. DCTAR Field Descriptions Description Table 27-6 lists the transfer sizes. Section 27.7.4.5, “Continuous Selection MCF548x Reference Manual, Rev. 3 PASC Format,” switching between Freescale Semiconductor...
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The after DSPISCK delay is the delay between the last edge of DSPISCK and the negation of DSPICS. multiple of the system clock period, and it is computed according to the following equation: Section 27.7.3.3, “After DSPISCK Delay Freescale Semiconductor Description × ×...
‘1’ to it. Writing a ‘0’ to a flag bit has no effect. R TCF TXRXS EOQF TFUF Reset TXCTR Reset Addr Freescale Semiconductor PCS to DSPISCK CSSCK / ASC / DT Delay Scaler Value Setting 1110 1111 Table 27-8. DSPI Baud Rate Scaler...
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Rx FIFO is empty. 0 Rx FIFO is empty 1 Rx FIFO is not empty — Reserved, should be cleared. 27-12 Table 27-9. DSR Field Descriptions Description Transfers” for information on how what causes this MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
R TCFE EOQFE TFUFE Reset Reset Addr Figure 27-6. DSPI DMA/Interrupt Request Select Register (DIRSR) Freescale Semiconductor Table 27-9. DSR Field Descriptions (Continued) Description Section 27.7.2.4, “Tx FIFO Buffering Mechanism” for more details. Values are the TFFFE TFFFS MBAR + 0x8A30 MCF548x Reference Manual, Rev.
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RFDFE bit in the DIRSR register is set, this bit selects between generating an interrupt request or a DMA request. 0 RFDF flag generates interrupt requests 1 RFDF flag generates DMA requests 15–0 — Reserved, should be cleared. 27-14 DIRSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSR is set. 0 The SPI data is not the last data to transfer 1 The SPI data is the last data to transfer Freescale Semiconductor Section 27.7.2.4, “Tx FIFO Buffering SPI Command Field...
Received data. The RXDATA field contains the SPI data from the Rx FIFO entry pointed to by the receive next data pointer. 27-16 Description Section 27.7.2.5, “Rx FIFO Buffering RXDATA MBAR + 0x8A38 Figure 27-8. DSPI Rx FIFO Register (DRFR) Table 27-11. DRFR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Mechanism” Freescale Semiconductor...
The DRFDR0 – DRFDR3 registers provide visibility into the Rx FIFO for debugging purposes. Each register is an entry in the Rx FIFO. The DRFDR registers are read-only. Reading the DRFDR_x registers does not alter the state of the Rx FIFO. Freescale Semiconductor TXCMD 0000_0000_0000_0000 TXDATA MBAR + 0x8A3C–8A48...
27-18 RXDATA MBAR + 0x8A7C–8A88 Table 27-13. DRFDR_x Field Descriptions Description (DCTARn)” for information on the fields of the DCTAR registers. illustrates how master and slave data is exchanged. MCF548x Reference Manual, Rev. 3 Section 27.6.3, “DSPI Clock Freescale Semiconductor...
DSR[TXRXS] bit is cleared in this state. In the running state, serial transfers take place. The DSR[TXRXS] bit is set in the running state. mechanism. The transitions are described in Power-On-Reset Figure 27-12. DSPI Start and Stop State Diagram Freescale Semiconductor DSPISIN SOUT DSPISOUT DSPISCK DSPICSn Figure 27-11.
• Debug mode is selected and the FRZ bit is set • HALT bit is set Section 27.7.2.4, “Tx FIFO Buffering Mechanism.” The interrupt and DMA request conditions are Requests.” MCF548x Reference Manual, Rev. 3 Mechanism” and (DTFR)” for details on the SPI Freescale Semiconductor...
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI Tx FIFO is empty, the Tx FIFO underflow flag (DSR[FUF]) is set. See Request” for details. Freescale Semiconductor Request” for details. Section 27.7.6.4, “Transmit FIFO Underflow Interrupt MCF548x Reference Manual, Rev.
For the MCF548x, the clock rate is 100 MHz. System Clock Figure 27-13. Communications Clock Prescalers and Scalers 27-22 Figure 27-13 shows conceptually how the DSPISCK signal is Prescaler Scaler MCF548x Reference Manual, Rev. 3 DSPISCK Freescale Semiconductor...
The delay after transfer is the length of time between negation of the DSPICSn signal for a frame and the assertion of the DSPICSn signal for the next frame. See transfer. The PDT and DT fields in the DCTARn registers select the delay after transfer by the formula below: Freescale Semiconductor DSPISCK baud rate PBR × BR Scaler...
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Prescaler Fsys Delay before Transfer 100 MHz delay. pasc Prescaler Fsys Delay after Transfer 100 MHz NOTE MCF548x Reference Manual, Rev. 3 Eqn. 27-7 Delay after Transfer 0.98 ms PASC Eqn. 27-8 Eqn. 27-9 70.0 ns 70.0 ns Freescale Semiconductor...
In this format, the master and slave sample their DSPISIN pins on the odd-numbered DSPISCK edges and change the data on their DSPISOUT pins on the even-numbered DSPISCK edges. Freescale Semiconductor 0)” and Section 27.7.4.4, “Modified SPI Transfer Format (MTFE = Section 27.7.4.1, “Classic SPI Transfer Format (CPHA =...
Figure 27-17 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is illustrated. The delayed master sample points are indicated with a lighter shaded arrow. Freescale Semiconductor Bit 6 Bit 5 Bit 4...
DSPISCK edge. The slave samples the last bit on the last edge of the DSPISCK. The master samples the last slave DSPISOUT bit one-half DSPISCK cycle after the last edge of DSPISCK. No clock edge will 27-28 System Clock System Clock MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
When the CONT bit = 1 and the DSPICSn signal for the next transfer is the same as for the current transfer, the DSPICSn signal remains asserted for the duration of the two transfers. The delay between transfers Freescale Semiconductor (MTFE = 1, CPHA = 1, Fsck = Fsys/4) MCF548x Reference Manual, Rev.
DMA request. Table 27-21. Interrupt and DMA Request Conditions End of Queue TX FIFO Fill Transfer Complete TX FIFO Underflow RX FIFO Drain RX FIFO Overflow Freescale Semiconductor Figure 27-22 Transfer 1 Table 27-21 lists the six conditions. Condition Flag EOQF...
If the ROOE bit is set, the incoming data is shifted into the shift register. If the ROOE bit is negated, the incoming data is ignored. MCF548x Reference Manual, Rev. 3 27-32 Freescale Semiconductor...
PBR and the baud rate scaler BR in the DCTARn registers. The values calculated assume a 100 MHz system frequency. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Initialization and Application Information...
FIFO entries along with the FIFO counter. The Tx FIFO is chosen for the illustration, but the concepts carry over to the Rx FIFO. See “Tx FIFO Buffering Mechanism” and the FIFO operation. Freescale Semiconductor Table 27-23. Delay Values Delay Prescaler Values 20.0 ns 60.0 ns 40.0 ns...
C module is shown in Registers and ColdFire Interface C Frequency Divider Register Register (I2FDR) Clock Control Input Sync Freescale Semiconductor C™ module, including I C protocol, clock synchronization, and I Figure 28-1. Address Decode C Control C Status Register (I2CR)
Open-drain signal that serves as the data input/output for the I 28-2 C signals Table 28-1. I C Signal Summary Description C interface. Either it is driven by the I MCF548x Reference Manual, Rev. 3 C module when the bus C is in the slave mode. C interface. Freescale Semiconductor...
Slave address. Contains the specific slave address to be used by the I2C module. Note: This is not the address sent on the bus during the address transfer. — Reserved, should be cleared. Freescale Semiconductor Table 28-2. I C Memory Map Name...
— Reserved, should be cleared. 28.3.2.4 I C Status Register (I2SR) This I2SR contains bits that indicate transaction direction and status. Freescale Semiconductor C module and the I C interrupt. It also contains bits that govern operation IIEN MSTA TXAK MBAR + 0x8F08 Figure 28-4.
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1 No acknowledge signal was detected at the ninth clock. 28-6 IAAS MBAR + 0x8F0C Figure 28-5. I C Status Register (I2SR) Table 28-6. I2SR Field Descriptions Description C module is a slave and has an address match. MCF548x Reference Manual, Rev. 3 RXAK Freescale Semiconductor...
BNBE bit in order to clear the interrupt condition, otherwise it will persist until another IIC transaction is initiated. The MCF548x contains one I C module. The interrupt control register is common to I Freescale Semiconductor DATA MBAR + 0x8F10 Figure 28-6. I C Data I/O Register (I2DR) Table 28-7.
Description Device that sends the data to the bus Device that receives the data from the bus Device that initiates transfer, generates SCL and terminates transfer Device that is addressed by the master MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
When successful slave addressing is achieved, the data transfer can proceed (E in byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Each data byte is 8 bits long. Freescale Semiconductor 28-8. Interrupt bit is set...
SCL line if another device clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Freescale Semiconductor is the case of a master-transmitter transmitting to a...
1. Update I2FDR[IC] to select the required division ratio to obtain the SCL frequency from the system clock 28-12 Master2 Loses Arbitration, and becomes Slave-Receiver Figure 28-12. Arbitration Procedure Wait State Figure 28-13. Clock Synchronization MCF548x Reference Manual, Rev. 3 Figure 28-13). When all Figure 28-12). In this Start Counting High Period Freescale Semiconductor...
/* Put module in master TX mode (generates START) */ MCF_I2C_I2CR |= 0x10; MCF_I2C_I2CR |= 0x20; /* Put target address into I2DR */ MCF_I2C_I2DR = TARGET_ADDR; Freescale Semiconductor C interface system NOTE C bus module is enabled, execute the MCF548x Reference Manual, Rev. 3...
/* Put data to be sent into I2DR */ MCF_I2C_I2DR = tx_buffer[i]; /*Wait for transfer to complete (Poll IIF bit) */ while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF) ); /* Clear IIF bit */ MCF_I2C_I2SR &= 0xFD; 28-14 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The actual NACK does not take place until after the last byte has been received. */ if (i==(rx_byte_count-2)) /*Disable Acknowledge (set I2CR.TXAK) */ MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; if (i==(rx_byte_count-1)) Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Initialization Sequence 28-15...
Following are examples of slave TX and RX illustrating the dummy read of I2DR and, for slave TX, the checking of RXAK: /************************************************************************ * Slave TX illustrating NACK on last byte (interrupt function disabled) * *************************************************************************/ 28-16 NOTE NOTE MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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/* Clear I2CR.MTX to put the module in receive mode */ MCF_I2C_I2CR &= 0xEF; /* Dummy read of I2DR to signal the module is ready for the next byte */ dummy_read = MCF_I2C_I2DR; Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Initialization Sequence 28-17...
When considering these cases, the slave service routine should test the IAL bit first, and the software should clear the IAL bit if it is set. 28.5.7 Flow Control Figure 28-14 displays the flow of a typical I 28-18 C interrupt process. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Write Next Byte to I2DR TXAK=1 Switch to Generate Rx Mode STOP Signal Dummy Read from I2DR Figure 28-14. Flow-Chart of Typical I Freescale Semiconductor Clear IIF Master Mode Last Byte to be Read Second Last Byte to be Read (Read)
ColdFire core and multichannel DMA access to the intelligent FIFOs that handle all packet retries and data framing • Internal USB 2.0 physical layer transceiver • 4 KByte of FIFO RAM and 1 KByte of descriptor RAM Freescale Semiconductor MCF548x Reference Manual, Rev. 3 29-1...
DRAMDR. This operation is described in Section 29.4.1.1, “USB Descriptor 29-2 Comm Bus Arbiter USB Controller and Synchronization Logic Integrated USB 2.0 PHY Download”. MCF548x Reference Manual, Rev. 3 Figure 29-1. Descriptor Interrupt USB 2.0 Device Controller Section 29.2.1, “USB Freescale Semiconductor...
USB 2.0 bus. 29.1.3.5.2 USBVBUS USB cable Vbus monitor input. 29.1.3.5.3 USBRBIAS Connection for external current setting resistor. This signal should be connected to a 9.1 KΩ +/– 1% pull-down resistor. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Introduction 29-3...
31–8 — Reserved, should be cleared. SUSP Suspend. This is the USB suspend indicator. 0 USB is not suspended. 1 USB is suspended. Freescale Semiconductor Table 29-1. USB Memory Map (Continued) Byte0 Uninitialized Uninitialized SUSP MBAR + 0xB400 Figure 29-2. USB Status Register (USBSR) Table 29-2.
The USBCR configures features of the module. Reset Uninitialized Reset Uninitialized Addr 29-10 Table 29-2. USBSR Field Descriptions Description Uninitialized Uninitialized MBAR + 0xB404 Figure 29-3. USB Control Register (USBCR) MCF548x Reference Manual, Rev. 3 — SPLIT LOCK Freescale Semiconductor RESUME...
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USB reset. This bit executes a hard reset of the USB module. This bit allows the system software to force a reset of the USB’s logic when the system is first connected to the USB, or for debug purposes. Freescale Semiconductor Table 29-3. USBCR Field Descriptions Description MCF548x Reference Manual, Rev.
29.2.2.4 USB Descriptor RAM Data Register (DRAMDR) The DRAMDR allows user access to the USB descriptor memory. Reset Uninitialized Reset Addr Figure 29-5. USB Descriptor RAM Data Register (DRAMDR) Freescale Semiconductor Table 29-4. DRAMCR Field Descriptions Description Uninitialized Uninitialized Uninitialized MBAR + 0xB40C MCF548x Reference Manual, Rev.
1 A start of frame token has been received by the USB. The USB frame number is current. 29-14 Table 29-5. DRAMDR Field Descriptions Description Uninitialized Uninitialized MSOF SOF RSTSTOP UPDSOF RES SUSP FTUNLCK ISOERR MBAR + 0xB410 Table 29-6. USBISR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Setting a bit in the USBIMR masks the corresponding interrupt in the USBISR. Reset Uninitialized Reset Unaffected by Reset Addr Figure 29-7. USB Interrupt Mask Register (USBIMR) Freescale Semiconductor Description Uninitialized Uninitialized MSOF SOF RSTSTOP UPDSOF RES SUSP FTUNLCK ISOERR MBAR + 0xB414 MCF548x Reference Manual, Rev. 3...
There is only one USBAISR to record all interrupt events for multiple endpoints. It is the responsibility of the application software’s interrupt service routine (ISR) to read the contents of the EPINFO register to determine the interrupting endpoint number and direction. 29-16 Table 29-7. USBIMR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
The USBAIMR allows the application to mask interrupt sources within the USB module. The format of this register is identical to that of the USBAISR. A logic 1 in any of the defined bit positions masks the corresponding interrupt source. Conversely, a logic 0 allows the core to interrupt the application. Freescale Semiconductor TRANSERR EPHALT MBAR + 0xB000 Table 29-8.
The EPINFO contains the currently active endpoint index. The contents of this register are updated each time a token is received by the USB device controller. 29-18 ACKEN TRANSEREN EPHALTEN MBAR + 0xB001 Table 29-9. USBAIMR Field Descriptions Description MCF548x Reference Manual, Rev. 3 OUTEN INEN SETUPEN Freescale Semiconductor...
SET_CONFIGURATION request. See Value Section 29.4.3.5.2, “Device 29.2.2.11 USB Configuration Attribute Register (CFGAR) The CFGAR contains attributes of the current configuration. Freescale Semiconductor MBAR + 0xB003 Table 29-10. EPINFO Field Descriptions Description Configuration Value MBAR + 0xB004 Table 29-11.
This is the number that needs to be written into the appropriate field of this register. Reset Addr Figure 29-15. Endpoint Transaction Number Register (EPTNR) Freescale Semiconductor MBAR + 0xB00E Table 29-14. FRMNUMR Field Descriptions Description EP6T...
The application software must program these registers with the valid interface numbers for the current configuration. 29-22 Table 29-15. EPTNR Field Descriptions Description Undefined MBAR + 0xB014 Table 29-16. IFUR Field Descriptions Description MCF548x Reference Manual, Rev. 3 ALTSET Freescale Semiconductor...
Bits Name 15–0 PPCNT Packet passed counter. This register counts the number of packets that have been received successfully by the USB. Freescale Semiconductor Table 29-17. IFRn Field Descriptions Description PPCNT MBAR + 0xB080 Table 29-18. PPCNT Field Descriptions Description MCF548x Reference Manual, Rev.
Figure 29-23. USB Framing Error Counter Register (FRMECNT) Bits Name 15–0 FRMECNT Framing error counter. This register counts the occurrences of errors in SYNC and EOP fields of incoming packets. Freescale Semiconductor Table 29-21. BSECNT Field Descriptions Description PIDECNT MBAR + 0xB088 Table 29-22. PIDECNT Field Descriptions...
(that is, upon the reception of a SET_CONFIGURATION or SET_INTERFACE request). Reset MBAR + 0xB101(EP0ACR); 0xB131(EP1OUTACR); 0xB161(EP2OUTACR); Addr 0xB191(EP3OUTACR); 0xB1C1(EP4OUTACR); 0xB1F1(EP5OUTACR); Figure 29-26. Endpoint n Attribute Control Register OUT (EPnOUTACR) Freescale Semiconductor Description NOTE 0xB221(EP6OUTACR) MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition TTYPE...
0 No interrupt pending on this endpoint (default). 1 Interrupt pending on this endpoint. — Reserved, should be cleared. 29-30 IFNUM Description TXZERO CCOMP TXZERO CCOMP Description MCF548x Reference Manual, Rev. 3 PSTALL ACTIVE HALT PSTALL ACTIVE HALT Freescale Semiconductor...
29.2.4.5 bmRequest Type Register (BMRTR) The BMRTR records the bmRequestType field of a SETUP transaction on Endpoint 0. Reset Addr Figure 29-34. Endpoint n bmRequest Type Register (BMRTR) Freescale Semiconductor Description TYPE MBAR + 0xB106 MCF548x Reference Manual, Rev. 3...
29.2.4.10 Endpoint n Sync Frame Register (EPnOUTSFR, EPnINSFR) The endpoint sync frame register is relevant only if the EPnOUTACR or EPnINACR is programmed for isochronous type transfers. This register contains the synchronization frame number for that endpoint. Freescale Semiconductor Table 29-32. WVALUER Field Descriptions Description...
29.2.5.1 USB Endpoint n Status and Control Register (EPnSTAT) The EPnSTAT register allows the user to configure specific aspects of an individual endpoint. 29-34 0xB1FE (EP5OUTSFR); 0xB22E (EP6OUTSFR) 0xB216 (EP5INSFR); 0xB246 (EP6INSFR) Description MCF548x Reference Manual, Rev. 3 FRMNUM FRMNUM Freescale Semiconductor...
(for example, if an endpoint FIFO is emptied and then filled with no intervention from software, both EMT and FU would be set). Writing a 0 has no effect. Freescale Semiconductor BYTECNT Table 29-36. EPnSTAT Field Descriptions Description MCF548x Reference Manual, Rev.
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FIFO low. This indicates that the number of bytes in the FIFO has fallen below the FIFO low level alarm value. 29-36 Uninitialized EMT ERR FIFO 0xB504 (EP4ISR); 0xB534 (EP5ISR); 0xB564 (EP6ISR) Table 29-37. EPnISR Field Descriptions Description MCF548x Reference Manual, Rev. 3 FIFO Unin. Unin. Freescale Semiconductor...
FIFOs. Note that care should be taken to ensure that no two active endpoints are allocated to the same memory address range, as this will result in corrupted data. 29-38 Table 29-38. EPnIMR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
FIFO, is accessed through this register. The register can access data from the FIFO, independent of this FIFO’s transmit or receive configuration. Reset Reset MBAR + 0xB450 (EP0FDR); 0xB480 (EP1FDR); 0xB4B0 (EP2FDR); 0xB4E0 (EP3FDR); Addr Figure 29-45. USB Endpoint n FIFO Data Register (EPnFDR) Freescale Semiconductor Uninitialized DEPTH Uninitialized Description RXDATA[31:16] TXDATA[31:16]...
0001 A frame boundary has occurred on the [7:0] byte of the data bus 29-40 Table 29-40. EPnFDR Field Descriptions Description FAE RXW Uninitialized 0xB514 (EP4FSR); 0xB544 (EP5FSR); 0xB574 (EP6FSR) Table 29-41. EPnFSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 ALRM EMT EPnISR unless the EPnFCR[IPMSK] bit is Freescale Semiconductor...
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1 The FIFO has requested attention because it is empty. The FIFO must be written to clear this alarm. 15–0 — Reserved, should be cleared. Freescale Semiconductor Table 29-41. EPnFSR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition...
This bit should be set during normal USB operation. 0 Frame mode disabled. 1 Frame mode enabled. 29-42 COUNTER 0xB518 (EP4FCR); 0xB548 (EP5FCR); 0xB578 (EP6FCR) Table 29-42. EPnFCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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Counter. When in timer mode, the value of COUNTER[15:0] is multiplied by 64 and that result is used to determine the number of cycles that should elapse before the frame ready service request is asserted. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3...
The alarm, once asserted will not negate until the high level mark is reached, as specified by the granularity bits in the EPnFCR. 29-44 Uninitialized 0xB51C (EP4FAR); 0xB54C (EP5FAR); 0xB57C (EP6FAR) Table 29-43. EPnFAR Field Descriptions Description MCF548x Reference Manual, Rev. 3 ALRMP Freescale Semiconductor...
There are no safeguards to prevent retransmitting data that has been overwritten. When EPnFCR[FRM] is not set, this pointer has no meaning. 29-46 Table 29-45. EPnFWP Field Descriptions Description Uninitialized Table 29-46. EPnLRFP Field Descriptions Description MCF548x Reference Manual, Rev. 3 LRFP Freescale Semiconductor...
USB. The device must be able to detect a connection event to the USB. This operation is described in the USB Specification, Chapter 7 (Electrical Specification). Freescale Semiconductor Uninitialized Table 29-47. EPnLWFP Field Descriptions Description for information on the USB interrupts.
Software is responsible for FIFO management and endpoint reconfiguration each time the USB host requests a configuration change via the SET_CONFIGURATION request. 29-48 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Endpoint direction is defined via the EPnSTAT register for each endpoint. FIFO characteristics are programmed via the EPnFCR and EPnFAR. These settings should be configured before the device responds to a request from the host. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Software Interface...
Isochronous data is also moved in the form of packets, but since isochronous pipes are given a fixed portion of the USB bandwidth at all time, there is no concept of an end of transfer. 29-50 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
To receive a packet of data from the USB host, either DMA or programmed I/O may be used. Refer to the DMA API documentation for DMA access information. For programmed I/O, follow these steps: 1. Monitor EOF interrupt for the endpoint. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 Software Interface 29-51...
USB module into the data FIFO, the EOF interrupt asserts. At the end of a complete transfer, the EOT interrupt asserts. Until the CPU has serviced the EOT interrupt, the device will NAK any 29-52 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
1. A SETUP packet is received on EP0 and the USBAISR[SETUP] bit will be set. 2. Read 8 bytes from the BMRTR, BRTR, WVALUER, WINDEXR, and WLENGTHR registers and decode the command. 3. Clear the USBAISR[SETUP] interrupt. Freescale Semiconductor NOTE (DRAMCR)”, for more details. MCF548x Reference Manual, Rev. 3...
NAK’ing the poll. Device driver software must be careful that the interrupt endpoint polling interval is longer than the device’s interrupt service latency. 29-54 MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
In order to allow the driver software to maintain synchronization with the USB host, the USB maintains a register which holds the current USB frame number. The start of frame maskable interrupt (USBISR[SOF] and USBIMR[SOF]) along with the frame number register (FRMNUMR) may be used for this synchronization. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 29-55...
The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. Freescale Semiconductor Table 30-1. MCF548x Family Products Product...
(EMDC/EMDIO signals) to the transceiver. Refer to the MMFR and MSCR register descriptions as well as the description of how to read and write registers in the Freescale Semiconductor Section 30.4.8, “Full Duplex Flow Options”.
EnTXD0 is used for serial data in 7-wire mode. encoding of EnTXD. 30-4 Section 30.4.3, “Network Interface Section 30.4.14, “MII Management Frame Loopback”. Table 30-2 MCF548x Reference Manual, Rev. 3 Options,” Structure.” Section 30.4.6, “Ethernet summarizes the permissible Freescale Semiconductor...
This signal transfers control/status information between the PHY and MAC. It transitions synchronously to EnMDC. The EnMDIO pin is a bidirectional pin. Table 30-2 below provides the interpretation of the possible encodings of EnTXEN, EnTXER. Freescale Semiconductor MCF548x Reference Manual, Rev. 3 External Signals Table 30-3...
MCF548x Reference Manual, Rev. 3 TXEN and E TXER Indication Normal inter-frame Reserved Normal data transmission Transmit error propagation Table 30-3 RXER and E RXDV Indication Normal inter-frame Normal inter-frame Reserved False Carrier Reserved Normal Data Reception Data reception with errors Freescale Semiconductor below.
RMON Rx 65 to 127 byte packets RMON Rx 128 to 255 byte packets RMON Rx 256 to 511 byte packets RMON Rx packets w > 2048 bytes RMON Rx Octets Frames Received OK Frames Received with CRC Error Receive Fifo Overflow count Freescale Semiconductor...
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This bit is cleared by writing a 1 to it. Transmit frame interrupt. This bit indicates that a frame has been transmitted. This bit is cleared by writing a 1 to it. Freescale Semiconductor MBAR + 0x9004 (FEC0), 0x9804 (FEC1) Table 30-7. EIR Descriptions Description Section 30.4.8, “Full Duplex Flow...
The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit. 30-12 Table 30-7. EIR Descriptions (Continued) Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
ECR is a read/write user register, though both fields in this register may be altered by hardware as well. The ECR is used to enable/disable the FEC. Reset Reset Addr Freescale Semiconductor MBAR + 0x9008 (FEC0), 0x9808 (FEC1) Table 30-8. EIMR Field Descriptions Description MBAR + 0x9024 (FEC0), 0x9824 (FEC1) Figure 30-4.
“write” frame operation, but these frames will not be MII compliant. 30-14 Table 30-9. ECR Field Descriptions Description Uninitialized DATA Uninitialized MBAR + 0x9040 (FEC0), 0x9840 (FEC1) Table 30-10. MMFR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
PHY register. 30.3.3.5 MII Speed Control Register (MSCR) The MSCR provides control of the MII clock (EMDC signal) frequency and allows dropping the preamble on the MII management frame. Freescale Semiconductor Description MCF548x Reference Manual, Rev. 3 Memory Map/Register Definition...
The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time). Freescale Semiconductor MBAR + 0x9064 (FEC0), 0x9864 (FEC1) Figure 30-7. MIB Control Register (MIBC) Table 30-13.
This read only register provides address recognition information from the receive block about the frame currently being received. 30-18 MBAR + 0x9084 (FEC0), 0x9884 (FEC1) Table 30-14. RCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 MAX_FL BC_REJ PROM MII_ MODE Freescale Semiconductor LOOP...
DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user. 30-20 Table 30-16. TCR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
PAUSE frames. This register is not reset and bits 31:16 must be initialized by the user. Reset Reset Addr Figure 30-12. Physical Address High Register (PAHR) Freescale Semiconductor PADDR1 Uninitialized PADDR1 Uninitialized MBAR + 0x90E4 (FEC0), 0x98E4 (FEC1) Table 30-17.
(DA) field of receive frames with an individual DA. This register is not reset and must be initialized by the user. 30-22 Table 30-18. PAHR Field Descriptions Description OPCODE PAUSE_DUR Uninitialized MBAR + 0x90EC (FEC0), 0x98EC (FEC1) Table 30-19. OPD Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
(DA) field of receive frames with an individual DA. This register is not reset and must be initialized by the user. Reset Reset Addr Figure 30-17. Individual Address Lower Register (IALR) Freescale Semiconductor IADDR1 Uninitialized IADDR1 Uninitialized MBAR + 0x9118 (FEC0), 0x9918 (FEC1) Table 30-20.
This register must be initialized by the user. 30-24 Table 30-21. IALR Field Descriptions Description GADDR1 Uninitialized GADDR1 Uninitialized MBAR + 0x9120 (FEC0), 0x9920 (FEC1) Table 30-22. GAUR Field Descriptions Description MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
Some of the bits of this register are used to generate DMA requests. 30-26 Table 30-24. FECTFWR Field Descriptions Descriptions FIFO_DATA FIFO_DATA MBAR + 0x9184 (FEC0), 0x9984 (FEC1) Table 30-25. FECRFDR Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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1 is written to this bit location. 0 No wait condition. 1 When the FIFO is full and the FEC received more data. Writing a one to this bit clears this bit. Freescale Semiconductor MBAR + 0x9188 (FEC0), 0x9988 (FEC1) Table 30-26. FECRFSR Field Descriptions Descriptions MCF548x Reference Manual, Rev.
Frame mode overrides the FIFO granularity bits. The bits of this register are shown in Figure Table 30-27. 30-28 Descriptions Section 30.3.3.23, “FEC Receive FIFO Alarm Register 30-23, and the fields are further defined in the field descriptions in MCF548x Reference Manual, Rev. 3 Freescale Semiconductor...
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RFERR in the EIR. OF_MSK FIFO overflow mask. When this bit is set, the FIFO controller masks the status register’s OF bit from generating a RFERR in the EIR. Freescale Semiconductor FAE_ COUNTER MBAR + 0x918C (FEC0), 0x998C (FEC1) Table 30-27.
For the frame discard function, the LWFP divides the valid data region of the FIFO (the area 30-30 Descriptions MBAR + 0x9190 (FEC0), 0x9990 (FEC1) Table 30-28. FECRLRFP Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 LRFP Freescale Semiconductor When...
The alarm register defines the alarm threshold for the number of free bytes in the FIFO. If there are less than FECRFAR[ALARM] free bytes in the FIFO, the FECRFSR[ALARM] bit is set. Freescale Semiconductor MBAR + 0x9194 (FEC0), 0x9994 (FEC1) Table 30-29. FECRLWFP Field Descriptions Descriptions MCF548x Reference Manual, Rev.
TFDR for byte, word, and longword transactions. However, accessing the data port at TFDR+1, 2, or 3 for bytes or TFDR+2 for words is also acceptable. This register is usually read without wait state, but can be held under boundary conditions. Freescale Semiconductor Table 30-31. FECRFRP Field Descriptions Descriptions MBAR + 0x91A0 (FEC0), 0x99A0 (FEC1) Table 30-32.
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Empty. This read only bit indicates that the FIFO is empty. The FIFO must be written to clear this bit. 15–0 — Reserved, should be cleared. Freescale Semiconductor Table 30-34. FECTFSR Field Descriptions Descriptions Section 30.3.3.27, “FEC Transmit FIFO Status Register MCF548x Reference Manual, Rev.
This bit must be set to use frame functions. 30-36 Table 30-35. FAE_ COUNTER MBAR + 0x91AC (FEC0), 0x99AC (FEC1) Table 30-35. FECTFCR Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 Figure TXW_ MASK Freescale Semiconductor 30-31, and...
When FECTFCR[FRMEN] is not set, then this pointer has no meaning. The last read frame pointer is reset to zero, and non-functional bits of this pointer will always remain zero. Freescale Semiconductor Descriptions MCF548x Reference Manual, Rev. 3...
When FECTFCR[FRMEN] is not set, then this pointer has no meaning. The last written frame pointer is reset to zero, and non-functional bits of this pointer will always remain zero. 30-38 MBAR + 0x91B0 (FEC0), 0x99B0 (FEC1) Table 30-36. FECTLRFP Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 LRFP Freescale Semiconductor...
The write pointer is reset to zero, and non-functional bits of this pointer will always remain zero. 30-40 Table 30-38. FECTFAR Field Descriptions Descriptions MBAR + 0x91BC (FEC0), 0x99BC (FEC1) Table 30-39. FECTFRP Field Descriptions Descriptions MCF548x Reference Manual, Rev. 3 READ Freescale Semiconductor...
The FIFO’s within the FEC module have independent controllers. This register provides the user the ability to reset FIFOs via hardware or software. Reset Reset Addr Figure 30-37. FEC FIFO Reset Register (FECFRST) Freescale Semiconductor MBAR + 0x91C0 (FEC0), 0x99C0 (FEC1) Table 30-40. FECTFWP Field Descriptions Descriptions RST_ MBAR + 0x91C4 (FEC0), 0x99C4 (FEC1) MCF548x Reference Manual, Rev.
Set IALR / IAUR Set GAUR / GALR Set PALR / PAHR (only needed for full duplex flow control) Set OPD (only needed for full duplex flow control) Set RCR Set TCR MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 30-43...
Description Set MSCR (optional) MBAR + 0x9A00–0x9AE3) Reset Comm Bus FIFOs in the FIFO Reset register Set Comm Bus FIFO Alarm and Control Registers — FRAME_LENGTH Table 30-45. RFSW Field Descriptions Description MCF548x Reference Manual, Rev. 3 — Freescale Semiconductor...
Append Bad CRC, written by user 0 No effect 1 Transmit the CRC sequence inverted after the last data bye (regardless of TC value) 24–0 — Reserved, should be cleared. Freescale Semiconductor Description — Table 30-46. TFCW Field Descriptions Description MCF548x Reference Manual, Rev. 3 Functional Description —...
FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which indicate serious LAN problems. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 30-47...
MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected. The flowchart shown in Figure 30-41 illustrates the address recognition decisions made by the receive block. MCF548x Reference Manual, Rev. 3 30-48 Freescale Semiconductor...
Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. Freescale Semiconductor Accept/Reject Frame...
During pause frame transmission, the transmit hardware places data into the transmit data stream from the registers shown in the table below. 30-52 6-bit Hash (in Address Hex) 0x3C 0x3D 0x3E 0x3F Register Contents 01:80:C2:00:00:01 or Physical Address 0x0000 to 0xFFFF MCF548x Reference Manual, Rev. 3 Hash Decimal Value 0x8808 0x0001 Freescale Semiconductor...
This will cause an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the Freescale Semiconductor FEC Register Internal...
If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC generates the HBERR interrupt if it is enabled. MCF548x Reference Manual, Rev. 3 30-54 Freescale Semiconductor...
10101010 10101010 10101010 10101010 10101010 10101010 10101010 The left-most 1 represents the LSB of the byte. The start of frame delimiter (sfd) represents the start of a frame and has the bit value, 10101011. MCF548x Reference Manual, Rev. 3 Freescale Semiconductor 30-55...
The MII management register set located in the PHY may consist of a basic register set and an extended register set as defined below. Register Addr. 30-56 First Nibble Second Nibble MII Nibble Table 30-52. MII Management Register Set Register Name Control Status PHY Identifier MCF548x Reference Manual, Rev. 3 Basic/Extended Freescale Semiconductor...
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Table 30-52. MII Management Register Set (Continued) Register Addr. 8-15 16-31 Freescale Semiconductor Register Name Auto-Negotiation (AN) Advertisement AN Link Partner Ability AN Expansion AN Next Page Transmit Reserved Vendor Specific MCF548x Reference Manual, Rev. 3 Functional Description Basic/Extended 30-57...
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Part V Mechanical Part V provides mechanical descriptions of the MCF548x. Contents • Chapter 31, “Mechanical Data,” MCF548x. Freescale Semiconductor provides a functional pin listing and package diagram for the MCF548x Reference Manual, Rev. 3...
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This pin is a “no connect” on the MCF5483 and MCF5482 devices. This pin is a “no connect” on the MCF5481 and MCF5480 devices. On MCF5485, MCF5484, MCF5483, and MCF5482 device the pin should be connected to the appriopriate power rail even is USB is not being used.
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