Mmu Operation Register (Mmuor) - Freescale Semiconductor MCF54455 Reference Manual

Memory Management Unit (MMU)
4.2.4

MMU Operation Register (MMUOR)

MMUBAR 0x004 (MMUOR)
Offset:
31 30 29
R
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Field
31–16 TLB allocation address. This read-only field is maintained by MMU hardware. Its range and format depend on the
AA TLB implementation (specific TLB size in entries, associativity, and organization). The access TLB function can
use AA to read or write the addressed TLB entry. The MMU loads AA on the following three events:
• On DTLB access errors, it loads the TLB entry address that caused the error.
• If MMUOR[UAA] is set, it loads the address of the TLB entry chosen by the MMU for replacement.
• If MMUOR[STLB] is set, it uses the data in MMUAR to search the TLB. If the TLB hits, it loads the address of
the TLB entry that hits; if the TLB misses, it loads the TLB entry chosen by the MMU for replacement.
The MMU never picks a locked entry for replacement, and TLB hits of locked entries do not update hardware
replacement algorithm information. This is so access error handlers mapped with locked TLB entries do not
influence the replacement algorithm. Further, TLB search operations do not update the hardware replacement
algorithm information; TLB writes (loads) do update the hardware replacement algorithm information. The
algorithm that chooses the allocation address depends on the TLB implementation (such as LRU, round-robin,
pseudo-random).
15–9 Reserved, must be cleared.
8 Search TLB. STLB always reads as zero.
STLB 0 No operation
1 The MMU searches the TLB using data in MMUAR. This operation updates the probe TLB hit bit in the status
register plus loads the AA field as described above.
7 Clear all TLB entries. CA always reads as zero.
CA 0 No operation
1 Clear all TLB entries and all hardware TLB replacement algorithm information.
6 Clear all non-locked TLB entries. Setting CNL clears all TLB entries that do not have locked bits. CNL always
CNL reads as zero.
0 No operation
1 Clear all non-locked TLB entries
5 Clear all non-locked TLB entries that match ASID. CAS always reads as a zero.
CAS 0 No operation
1 Clear all non-locked TLB entries that match ASID register
4 ITLB operation. Used by TLB search and access operations that use the TLB allocation address.
ITLB 0 MMU uses DTLB to search or update allocation address
1 MMU uses ITLB for of the allocation address searches and updates
4-6
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
STLB
0 0 0 0
Figure 4-5. MMU Operation Register (MMUOR)
Table 4-5. MMUOR Field Descriptions
Description
24 23 22 21
AA
0 0 0 0
8 7 6 5
0 0 0 0
ITLB
CA CNL CAS
0 0 0 0
Access: User read/write
20 19 18 17
0 0 0 0
4 3 2 1
0
ADR R/W
ACC UAA
0 0 0 0
Freescale Semiconductor
16
0
0
0
0