Freescale Semiconductor MCF54455 Reference Manual page 101

ColdFire Core
Table 3-19. General Branch Instruction Execution Times (continued)
Opcode <EA>
Rn
JMP <ea> —
JSR <ea> —
RTE —
RTS —
Opcode Correctly Predicts
Bcc
The following notes apply to the branch execution times:
1. For BRA and JMP <ea> instructions, where <ea> is (d16,PC) or xxx.wl, the branch acceleration
logic of the IFP calculates the target address and begins prefetching the new path. Because the IFP
and OEP are decoupled by the FIFO instruction buffer, the execution time can vary from one to
three cycles, depending on the decoupling amount.
For all other <ea> values of the JMP instruction, the branch acceleration logic is not used, and the
execution times are fixed.
2. For BSR and JSR xxx.wl opcodes, the same branch acceleration mechanism is used to initiate the
fetch of the target instruction. Depending on the amount of decoupling between the IFP and OEP,
the resulting execution times can vary from 1 to 3 cycles.
For the remaining <ea> values for the JSR instruction, the branch acceleration logic is not used,
and the execution times are fixed.
3. For the RTS opcode, the timing depends on the prediction results of the hardware return stack:
a) If predicted correctly, 2(1/0).
b) If mispredicted, 9(1/0).
c) If not predicted, 8(1/0).
3-35
(An) (An)+
5(0/0) —
5(0/1) —
— 15(2/0)
3
— 2(1/0)
3
9(1/0)
3
8(1/0)
Table 3-20. Bcc Instruction Execution Times
Branch Cache Prediction Table
Correctly Predicts
Taken Taken
0(0/0) 1(0/0)
Effective Address
(d16,An) (d8,An,Xi*SF)
-(An)
(d16,PC) (d8,PC,Xi*SF)
1
— 5(0/0) 6(0/0)
— 5(0/1) 6(0/1)
— — —
— — —
Predicted
Correctly as Not
Taken
1(0/0)
xxx.wl #xxx
1
1(0/0) —
2
1(0/1) —
— —
— —
Predicted
Incorrectly
8(0/0)
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