Freescale Semiconductor MCF54455 Reference Manual page 625

Fast Ethernet Controllers (FEC0 and FEC1)
Table 26-3 shows the FEC register memory map.
Address
FEC0
FEC1
0xFC03_0004 Interrupt Event Register (EIRn)
0xFC03_4004
0xFC03_0008 Interrupt Mask Register (EIMRn)
0xFC03_4008
0xFC03_0010 Receive Descriptor Active Register (RDARn)
0xFC03_4010
0xFC03_0014 Transmit Descriptor Active Register (TDARn)
0xFC03_4014
0xFC03_0024 Ethernet Control Register (ECRn)
0xFC03_4024
0xFC03_0040 MII Management Frame Register (MMFRn)
0xFC03_4040
0xFC03_0044 MII Speed Control Register (MSCRn)
0xFC03_4044
0xFC03_0064 MIB Control/Status Register (MIBCn)
0xFC03_4064
0xFC03_0084 Receive Control Register (RCRn)
0xFC03_4084
0xFC03_00C4 Transmit Control Register (TCRn)
0xFC03_40C4
0xFC03_00E4 Physical Address Low Register (PALRn)
0xFC03_40E4
0xFC03_00E8 Physical Address High Register (PAURn)
0xFC03_40E8
0xFC03_00EC Opcode/Pause Duration (OPDn)
0xFC03_40EC
0xFC03_0118 Descriptor Individual Upper Address Register
0xFC03_4118 (IAURn)
0xFC03_011C Descriptor Individual Lower Address Register (IALRn)
0xFC03_411C
0xFC03_0120 Descriptor Group Upper Address Register (GAURn)
0xFC03_4120
0xFC03_0124 Descriptor Group Lower Address Register (GALRn)
0xFC03_4124
0xFC03_0144 Transmit FIFO Watermark (TFWRn)
0xFC03_4144
26-7
Table 26-3. FEC Register Memory Map
Register
Width
Access Reset Value
(bits)
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0xF000_0000
32 R/W Undefined
32 R/W 0x0000_0000
32 R/W 0x0000_0000
32 R/W 0x05EE_0001
32 R/W 0x0000_0000
32 R/W Undefined
32 R/W See Section
32 R/W See Section
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W 0x0000_0000
Freescale Semiconductor
Section/Page
26.4.2/26-11
26.4.3/26-13
26.4.4/26-14
26.4.5/26-14
26.4.6/26-15
26.4.7/26-16
26.4.8/26-17
26.4.9/26-18
26.4.10/26-19
26.4.11/26-21
26.4.12/26-22
26.4.13/26-22
26.4.14/26-23
26.4.15/26-23
26.4.16/26-24
26.4.17/26-24
26.4.18/26-25
26.4.19/26-25