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Reset Controller Module
13.2
External Signal Description
Table 13-1
provides a summary of the reset-controller signal properties. The signals are described in the
following paragraphs.
Name
RESET
RSTOUT
1
All pull-ups are disconnected when the signal is programmed as an output.
2
RESET is always synchronized except when in low-power stop mode.
13.2.1
RESET
Asserting the external RESET for at least four rising FB_CLK edges causes the external reset request to
be recognized and latched.
13.2.2
RSTOUT
This active-low output signal is driven low when the internal reset controller module resets the device. It
may take up to six FB_CLK edges after RESET assertion for RSTOUT to assert, due to an internal
synchronizer on RESET. When RSTOUT is active, the user can drive override options on the data bus. See
Chapter 11, "Chip Configuration Module (CCM),"
13.3
Memory Map/Register Definition
The reset controller programming model consists of these registers:
•
Reset control register (RCR), which selects reset control functions
•
Reset status register (RSR), which reflects the state of the last reset source
See
Table 13-2
for the memory map and the following paragraphs for register descriptions.
Address
0xFC0A_0000 Reset Control Register (RCR)
0xFC0A_0001 Reset Status Register (RSR)
13.3.1
Reset Control Register (RCR)
The RCR allows software control for requesting a reset and for independently asserting the external
RSTOUT pin.
13-2
Table 13-1. Reset Controller Signal Properties
1
I/O
Pull-up
I
Active
O
—
for more details on these override options.
Table 13-2. Reset Controller Memory Map
Register
Input
Input
Hysteresis
Synchronization
Y
—
Width
Access Reset Value
(bits)
8
R/W
8
R
See Section
2
Y
—
Section/Page
0x00
13.3.1/13-2
13.3.2/13-3
Freescale Semiconductor
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