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Enhanced Direct Memory Access (eDMA)
Address: 0xFC04_401E (EDMA_SSRT)
7
R
0
W
SAST
Reset
0
Figure 19-13. eDMA Set START Bit Register (EDMA_SSRT)
Field
7
Reserved, must be cleared.
6
Set all START bits (activates all channels).
SAST
0 Set only those TCDn_CSR[START] bits specified in the SSRT field.
1 Set all bits in TCDn_CSR[START].
5–4
Reserved, must be cleared.
3–0
Set START bit. Sets the corresponding bit in TCDn_CSR[START].
SSRT
19.4.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE)
The EDMA_CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of
the given channel. The data value on a register write causes the DONE bit in the corresponding transfer
control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE
bits to be cleared. Reads of this register return all zeroes.
Address: 0xFC04_401F (EDMA_CDNE)
7
R
0
W
CADN
Reset
0
Figure 19-14. eDMA Clear DONE Status Bit Register (EDMA_CDNE)
Field
7
Reserved, must be cleared.
6
Clears all DONE bits.
CADN
0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field.
1 Clears all bits in TCDn_CSR[DONE]
5–4
Reserved, must be cleared.
3–0
Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE].
CDNE
19-14
6
5
0
0
0
0
Table 19-14. EDMA_SSRT Field Descriptions
6
5
0
0
0
0
Table 19-15. EDMA_CDNE Field Descriptions
4
3
0
0
0
0
Description
4
3
0
0
0
0
Description
Access: User write-only
2
1
0
0
SSRT
0
0
Access: User write-only
2
1
0
0
CDNE
0
0
Freescale Semiconductor
0
0
0
0
0
0
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