Introduction - Freescale Semiconductor MCF54455 Reference Manual

Chapter 35
IEEE 1149.1 Test Access Port (JTAG)
35.1

Introduction

The Joint Test Action Group (JTAG) is a dedicated user-accessible test logic compliant with the
IEEE 1149.1 standard for boundary-scan testability, which helps with system diagnostic and
manufacturing testing.
This architecture provides access to all data and chip control pins from the board-edge connector through
the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
35.1.1 Block Diagram
Figure 35-1 shows the block diagram of the JTAG module.
TDI/DSI
JTAG_EN
TCLK
TMS/BKPT
TRST/DSCLK
JTAG Module
Freescale Semiconductor
TAP Controller
1-bit Bypass Register
Boundary Scan Register
31
32-bit IDCODE Register
1-bit TEST_CTRL Register
5-bit TAP Instruction Decoder
4
5-bit TAP Instruction Register
Figure 35-1. JTAG Block Diagram
0
0
Disable DSCLK
Force BKPT = 1
DSI = 0
DSO
to Debug Module
DSI
BKPT
DSCLK
1
TDO/DSO
0
1
0
35-1