Timing Registers (Time_X) - Freescale Semiconductor MCF54455 Reference Manual

— bits [15:8]: byte 2
— bits [7:0]: byte 3
• Big endian, 16-bit register
— bits [15:8]: byte 0
— bits [7:0]: byte 1
23.3.2

Timing Registers (TIME_x)

The timing registers contain the parameters that control the timing on the ATA bus. Details of the ATA bus
timing are shown in detail in the following sections:
• Section 23.4.1.1, "PIO Mode Timing Diagrams"
• Section 23.4.1.2, "Multiword DMA Mode Timing Diagrams"
• Section 23.4.1.3, "Ultra DMA In Timing Diagrams"
• Section 23.4.1.4, "Ultra DMA Out Timing Diagrams"
Every timing parameter is 8-bit wide and can assume valid values between 1 and 255. Reset value is
always 0x01.
Address: 0x9000_0000 (TIME_OFF)
0x9000_0001 (TIME_ON)
0x9000_0002 (TIME_1)
0x9000_0003 (TIME_2W)
0x9000_0004 (TIME_2R)
0x9000_0005 (TIME_AX)
0x9000_0006 (TIME_PIO_RDX)
0x9000_0007 (TIME_4)
0x9000_0008 (TIME_9)
0x9000_0009 (TIME_M)
0x9000_000A (TIME_JN)
0x9000_000B (TIME_D)
7
R
W
Reset 0
Field
7–0 Indicates the timing parameter used for the ATA bus. See
TIME_x setting the individual values. Valid values between 1 and 255. Reset value is always 0x01.
23.3.3 FIFO Data Register (FIFO_DATA_n)
The FIFO data register reads or writes data to the internal FIFO. It can be accessed as a 16-bit register or
as a 32-bit register. Any longword write to the register puts the four bytes written into the FIFO, and any
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0x9000_000C (TIME_K)
0x9000_000D (TIME_ACK)
0x9000_000E (TIME_ENV)
0x9000_000F (TIME_RPX)
0x9000_0010 (TIME_ZAH)
0x9000_0011 (TIME_MLIX)
0x9000_0012 (TIME_DVH)
0x9000_0013 (TIME_DZFS)
0x9000_0014 (TIME_DVS)
0x9000_0015 (TIME_CVH)
0x9000_0016 (TIME_SS)
0x9000_0017 (TIME_CYC)
6 5
0 0
Figure 23-2. TIME_x Register
Table 23-3. TIME_x Field Descriptions
Advanced Technology Attachment (ATA)
4 3
TIME_x
0 0
Description
Section 23.4.1, "Timing on ATA Bus,"
Access: User read/write
2 1
0 0
for details on
0
1
23-7