Freescale Semiconductor MCF54455 Reference Manual page 549

PCI Bus Controller
PCI Bus
PCI_CBE[3:0]
Command
1110
MEMORY READ
LINE
1111
MEMORY WRITE
AND INVALIDATE
Though this device supports many PCI commands as an initiator, the communication subsystem initiator
interface should use PCI
22.4.1.5 Addressing
PCI defines three physical address spaces: PCI memory space, PCI I/O space, and PCI configuration
space. Every device for every PCI transaction performs address decoding on the PCI bus. Each agent is
responsible for decoding its own address. The PCI specification supports two types of address decoding:
positive decoding and subtractive decoding (refer to
address space accessed depends primarily on the type of PCI command used.
22.4.1.5.1 Memory Space Addressing
For memory accesses, PCI defines two types of burst ordering controlled by the two low-order bits of the
address: linear incrementing (AD[1:0] equals 0b00) and cache wrap mode (AD[1:0] equals 0b10). The
other two AD[1:0] encodings (0b01 and 0b11) are reserved.
For linear incrementing mode, the memory address is encoded/decoded using PCI_AD[31:2]. Thereafter,
the address increments by 4 bytes after each data phase completes until the transaction terminates or
completes (a 4 byte data width per data phase is implied). The two low-order bits of the address are still
included in all the parity calculations.
As an initiator, the PCI controller supports linear incrementing and cache wrap mode. When an internal
bus burst transaction is wrapped for memory transactions, the cache wrap mode automatically generates.
For zero-word-aligned bursts and single-beat transactions, the PCI controller drives AD[1:0] to 0b00.
As a target, PCI controller treats cache wrap mode as a reserved memory mode when the cache line size
field is cleared, PCICR1[CLS]. The PCI controller returns the first beat of data and signals a disconnect
without data on the second data phase. When the cache line size field is programmed to a non-zero value,
cache wrap bursts break up and transfer linearly on the internal bus. Reads from the PCI controller,
implemented as delayed reads, always disconnect at the cache line boundary. The PCI controller is not
optimized for wrapping bursts.
22-32
Table 22-26. PCI Bus Commands (continued)
PCI Controller PCI Controller
Supports as Supports as
Initiator Target
Yes Yes
Yes (DMA Yes
access only)
and
MEMORY READ MEMORY WRITE
Definition
The command indicates an initiator
MEMORY READ LINE
requests the transfer of an entire cache line. For the PCI
controller, the
MEMORY READ LINE
command. Cache line wrap is not
MEMORY READ
implemented.
The
MEMORY WRITE AND INVALIDATE
initiator transfers an entire cache line; if this data is in any
cacheable memory, that cache line needs to be invalidated.
The
MEMORY WRITE AND INVALIDATE
the command. Cache line wrap is not
MEMORY WRITE
implemented.
commands.
Section 22.4.1.5.4, "Address
functions the same as the
command indicates an
functions the same as
Decoding"). The
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