Bdm Address Attribute Register (Baar) - Freescale Semiconductor MCF54455 Reference Manual

Debug Module
Field
9–8 Branch target bytes. Defines the number of bytes of branch target address PSTDDATA displays.
BTB 00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See Section 34.4.4.1, "Begin Execution of Taken Branch (PST =
7 Reserved, must be cleared.
6 Non-pipelined mode. Determines whether the core operates in pipelined mode or not.
NPL 0 Pipelined mode
1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at
least 5 cycles to the execution time of each instruction. Superscalar instruction dispatch is disabled when
operating in this mode. Given an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline
mode would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction
executes. In normal pipeline operation, occurrence of an address and/or data breakpoint trigger is imprecise. In
non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting
can be considered precise.
An address or data breakpoint should always occur before the next instruction begins execution. Therefore, the
occurrence of the address/data breakpoints should be guaranteed.
5 Ignore pending interrupts.
IPI 0 Core services any pending interrupt requests that were signalled while in single-step mode.
1 Core ignores any pending interrupt requests signalled while in single-instruction-step mode.
4 Single-Step Mode. Setting SSM puts the processor in single-step mode.
SSM 0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command
can be executed. On receipt of the
This process continues until SSM is cleared.
3 Ownership-trace enable. Enables the display of the ASID on the PSTDDATA outputs upon entrance into user
OTE mode, a load of the ASID by a MOVEC instruction, or the execution of a BDM SYNC_PC command.
0 No ASID displayed
1 ASID displayed on PSTDDATA outputs
2 Reserved, must be cleared.
1 Force the debug mode core output signal (to the on-chip peripherals). The debug mode output is logically defined
FDBG as:
Debug mode output = CSR[FDBG] | (CSR[DBGH] and Core is halted)
0 Debug mode output is not forced asserted.
1 Debug mode output core output signal is asserted.
0 Disable debug signal assertion during core halt. The debug mode output (to the on-chip peripherals) is logically
DBGH defined as:
Debug mode output = CSR[FDBG] | (CSR[DBGH] and Core is halted)
0 Debug mode output is asserted when the core is halted.
1 Debug mode output is not asserted when the core is halted.
34.3.3

BDM Address Attribute Register (BAAR)

The BAAR register defines the address space for memory-referencing BDM commands. BAAR[R, SZ]
are loaded directly from the BDM command, while the low-order 5 bits can be programmed from the
34-11
Table 34-7. CSR Field Descriptions (continued)
Description
command, the processor executes the next instruction and halts again.
GO
0x5)".
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