Freescale Semiconductor MCF54455 Reference Manual page 304

Table 11-13. Serial Configuration During Reset for 360-pin Devices (continued)
Pin(s) Affected
Configuration
(none)
(none)
(none) See MISCCR[5]
(none) See MISCCR[0]
(none) See MISCCR[1]
(none) See MISCCR[7]
(none) See MISCCR[6]
(none) See MISCCR[4]
(none)
See RCON[3] -
(none) host mode disables
Freescale Semiconductor
Default Override Serial
RCON Bits
24 (dec) SBF_RCON[119:112]
SBF_RCON[111]
See RCON[4]
SBF_RCON[110]
SBF_RCON[109]
SBF_RCON[108]
SBF_RCON[107]
SBF_RCON[106]
SBF_RCON[105]
SBF_RCON[104]
See RCON[2]
SBF_RCON[103]
interrupt
PLL Reference Clock Multiplier
This value is loaded into the PLL's PCR[PFDR].
1 Limp mode
0 PLL mode
Timer/SSI DMA Channel Mux Select
1 Timer 0-3 DMA signals mapped to DMA channels
9-12, respectively
0 SSI RX0, SSI RX1, SSI TX0, SSI TX1 DMA signals
mapped to DMA channels 9-12, respectively
1 PLL drives USB serial interface clocks
0 USB_CLKIN pin drives USB serial interface clock
USB VBUS Overcurrent Sense Polarity
1 USB_VBUS_OC is active-high
0 USB_VBUS_OC is active-low
SSI RXD/TXD Pull Enable
1 SSI_RXD,SSI_TXD pull cells enabled
0 SSI_RXD,SSI_TXD pull cells disabled
SSI RXD/TXD Pull Select
1 SSI_RXD,SSI_TXD pulled high
0 SSI_RXD,SSI_TXD pulled low
1 PLL drives SSI clock
0 SSI_CLKIN pin drives SSI clock
PCI Pad Slew Rate Mode
1 66 MHz slew rate mode
0 33 MHz slew rate mode
1 PCI interrupt enabled
0 PCI interrupt disabled
Chip Configuration Module (CCM)
Function
PLL Mode
USB Clock Source
SSI Clock Source
PCI Interrupt
11-17