Freescale Semiconductor MCF54455 Reference Manual page 855

Debug Module
DRc[4:0]: 0x06 (AATR)
0x16 (AATR1)
31 30 29
R
W
0 0 0
Reset 0 0 0
15 14 13
R
W RM SZM
Reset 0 0 0
Figure 34-5. Address Attribute Trigger Registers (AATR, AATR1)
Field
31–25 Reserved, must be cleared.
24 ABLR/ABHR/AATR address breakpoint ASID enable. Corresponds to the ASID control enable for the address
ASIDCTRL breakpoint defined in ABLR, ABHR, and AATR.
0 Disable ASID qualifier (reset default)
1 Enable ASID qualifier
23–16 ABLR/ABHR/AATR ASID. Corresponds to the ASID to be included in the address breakpoint specified by
AATRASID ABLR, ABHR, and AATR.
15 Read/write Mask. Setting RM masks R in address comparisons.
RM
14–13 Size Mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
SZM
12–11 Transfer Type Mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
TTM
10–8 Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
TMM
7 Read/Write. R is compared with the R/W signal of the processor's local bus.
R
6–5 Size. Compared to the processor's local bus size signals.
SZ 00 Longword
01 Byte
10 Word
11 Reserved
34-13
28 27 26 25
ASID
0 0 0 0
CTRL
0 0 0 0
12 11 10 9
TTM TMM
0 0 0 0
Table 34-9. AATRn Field Descriptions
24 23 22 21
AATRASID
0 0 0 0
8 7 6 5
R SZ
0 0 0 0
Description
Access: Supervisor write-only
BDM write-only
20 19 18 17
0 0 0 0
4 3 2 1
TT TM
0 0 1 0
Freescale Semiconductor
16
0
0
1