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Debug Module
between each bit exchange. The msb is sent first. Because DSO changes state based on an internally
recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The
development system must count clock cycles in a given transfer. C0–C4 are described as:
•
C0: Set the state of the DSI bit
•
C1: First synchronization cycle for DSI (DSCLK is high)
•
C2: Second synchronization cycle for DSI (DSCLK is high)
•
C3: BDM state machine changes state depending upon DSI and whether the entire input data
transfer has been transmitted
•
C4: DSO changes to next value
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
34.4.1.3
Receive Packet Format
The basic receive packet consists of 16 data bits and 1 status bit
.
16
15
14
13
S
Field
16
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored
S
unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer
after 32 processor clock periods.
S
0
0
1
1
1
15–0
Data. Contains the message to be sent from the debug module to the development system. The response message
Data
is always a single word, with the data field encoded as shown above.
34.4.1.3.1
Transmit Packet Format
The basic transmit packet consists of 16 data bits and 1 reserved bit.
34-29
NOTE
12
11
10
9
Figure 34-17. Receive BDM Packet
Table 34-22. Receive BDM Packet Field Description
Data
xxxx
Valid data transfer
FFFF
0000
Not ready with response; come again
0001
Error-Terminated bus cycle; data invalid
FFFF
Illegal Command
8
7
6
5
4
Data
Description
Message
Status OK
3
2
1
0
Freescale Semiconductor
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