Freescale Semiconductor MCF54455 Reference Manual page 473

FlexBus
Figure 20-13 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_AD[31:16].
Mux'd Bus
Non-Mux'd Bus
FB_CSn, FB_BE/BWEn
Figure 20-14 depicts a longword read from a 32-bit device.
Mux'd Bus
Non-Mux'd Bus
20-20
S0
FB_CLK
FB_AD[15:0]
FB_AD[31:16]
ADDR[31:16]
FB_A[15:0]
FB_D[31:16]
ADDR[31:16]
FB_R/W
FB_ALE
FB_OE
FB_TA
FB_TSIZ[1:0]
Figure 20-13. Single Word-Write Transfer
S0
FB_CLK
ADDR[31:0]
FB_AD[31:0]
FB_A[23:0]
ADDR[31:0]
FB_D[31:0]
FB_R/W
FB_ALE
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 20-14. Longword-Read Transfer
S1
S2 S3
ADDR[15:0]
DATA[15:0]
ADDR[15:0]
DATA[15:0]
10
S1 S2 S3
DATA[31:0]
ADDR[23:0]
DATA[31:0]
00
S0
S0
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