Freescale Semiconductor MCF54455 Reference Manual page 169

Cache
The following tables present the same information as
line. In Table 6-7 the current state is invalid.
Table 6-7. Data Cache Line State Transitions (Current State Invalid)
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
In Table 6-8 the current state is valid.
Table 6-8. Data Cache Line State Transitions (Current State Valid)
Access
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
6-24
Access
(C,W)I1 Read line from memory and update cache;
supply data to processor;
go to valid state.
(C,W)I2 Not possible
CI3 Read line from memory and update cache;
write data to cache;
go to modified state.
WI3 Write data to memory;
stay in invalid state.
CI4 Not possible
WI4 Not possible
(C,W)I5 No action;
stay in invalid state.
(C,W)I6 No action;
stay in invalid state.
(C,W)I7 No action;
stay in invalid state.
(C,W)V1 Read new line from memory and update cache;
supply data to processor; stay in valid state.
(C,W)V2 Supply data to processor;
stay in valid state.
CV3 Read new line from memory and update cache;
write data to cache;
go to modified state.
WV3 Write data to memory;
stay in valid state.
CV4 Write data to cache;
go to modified state.
WV4 Write data to memory and to cache;
stay in valid state.
(C,W)V5 No action;
go to invalid state.
Table 6-6, organized by the current state of the cache
Response
Response
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