Freescale Semiconductor MCF54455 Reference Manual page 876

The following sections describe the commands summarized in
The BDM status bit (S) is 0 for normally completed commands. S is set for
illegal commands, not-ready responses, and transfers with bus-errors.
Section 34.4.1.2, "BDM Serial
format.
34.4.1.5.1 Read A/D Register (
Read the selected address or data register and return the 32-bit result. A bus error response is returned if
the CPU core is not halted.
Command/Result Formats:
15 14
Command
Result
Command Sequence:
Operand Data: None
Result Data: The contents of the selected register are returned as a longword value,
most-significant word first.
34.4.1.5.2 Write A/D Register (
The operand longword data is written to the specified address or data register. A write alters all 32 register
bits. A bus error response is returned if the CPU core is not halted.
Command Format:
15 14 13
0x2
Freescale Semiconductor
Interface," describes the receive packet
/
RAREG RDREG
13 12 11 10
0x2 0x1
Figure 34-21.
RAREG
RAREG/RDREG
??? MS RESULT
Figure 34-22.
RAREG
/
WAREG WDREG
12 11 10 9
0x0
Figure 34-23.
WAREG
Table 34-25.
NOTE
)
9 8 7 6 5
0x8
D[31:16]
D[15:0]
/ Command Format
RDREG
XXX NEXT CMD
LS RESULT
XXX NEXT CMD
BERR 'NOT READY'
/ Command Sequence
RDREG
)
8 7 6 5
0x8
D[31:16]
D[15:0]
/ Command Format
WDREG
Debug Module
4 3 2 1
A/D Register
4 3 2 1
A/D Register
0
0
34-34