Freescale Semiconductor MCF54455 Reference Manual page 296

Address: 0xFC0A_0010 (MISCCR)
15 14 13
R 0 0 0
W
Reset 0 0 0
Note: Reset value depends on RCON type. See
Field
LIMP
BME
BMT
SSIPUE
SSIPUS
TIMDMA
SSISRC
USBPUD
USBOC
USBSRC
Field
15–13 Reserved, must be cleared.
12 Limp mode enable. Selects between the PLL and the low-power clock divider as the source of all system clocks.
LIMP 0 Normal operation; PLL drives system clocks.
1 Limp mode; low-power clock divider drives system clocks.
Note: The transient behavior of the system when writing this bit cannot be predicted. When any USB wake-up
event is detected, this bit is cleared, limp mode is exited, and the PLL begins the process of relocking and
driving the system clocks.
11 Bus monitor external enable bit. Enables the bus monitor to operate during external FlexBus cycles
BME 0 Bus monitor disabled on external FlexBus cycles
1 Bus monitor enabled on external FlexBus cycles
Freescale Semiconductor
12 11 10 9
LIMP BME BMT
See Note
Table
Figure 11-7. Miscellaneous Control Register (MISCCR)
Table 11-7. MISCCR Field Reset Values
00
0
1
000
1
1
1
1
0
1
1
Table 11-8. MISCCR Field Descriptions
8 7 6 5
SSI SSI TIM
PUE PUS DMA
11-7.
BOOTMOD[1:0]
10
FB_AD4 SBF_RCON[111]
1 SBF_RCON[123]
000 SBF_RCON[122:120]
1 SBF_RCON[107]
1 SBF_RCON[106]
1 SBF_RCON[110]
1 SBF_RCON[105]
0
1 SBF_RCON[108]
1 SBF_RCON[109]
Description
Chip Configuration Module (CCM)
Access: Supervisor read/write
4 3 2 1
0
SSI USB USB
SRC PUD OC
0 0 See Note
11
0
0
USB
SRC
11-9