Freescale Semiconductor MCF54455 Reference Manual page 366

Address: 0xFC0A_4030 (PPDSDR_FEC0H)
0xFC0A_4031 (PPDSDR_FEC0L)
0xFC0A_4039 (PPDSDR_UART)
0xFC0A_403C (PPDSDR_PCI)
0xFC0A_4040 (PPDSDR_FEC1H)
0xFC0A_4041 (PPDSDR_FEC1L)
0xFC0A_4044 (PPDSDR_FBADH)
0xFC0A_4045 (PPDSDR_FBADMH)
0xFC0A_4046 (PPDSDR_FBADML)
0xFC0A_4047 (PPDSDR_FBADL)
7
R
W
Reset: [Px7]
Figure 16-18. Port x Pin Data/Set Data Registers (PPDSDR_x)
Address: 0xFC0A_403A (PPDSDR_DSPI)
7
R 0
W
Reset: 0
Figure 16-19. Port DSPI Pin Data/Set Data Registers (PPDSDR_DSPI)
Address: 0xFC0A_4037 (PPDSDR_FECI2C)
0xFC0A_403E (PPDSDR_ATAH)
7
R 0
W
Reset: 0
Figure 16-20. Port x Pin Data/Set Data Registers (PPDSDR_x)
Address: 0xFC0A_4032 (PPDSDR_SSI)
7
R 0
W
Reset: 0
Figure 16-21. Port SSI Pin Data/Set Data Registers (PPDSDR_SSI)
Freescale Semiconductor
6 5
[Px6] [Px5] [Px4]
6 5
[PDSPI6] [PDSPI5] [PDSPI4]
6 5
0
0 [Px5] [Px4]
6 5
0 0
0 0 [PSSI4]
4 3 2
PPDR_x
PSDR_x
[Px3] [Px2]
4 3 2
PPDR_DSPI
PSDR_DSPI
[PDSPI3] [PDSPI2]
4 3 2
PPDR_x
PSDR_x
[Px3] [Px2]
4 3 2
PPDR_SSI
PSDR_SSI
[PSSI3] [PSSI2]
Pin Multiplexing and Control
Access: User read/write
1 0
[Px1] [Px0]
Access: User read/write
1 0
[PDSPI1] [PDSPI0]
Access: User read/write
1 0
[Px1] [Px0]
Access: User read/write
1 0
[PSSI1] [PSSI0]
16-21