Freescale Semiconductor MCF54455 Reference Manual page 845

Debug Module
The first version 2 ColdFire core devices implemented the original debug architecture, now called revision
A. Based on feedback from customers and third-party developers, enhancements have been added to
succeeding generations of ColdFire cores. For revision A, CSR[HRL] is 0. See
"Configuration/Status Register
Revision B (and B+) of the debug architecture offers more flexibility for configuring the hardware
breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while
hardware breakpoint registers are active. Revision B+ adds three additional PC breakpoint registers. For
revision B, CSR[HRL] is 1, and for revision B+, CSR[HRL] is 0x9.
Revision C of the debug architecture more than doubles the on-chip breakpoint registers and provides an
ability to interrupt debug service routines. This revision also combines the PST and DDATA signals into
PSTDDATA[7:0]. Because real-time trace information appears as a sequence of 4-bit values, there are no
alignment restrictions. In other words, PST values and operands may appear on either nibble of
PSTDDATA. For revision C, CSR[HRL] is 2.
The addition of the memory management unit (MMU) to the baseline architecture requires corresponding
enhancements to the ColdFire debug functionality, resulting in revision D. For revision D, the revision
level bit, CSR[HRL], is 3.
With software support, the MMU can provide a demand-paged, virtual address environment. To support
debugging in this virtual environment, the debug enhancements are primarily related to the expansion of
the virtual address to include the 8-bit address space identifier (ASID). Conceptually, the virtual address
is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address.
The expansion of the virtual address affects two major debug functions:
• The ASID is optionally included in the specification of the hardware breakpoint registers. As an
example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID
value may be programmed as part of the breakpoint instruction address. Likewise, each operand
address/data breakpoint register is expanded to include an ASID value. Finally, control registers
define if and how the ASID is to be included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which the ASID value may be
optionally displayed as part of the real-time trace functionality. When enabled, real-time trace
displays instruction addresses on every change-of-flow instruction that is not absolute or
PC-relative. For Rev. D, this instruction address display optionally includes the contents of the
ASID, thus providing the complete instruction virtual address on these instructions.
• Additionally when a
system, the processor optionally displays the complete virtual instruction address, including the
8-bit ASID value.
In addition to these ASID-related changes, the MMU control registers are accessible by using serial BDM
commands. The same BDM access capabilities are also provided for the EMAC programming model.
Finally, a serial BDM command is implemented (
generates an incorrect memory address that hangs the external bus. The BDM command attempts to break
this condition by forcing a bus termination.
34-3
(CSR)".
_ serial BDM command is loaded from the external development
SYNC PC
FORCE
Section 34.3.2,
_ ) to assist debugging when a software error
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