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Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction. These control registers are
write-only from the programming model and they can be written through the
BDM port using the
configuration/status register (CSR) can be read through the BDM port using
the
RDMREG
The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values. With the addition of the MMU capabilities, the breakpoint specifications
must be expanded to optionally include the address space identifier (ASID) in these user-programmable
virtual address triggers.
The core includes four PC breakpoint triggers and two sets of operand address breakpoint triggers, each
with two independent address registers (to allow specification of a range) and a data breakpoint with
masking capabilities. Core breakpoint triggers are accessible through the serial BDM interface or written
through the supervisor programming model using the WDEBUG instruction.
Two ASID-related registers (PBAC and PBASID) are added for the PC breakpoint qualification, and two
existing registers (AATR and AATR1) are expanded for the address breakpoint qualification.
34.3.1
Shared Debug Resources
The debug module revision A implementation provides a common hardware structure for BDM and
breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown
in
Table
34-6.
Register
AATR
ABHR
DBR
Therefore, loading a register to perform a specific function that shares hardware resources is destructive
to the shared function. For example, if an operand address breakpoint is loaded into the debug module, a
BDM command to access memory overwrites an address breakpoint in ABHR. If a data breakpoint is
configured, a BDM write command overwrites the data breakpoint in DBR.
Revision B added hardware registers to eliminate these shared functions. The BAAR is used to specify bus
attributes for BDM memory commands and has the same format as the LSB of the AATR. The registers
containing the BDM memory address and the BDM data are not program visible.
Freescale Semiconductor
command. In addition, the
WDMREG
command.
Table 34-6. Shared BDM/Breakpoint Hardware
BDM Function
Bus attributes for all memory commands
Address for all memory commands
Data for all BDM write commands
NOTE
Breakpoint Function
Attributes for address breakpoint
Address for address breakpoint
Data for data breakpoint
Debug Module
34-8
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