Freescale Semiconductor MCF54455 Reference Manual page 649

Fast Ethernet Controllers (FEC0 and FEC1)
(as a single 32-bit word) by the receive logic. The length field for the end of frame buffer is written with
the length of the entire frame, not only the length of the last buffer.
For simplicity, the driver may assign a large enough default receive buffer length to contain an entire
frame, keeping in mind that a malfunction on the network or out-of-spec implementation could result in
giant frames. Frames of 2K (2048) bytes or larger are truncated by the FEC at 2047 bytes so software never
sees a receive frame larger than 2047 bytes.
Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes
to the RDARn register. As frames are received, the FEC fills receive buffers and updates the associated
BDs, then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E
bit cleared, it polls this BD once more. If RxBDn[E] is clear a second time, FEC stops reading receive BDs
until the driver writes to RDARn.
26.5.1.2 Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1)
In the RxBD, the user initializes the E and W bits in the first longword and the pointer in the second
longword. When the buffer has been DMA'd, the Ethernet controller modifies the E, L, M, BC, MC, LG,
NO, CR, OV, and TR bits and writes the length of the used portion of the buffer in the first longword. The
M, BC, MC, LG, NO, CR, OV, and TR bits in the first longword of the buffer descriptor are only modified
by the Ethernet controller when the L bit is set.
15 14
Offset + 0 E RO1
Offset + 2
Offset + 4
Offset + 6
Word Field
Offset + 0 15 Empty. Written by the FEC (=0) and user (=1).
E 0 The data buffer associated with this BD is filled with received data, or data reception has aborted
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Offset + 0 14 Receive software ownership. This field is reserved for use by software. This read/write bit is not
RO1 modified by hardware, nor does its value affect hardware.
Offset + 0 13 Wrap. Written by user.
W 0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ERDSR.n
Offset + 0 12 Receive software ownership. This field is reserved for use by software. This read/write bit is not
RO2 modified by hardware, nor does its value affect hardware.
Offset + 0 11 Last in frame. Written by the FEC.
L 0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
26-31
13 12 11 10 9
W RO2 L — —
Rx Data Buffer Pointer - A[31:16]
Rx Data Buffer Pointer - A[15:0]
Figure 26-25. Receive Buffer Descriptor (RxBDn)
Table 26-29. Receive Buffer Descriptor Field Definitions
due to an error condition. The status and length fields have been updated as required.
8 7 6 5
M BC MC LG NO
Data Length
Description
4 3 2 1 0
— CR OV TR
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