Cpushl Enhancements - Freescale Semiconductor MCF54455 Reference Manual

Table 6-8. Data Cache Line State Transitions (Current State Valid) (continued)
Access
Cache push
Cache push
In Table 6-9 the current state is modified.
Table 6-9. Data Cache Line State Transitions (Current State Modified)
Access
Read miss CD1 Push modified line to buffer;
Read hit CD2 Supply data to processor;
Write miss CD3 Push modified line to buffer;
(copyback)
Write miss WD3 Write data to memory;
(write-through)
Write hit CD4 Write data to cache;
(copyback)
Write hit WD4 Write data to memory and to cache;
(write-through)
Cache invalidate CD5 No action (modified data lost);
Cache push CD6 Push modified line to memory;
Cache push CD7 Push modified line to memory;
6.4.8

CPUSHL Enhancements

The extended CPUSHL functionality adds two new bits in the cache control register (CACR) to support a
set search using a physical address. In particular, the added CACR bits are defined as:
cacr[14] = cacr[SPA] cpushl Search by physical address
cacr[20] = cacr[IVO] cpushl Invalidate only
Freescale Semiconductor
(C,W)V6 No action;
go to invalid state.
(C,W)V7 No action;
stay in valid state.
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
stay in modified state.
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
stay in modified state.
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state, execute
a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
go to invalid state.
go to invalid state.
go to valid state.
Response
Response
Cache
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