Freescale Semiconductor MCF54455 Reference Manual page 155

Cache
31
Tag Data/Tag Reference
The following steps determine if a data-cache line for a given address is allocated:
1. The cache set index, A[11:4], selects one cache set.
2. A[31:12] and the cache set index are used as a tag reference or to update the cache line tag field.
A[31:12] can specify 20 possible address lines that can be mapped to one of the four ways.
3. The four tags from the selected cache set are compared with the tag reference. A cache hit occurs
if a tag matches the tag reference and the V bit is set, indicating that the cache line contains valid
data. If a cacheable write access hits in a valid cache line, the write can occur to the cache line
without loading it from memory.
If the memory space is copyback, the updated cache line is marked modified (M = 1), because the
new data made the data in memory stale. If the memory location is write-through, the write is
passed to system memory and the M bit is not used. The tag does not have TT or TM bits.
To allocate a cache entry, the cache set index selects one of the cache's 256 sets. The cache control logic
looks for an invalid cache line to use for the new entry. If none are available, the cache controller uses a
pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First, the
cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit
replacement counter chooses the way. After a line is allocated, the pointer increments to point to the next
way.
Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If
CACR[DHLCK,IHLCK] are set, the replacement pointer is restricted to way 2 or 3.
6-10
Address
12 11
4 3
Index
Set 0
Set 1
Set Select
A[11:4]
•
•
•
Set 255
Address
A[31:12]
Comparator
Figure 6-6. Data-Caching Operation
0
Way 3
Way 2
Way 1
Way 0
TAG STATUS LW0 LW1 LW2 LW3
• • • •
• • • •
• • • •
TAG STATUS LW0 LW1 LW2 LW3
3
2
Hit 3
1
Hit 2
Hit 1
0
Hit 0
• •
• •
• •
Data
MUX
Line Select
Hit
Logical OR
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