Dspi Dma/Interrupt Request Select And Enable Register (Dspi_Rser) - Freescale Semiconductor MCF54455 Reference Manual

DMA Serial Peripheral Interface (DSPI)
Field
15–12 TX FIFO counter. Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time the
TXCTR DSPI _PUSHR is written. The TXCTR is decremented every time an SPI command is executed and the SPI data is
transferred to the shift register.
11–8 Transmit next pointer. Indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR field is
TXNXTPTR updated every time SPI data is transferred from the TX FIFO to the shift register. See
Buffering Mechanism,"
7–4 RX FIFO counter. Indicates the number of entries in the RX FIFO. The RXCTR is decremented every time the
RXCTR DSPI_POPR is read. The RXCTR is incremented after the last incoming databit is sampled, but before the t
starts. Refer to
3–0 Pop next pointer. Contains a pointer to the RX FIFO entry that is returned when the DSPI_POPR is read. The
POPNXTPTR POPNXTPTR is updated when the DSPI_POPR is read. See
more details.
31.3.5 DSPI DMA/Interrupt Request Select and Enable Register
(DSPI_RSER)
The DSPI_RSER serves two purposes. It enables flag bits in the DSPI_SR to generate DMA requests or
interrupt requests. The DSPI_RSER also selects the type of request to be generated. See the individual bit
descriptions for information on the types of requests the bits support. Do not write to the DSPI_RSER
while the DSPI is running.
Address 0xFC05_C030 (DSPI_RSER)
:
31 30 29
R TCF 0 0
_RE
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Figure 31-6. DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
Field
31 Transmission complete request enable. Enables DSPI_SR[TCF] flag to generate an interrupt request.
TCF_RE 0 TCF interrupt requests are disabled
1 TCF interrupt requests are enabled
30–29 Reserved, must be cleared.
31-16
Table 31-6. DSPI_SR Field Descriptions (continued)
for more details.
Section 31.4.4.1, "Classic SPI Transfer Format (CPHA =
28 27 26 25
0
EOQF TFUF TFFF
_RE _RE _RE
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
Table 31-7. DSPI_RSER Field Descriptions
Description
0)" for details.
Section 31.4.2.5, "RX FIFO Buffering
24 23 22 21
0 0 0
TFFF
_DIRS
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Description
Section 31.4.2.4, "TX FIFO
ASC
Mechanism" for
Access: User Read/Write
20 19 18 17
0 0
RFOF RFDF RFDF
_RE _RE _DIRS
0 0 0 0
4 3 2 1
0 0 0 0
0 0 0 0
Freescale Semiconductor
delay
16
0
0
0
0