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MSC8144E SC3400 DSP Subsystem
10.9.4 WAIT State
This state is entered by executing the WAIT instruction on the SC3400 core, which enters the
WAIT processing state. During this state, all the SC3400 core clocks are stopped. In addition, the
clocks of most of the DSP core subsystem components are stopped. The only DSP core
subsystem blocks that receive an active clock during WAIT state are those that are involved in
waking up the DSP core subsystem from this state. These modules are: the EPIC, the Timer, the
DPU.
The WAIT State is an intermediate power-saving state, consuming more power than the STOP
state, but less than Execution state. The platform exits WAIT state when an enabled interrupt
request is asserted, or the platform is transferred to Debug state, or to Reset state.
10.9.5 STOP State
This state is entered by executing the STOP instruction on the SC3400 core, which enters the
STOP processing state. During the STOP state, all DSP core subsystem clocks are stopped. Only
very limited logic that is required to wake up from STOP state receives an active clock. This state
has the lowest power consumption for the DSP core subsystem.
Whenever the STOP command is issued to the SC3400 core, a hardware request-acknowledge
signal protocol is initiated between the blocks of DSP core subsystem and the external
environment in order to ensure that the platform is idle, and for the external environment to
acknowledge that the platform can enter STOP state. The platform exits STOP state when a
dedicated input is asserted from outside the platform, or when the platform is transferred to
Debug state or to Reset state. See the SC3000 DSP Core Reference Manual for details about the
STOP processing state and conditions for exiting it.
Note:
In STOP processing state, the EPIC clocks are stopped. The EPIC serves as the
combinatorial collector of all the enabled interrupts with priority larger than 0. The
EPIC performs a logic OR operation for all the interrupt inputs. The output from OR
operand is used to wake the core from STOP mode. Therefore, any enabled level
interrupt causes the platform to wake from STOP state. You cannot use edge interrupts
to wake the DSP core subsystem from STOP mode; therefore, disable all edge
interrupts prior to entering the STOP state.
Note:
The STOP instruction only stops operation of the SC3400 core. To stop the entire
SC3400 DSP core subsystem, you must set the respective GCR2[COREn_STP_EN]
bit (see Section 8.2.2, General Configuration Register 2 (GCR2), on page 8-3 for
details). After setting the bit, the core subsystem does not stop until the corresponding
GCR1[COREn_STP_ACK] bit is set (see Section 8.2.3, General Status Register 1
(GSR1), on page 8-4 for details).
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MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
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