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Chip Configuration Module (CCM)
Address: 0xFC0A_0008 (RCON)
15
14
R
0
0
W
Reset
0
0
Address: 0xFC0A_0008 (RCON)
15
14
13
R
0
0
0
W
Reset
0
0
0
11.3.3
Chip Identification Register (CIR)
Address: 0xFC0A_000A (CIR)
15
14
13
R
W
Reset
Field
15–6
Part identification number. Contains a unique identification number for the device.
PIN
0x04F MCF54450
0x04D MCF54451
0x04B MCF54452
0x049 MCF54453
0x04A MCF54454
0x048 MCF54455
5–0
Part revision number. This number increases by one for each new full-layer mask set of this part. The revision
PRN
numbers are assigned in chronological order.
11.3.4
Miscellaneous Control Register (MISCCR)
The MISCCR register provides clock source selection and configuration for internal clocks, as well as
SSI/timer DMA mux control and other miscellaneous control functionality.
11-8
13
12
11
10
0
0
0
0
0
0
0
0
Figure 11-4. Reset Configuration Register (RCON) 360-pin
12
11
10
9
0
0
0
1
0
0
0
1
Figure 11-5. Reset Configuration Register (RCON) 256-pin
12
11
10
9
PIN
Device Dependent
Figure 11-6. Chip Identification Register (CIR)
Table 11-6. CIR Field Descriptions
9
8
7
6
1
1
FBCONFIG
1
1
1
1
8
7
6
5
1
FBCONFIG
1
0
1
0
8
7
6
5
Description
Access: Supervisor read-only
5
4
3
2
PLL
PCI
PCI
MODE
MODE
SLEW
1
0
1
1
Access: Supervisor read-only
4
3
2
1
PLL
OSC
PLLMULT
MODE
MODE
0
0
1
1
Access: Supervisor read-only
4
3
2
1
PRN
Mask Set Dependent
Freescale Semiconductor
1
0
PLLMULT
0
1
0
0
0
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