Freescale Semiconductor MCF54455 Reference Manual page 874

The sequence is as follows:
• In cycle 1, the development system command is issued (
responds with the low-order results of the previous command or a command complete status of the
previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The debug module
returns a not-ready response unless the received command is decoded as unimplemented, which is
indicated by the illegal command encoding. If this occurs, the development system should
retransmit the command.
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
• In cycle 3, the development system supplies the low-order 16 address bits. The debug module
always returns a not-ready response.
• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial
transfers that begin during a memory access return a not-ready response.
• Results are returned in the two serial transfer cycles after the memory access completes. For any
command performing a byte-sized memory read operation, the upper 8 bits of the response data are
undefined and the referenced data is returned in the lower 8 bits. The next command's opcode is
sent to the debug module during the final transfer. If a bus error terminates a memory or register
access, error status (S = 1, DATA = 0x0001) returns instead of result data.
34.4.1.5 BDM Command Set
Table 34-25 summarizes the BDM command set. Subsequent sections contain detailed descriptions of
each command. Issuing a BDM command when the processor is accessing debug module registers using
the WDEBUG instruction causes undefined behavior. See
Freescale Semiconductor
in this example). The debug module
READ
NOTE
Table 34-26 for register address encodings.
Debug Module
34-32