Ssi Transmit Fifo 0 And 1 Registers - Freescale Semiconductor MCF54455 Reference Manual

27.3.2

SSI Transmit FIFO 0 and 1 Registers

The SSI transmit FIFO registers are 15x32-bit registers. These registers are not directly accessible. The
transmit shift register (TXSR) receives its values from these FIFO registers. When the transmit interrupt
enable (SSI_IER[TIE]) bit and either of the transmit FIFO empty (SSI_ISR[TFE0, TFE1]) bits are set, an
interrupt is generated when the data level in of the SSI transmit FIFOs falls below the selected threshold.
27.3.3 SSI Transmit Shift Register (TXSR)
TXSR is a 24-bit shift register that contains the data transmitted and is not directly accessible. When a
continuous clock is used, the selected bit clock shifts data out to the SSI_TXD pin when the associated
frame sync is asserted. When a gated clock is used, the selected gated clock shifts data out to the SSI_TXD
port.
The word length control bits (SSI_CCR[WL]) determine the number of bits to shift out of the TXSR before
it is considered empty and can be written to again. The data to be transmitted occupies the most significant
portion of the shift register if SSI_TCR[TXBIT0] is cleared. Otherwise, it occupies the least significant
portion. The unused portion of the register is ignored.
If TXBIT0 is cleared and the word length is less than 16 bits, data occupies
the most significant portion of the lower 16 bits of the transmit register.
When SSI_TCR[SHFD] is cleared, data is shifted out of this register with the most significant bit (msb)
first. If this bit is set, the least significant bit (lsb) is shifted out first. The following figures show the
transmitter loading and shifting operation. They illustrate some possible values for WL, which can be
extended for the other values.
31
16 bits
20 bits
24 bits
31
16 bits
SSI_TXD
Figure 27-5. Transmit Data Path (TXBIT0=0, TSHFD=0) (msb Alignment)
Freescale Semiconductor
NOTE
15 11 7
12 bits
12 bits
Synchronous Serial Interface (SSI)
0
SSI_TX
0
TXSR
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