Reads From Local Memory - Freescale Semiconductor MCF54455 Reference Manual

(PCI space). When a hit on PCI base address ranges (0 through 5), the upper bits of the address are written
over by this register value to address some space in the processor. One 256-Kbyte base address range
(BAR0) maps to non-prefetchable local memory and the rest (BAR1–5) target to prefetchable memory.
Prefetching for PCI reads performs if the PCITCR1[PID] bit clears and the PCI command is a
or the PCITCR1[P] bit sets and the read address falls in the range of prefetchable memory
READ MULTIPLE
space.
22.4.4.1

Reads from Local Memory

The PCI controller implements delayed reads when accessed as a target device. The following sequence
of events occur for every delayed read:
1. The read attempt, if valid, latches as a delayed request.
2. Before performing the read on the internalbus, all previously posted writes moving across the target
interface complete first on the internal bus.
3. The read performs on the internal bus and queues in a target read buffer.
4. All posted writes moving in the initiator direction and posted before the read occurs on the internal
bus complete to the external PCI target.
5. The queued target read data permits to be sent back to the external PCI master when re-attempted.
The external master requires to re-attempt the target read.
After a delayed read completes on the internal bus, it may be discarded due to a tardy master. If the master
that initiated the transaction does not retry the transaction in 2
PCIGSCR[DRD] status bit sets.
For prefetchable memory (BAR1–5 space), internal bus can fetch extra data to increase target read
performance. Prefetching performs for BAR addressed transactions if the PCITCR1[PID] bit clears and
the PCI command is a
MEMORY READ MULTIPLE
latches and prefetching is enabled, up to 16-bytes are fetched, if possible. The first 4 bytes is the delayed
request and the next 28 bytes are prefetched. This data is stored in the first cacheline size read buffer. If no
new target writes are transferred and no internal bus initiated memory writes to the PCI bus get posted,
memory can fetch the next 3 lines in anticipation of the next PCI request and store in the second cacheline
size read buffer. All prefetch data is invalidated when memory writes post in either direction across the
PCI controller or when the PCITCR1[PID] is set. The prefetch data is any data outside the initial 4-byte
PCI read requested by the external master and latched as a delayed request.
If a subsequent beat of a PCI read burst is requested and not stored in a read buffer, delayed or prefetched,
the subsequent data phase disconnects without data transfer and is not treated as a delayed request. The
external PCI master, if prefetching, may choose not to repeat the subsequent data phase as a new request
and discard.
When an internal error (bus error response to the SCM) occurs on a read in delayed mode on the internal
bus, it is not directly sent back to the PCI bus. It is stored in an interim register sent back when the external
PCI master re-attempts the read. A target abort is issued to the PCI bus if the error occurred on the delayed
read request. If prefetching is enabled and an error occurs on the prefetched access on the cache line of the
delayed read access, it only generates a target abort if the error occurs prior to when the delayed read is
sent to the external PCI master. Otherwise, the PCI controller does not store the prefetched data. If the next
Freescale Semiconductor
15
PCI clocks, delayed read discards and the
or the PCITCR1[P] bit is set. When a delayed request
PCI Bus Controller
MEMORY
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