Table of Contents
Advertisement
Synchronous Serial Interface (SSI)
Table 27-26. SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2 (continued)
SSI_CLKIN
freq (MHz)
(SSI_MCLK)
12.288
12.288
12.288
12.288
12.288
12.288
Table 27-27
shows the example of programming clock controller divider ratio to generate the SSI_MCLK
and SSI_BCLK frequencies close to the ideal sampling rates. In these examples, setting the SSI to I
master mode (SSI_CR[I2S] = 01) or individually programming the SSI into network, transmit internal
clock mode selects the master mode. (The table specifically illustrates the I
rates.)
2
I
S master mode requires a 32-bit word length, regardless of the actual data type. Consequently, the fixed
2
I
S frame rate of 64 bits per frame (word length (WL) can be any value) and DC = 1 are assumed.
Table 27-27. SSI Sys Clock, Bit Clock, Frame Clock in Master Mode
Sampling
/Frame
rate (kHz)
11.025
27.4.3
External Frame and Clock Operation
When applying external frame sync and clock signals to the SSI module, at least four bit clock cycles
should exist between the enabling of the transmit or receive section and the rising edge of the
corresponding frame sync signal. The transition of SSI_FS should be synchronized with the rising edge of
external clock signal, SSI_BCLK.
27.4.4
Supported Data Alignment Formats
The SSI supports three data formats to provide flexibility with managing data. These formats dictate how
data is written to and read from the data registers. Therefore, data can appear in different places in
SSI_TX0/1 and SSI_RX0/1 based on the data format and the number of bits per word. Independent data
formats are supported for the transmitter and receiver (i.e. the transmitter and receiver can use different
data formats).
27-50
SSI_CCR
DIV2 PSR
PM
0
0
5
0
0
3
0
0
23
0
0
11
0
0
5
0
0
3
Over-
SSI_CLKIN
sampling
freq (MHz)
rate
(SSI_MCLK)
44.10
384
16.934
22.05
384
16.934
384
16.934
48.00
256
12.288
Bit Clk (kHz)
Frame rate
SSI_BCLK
WL
DC
3
3
1024
3
3
1536
7
3
256
7
3
512
7
3
1024
7
3
1536
SSI_CCR
Bit Clk (kHz)
SSI_BCLK
DIV2 PSR PM
0
0
2
2822.33
0
0
5
1411.17
0
0
11
705.58
0
0
1
3072
(kHz)
32
48
4
8
16
24
2
S mode frequencies/sample
Freescale Semiconductor
2
S
Advertisement
Table of Contents
