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MCF52211 ColdFire

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52210

MCF52211

MCF52212

MCF52213

Document Number: MCF52211RM

Rev. 2

09/2007

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Summary of Contents for Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213

Page 1 ® MCF52211 ColdFire Integrated Microcontroller Reference Manual Devices Supported: MCF52210 MCF52211 MCF52212 MCF52213 Document Number: MCF52211RM Rev. 2 09/2007...
Page 2 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 3: Table Of Contents
2.13 General Purpose Timer Signals ..........2-11 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 1...
Page 4 5.1.1 Overview ............5-1 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 3...
Page 5 Functional Description ............7-6 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 6...
Page 6 10.6.2 Reset Control Flow ........... 10-7 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 8...
Page 7 13.3 Features ..............13-2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 11...
Page 8 15.4.1 Capability Registers ..........15-10 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 14...
Page 9 18.1.1 Overview ............18-1 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 16...
Page 10 21.3 Block Diagram ............. . 21-2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 19...
Page 11 22.1.2 Features ............22-2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 22...
Page 12 24.1.1 Overview ............24-1 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 23...
Page 13 25.3.6 Repeated START ........... . 25-10 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 25...
Page 14 26.5.11Supply Pins VDDA and VSSA ......... 26-38 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 26...
Page 15 28.6.1 Theory of Operation ..........28-39 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 27...
Page 16 B.2 Changes between Rev. 0 and Rev. 1 ..........31-2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 29...
Page 17: Mcf52211 Coldfire® Integrated Microcontroller Reference Manual,
Clock module with 8 MHz on-chip relaxation oscillator and integrated phase-locked loop (PLL) To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com/coldfire. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C) bus controllers ® Table 1-1.
Page 18: Mcf52211 Family Configurations
• • • • • • • • • • • • • 64 LQFP/QFN 64 LQFP 81 MAPBGA 100 LQFP Freescale Semiconductor 52213 • • • • • • • • • • • • • • 64 LQFP...
Page 19: Block Diagram
Part Numbers and Packaging Table 1-2 summarizes the features of the MCF52211 product family. Several speed/package options are available to match cost- or performance-sensitive applications. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Slave Mode Access (CIM_IBO/EzPort) Arbiter Interrupt...
Page 20: Features
64 / 8 64 LQFP 64 / 8 64 LQFP 128 / 8 64 LQFP 128 / 8 64 LQFP Freescale Semiconductor Temp range (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85...
Page 21 — Programmable bit rates up to half the CPU clock frequency — Up to 16 pre-programmed transfers • Fast analog-to-digital converter (ADC) — Eight analog input channels MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C bus Overview...
Page 22 — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown • Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down • Real-Time Clock (RTC) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 23 — Bursting and cycle steal support — Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4) • Reset — Separate reset in and reset out signals — Seven sources of reset: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Overview...
Page 24: Integrated Debug Module
Integrated Debug Module The ColdFire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. Through a standard debug interface, access to debug information and MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 25: Jtag
Bypass the MCF52211 for a given circuit board test by effectively reducing the boundary-scan register to a single bit • Disable the output drive to pins during circuit-board testing • Drive output pins to stable levels MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Overview...
Page 26: On-Chip Memories
PC. The dual-mode controller on the MCF52211 can act as a USB OTG host and as a USB device. It also supports full-speed and low-speed modes. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 27: Dma Timers (Dtim0–Dtim3)
8-bit prescaler that clocks the actual timer counter MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C modules. The I C bus is a two-wire, bidirectional serial bus that provides...
Page 28: Periodic Interrupt Timers (Pit0 And Pit1)
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 1-12 Freescale Semiconductor...
Page 29: Reset
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Overview 1-13...
Page 30: Gpio
Nearly all pins on the MCF52211 have general purpose I/O capability and are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 1-14 Freescale Semiconductor...
Page 31: Introduction
Active-low signals, such as SRAS and TA, are indicated with an overbar. Overview Figure 2-1 shows the block diagram of the device with the signal interface. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE Signal Descriptions...
Page 32: Pin Functions
V2 ColdFire CPU 16 Kbytes 128 Kbytes SRAM Flash (2K×32)×2 (16K×16)×4 STBY PLL OCO PIT0 CLKGEN EXTAL XTAL CLKOUT QSPI SDAn SCLn UTXDn URXDn URTSn UCTSn Watch PWMn DTINn/DTOUTn RCON_B ALLPST DDATA CLKMOD PORTS CIM_IBO RSTI RSTO PIT1 Freescale Semiconductor...
Page 33 Table 2-1. Pin Functions by Primary and Alternate Purpose Primary Secondary Tertiary Group Function Function Function — — — — — — — — SYNCA — SYNCB — VDDA — VSSA — — — Clock EXTAL — Generation XTAL — VDDPLL —...
Page 34 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Primary Secondary Tertiary Group Function Function Function Interrupts IRQ7 — IRQ6 — IRQ5 — IRQ4 — IRQ3 — IRQ2 — IRQ1 SYNCA USB_ALT_C JTAG/BDM JTAG_EN — TCLK/ CLKOUT PSTCLK TDI/DSI —...
Page 35 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Primary Secondary Tertiary Group Function Function Function QSPI QSPI_DIN/ — URXD1 EZPD QSPI_DOUT — UTXD1 /EZPQ QSPI_CLK/ URTS1 EZPCK QSPI_CS3 SYNCA QSPI_CS2 — QSPI_CS1 — QSPI_CS0 UCTS1 Reset RSTI — RSTO —...
Page 36 Table 2-1. Pin Functions by Primary and Alternate Purpose (continued) Primary Secondary Group Function Function Function UART 1 UCTS1 SYNCA URTS1 SYNCB URXD1 — UTXD1 — UART 2 UCTS2 — URTS2 — URXD2 — UTXD2 — VSTBY VSTBY — VDDUSB —...
Page 38: Pll And Clock Signals
During this mode, the EzPort has access to the flash memory which can be programmed from an external device. Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. Freescale Semiconductor...
Page 39: External Interrupt Signals
Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active Chip Selects MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 2-5. Clocking Modes Configure the Clock Mode PLL disabled, clock driven by external oscillator...
Page 40: Uart Module Signals
RxFIFO level. Table 2-10. DMA Timer Signals Function Event input to the DMA timer modules. Programmable output from the DMA timer modules. C interface. It is driven by the Freescale Semiconductor...
Page 41: General Purpose Timer Signals
TRST Test Clock TCLK Test Mode Select MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 2-11. ADC Signals Inputs to the ADC. Reference voltage high and low inputs. Isolate the ADC circuitry from power supply noise Table 2-12. GPT Signals Inputs to or outputs from the general purpose timer module Table 2-13.
Page 42 Indicate core status. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0]. Logical AND of PST[3.0] Freescale Semiconductor...
Page 43: Ezport Signal Descriptions
PLL Analog Supply VDDPLL, VSSPLL Positive Supply Ground MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 2-15. EzPort Signal Descriptions Abbreviation EZPCK Shift clock for EzPort transfers EZPCS Chip select for signaling the start and end of...
Page 44 Signal Descriptions MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 2-14 Freescale Semiconductor...
Page 45: Overview
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Instruction Address...
Page 46: Memory Map/Register Description
MAC registers (described fully in — One 32-bit accumulator(ACC) register — One 16-bit mask register (MASK) — 8-bit Status register (MACSR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Table 3-1 lists the processor registers. Chapter 4, “Multiply-Accumulate Unit (MAC)”): Freescale Semiconductor...
Page 47 (OTHER_A7) 0x801 Vector Base Register (VBR) 0x80E Status Register (SR) 0xC04 Flash Base Address Register (FLASHBAR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Width Access Reset Value (bits) Supervisor/User Access Registers 0xCF20_C089 0x10A0_1070 0x0000_0004 Supervisor Access Only Registers...
Page 48: Address Registers (A0–A6)
Data Section 3.3.4.15, “Reset Exception” Figure 3-2. Data Registers (D0–D7) Address Figure 3-3. Address Registers (A0–A6) Written with Reset Value Section/Page MOVEC See Section 3.2.8/3-8 Access: User read/write BDM read/write Access: User read/write BDM read/write Freescale Semiconductor...
Page 49: Condition Code Register (Ccr)
The extend bit (X) is also an input operand during multiprecision arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare (CMP), Bcc, or Scc instructions are executed. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE instruction before any move.l Ay,USP...
Page 50: Vector Base Register (Vbr)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 — — Figure 3-5. Condition Code Register (CCR) Table 3-2. CCR Field Descriptions Description Address Figure 3-6. Program Counter Register (PC) Access: User read/write BDM read/write — — Access: User read/write BDM read/write Freescale Semiconductor —...
Page 51: Status Register (Sr)
Reserved, must be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3-7. Vector Base Register (VBR) Figure 3-8.
Page 52: Functional Description
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Description (CCR)”. (FLASHBAR)”. 3-1, the non-Harvard architecture of the processor is readily apparent. Core Bus Address Core Bus Read Data Section 18.3.2, Figure 3-9 Opword Extension 1 FIFO Extension 2 Freescale Semiconductor...
Page 53 Consider the operation of the OEP for three basic classes of non-branch instructions: • Register-to-register: Ry,Rx • Embedded load: <mem>y,Rx • Register-to-memory (store) move Ry,<mem>x MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DSOC AGEX ColdFire Core Core Bus Address Core Bus Write Data...
Page 54 <ea>y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-10 Operand Execution Pipeline DSOC AGEX Figure 3-11. V2 OEP Register-to-Register Figure 3-11. new Rx Core Bus Address Core Bus Write Data Freescale Semiconductor...
Page 55 See <ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Operand Execution Pipeline DSOC Figure 3-12. V2 OEP Embedded-Load Part 1...
Page 56 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-12 Operand Execution Pipeline DSOC Figure 3-14. V2 OEP Register-to-Memory Figure 3-15 depict the execution templates for these three classes of AGEX <ea>x Core Bus Address Core Bus Write Data Freescale Semiconductor...
Page 57: Instruction Set Architecture (Isa_A+)
ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor next next AGEX ColdFire Core next...
Page 58: Exception Processing Overview
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to by the supervisor stack pointer (SSP). As shown in MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-14 Description Section 3.3.4.1, Figure 3-16, the processor uses a simplified Freescale Semiconductor...
Page 59 Vector Number(s) 6–7 15–23 25–31 32–47 48–63 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 14, “Interrupt Controller Module” Table 3-5. Exception Vector Assignments Stacked Vector Program Offset (Hex) Counter 0x000 —...
Page 60: Exception Stack Frame Definition
Table 3-6. Format Field Encodings SSP @ 1st Instruction of Handler Original SSP - 8 Original SSP - 9 Original SSP - 10 Original SSP - 11 Assignment Device-specific interrupts Status Register Table 3-6. Format Field 0100 0101 0110 0111 Table 3-7. Freescale Semiconductor...
Page 61: Processor Exceptions
All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 3-7. Fault Status Encodings Definition...
Page 62: Illegal Instruction Exception
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) Logical OR (OR) Subtract (SUB), Subtract Extended (SUBX) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-18 OpMode Table 3-8. ColdFire Opword Line Definition Instruction Class Figure 3-17. The opword line Effective Address Mode Register Freescale Semiconductor...
Page 63: Privilege Violation
PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Instruction Class ColdFire Core 3-19...
Page 64: Rte And Format Error Exception
(4) transfers control to the instruction address defined by the second longword operand within the stack frame. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-20 for a detailed explanation of this exception, which is generated in Freescale Semiconductor...
Page 65: Trap Instruction Exception
PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor for details. Chapter 14, “Interrupt Controller Module,”...
Page 66 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-22 Description Figure 3-18. Access: User read-only BDM read-only DEBUG Freescale Semiconductor...
Page 67 BDM: Load: 0x081 (D1) Store: 0x181 (D1) CLSZ CCAS Reset MBSZ UCAS Reset Figure 3-19. D1 Hardware Configuration Info MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description CCSZ FLASHSZ SRAMSZ ColdFire Core Access: User read-only BDM read-only 3-23...
Page 68 0101 8 Kbytes 0110 16 Kbytes 0111 32 Kbytes (This is the value used for this device) 1000 64 Kbytes 1001 128 Kbytes Else Reserved for future use Reserved. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-24 Description Freescale Semiconductor...
Page 69: Instruction Execution Timing
The processor core decomposes misaligned operand references into a series of aligned accesses as shown in Table 3-11. address[1:0] 01 or 11 01 or 11 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 3-11. Misaligned Operand References Size Operations Word Byte, Byte Long Byte, Word,...
Page 70: Move Instruction Execution Times
— — — — — — — — 3(1/1) — — — — — — — — (d16,Ax) (d8,Ax,Xi*SF) xxx.wl 1(0/1) 2(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) — — Freescale Semiconductor...
Page 71: Standard One Operand Instruction Execution Times
1(0/0) NOT.L 1(0/0) 1(0/0) SWAP 1(0/0) TST.B <ea> 1(0/0) TST.W <ea> 1(0/0) TST.L <ea> 1(0/0) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Destination (Ax) (Ax)+ -(Ax) 3(1/1) 3(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1)
Page 72: Standard Two Operand Instruction Execution Times
23(1/0) 20(0/0) 24(1/0) 23(1/0) 20(0/0) — — — — — — 4(1/1) 3(1/1) — — — — 2(0/0) 1(0/0) — — — 1(0/0) — — 1(0/0) — — 1(0/0) 4(1/0) 3(1/0) 1(0/0) 4(1/1) 3(1/1) — — — — Freescale Semiconductor...
Page 73: Miscellaneous Instruction Execution Times
— TRAP #imm — 1(0/0) TPF.W 1(0/0) TPF.L 1(0/0) UNLK 2(1/0) WDDATA <ea> — MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) —...
Page 74: Mac Instruction Execution Times
— — — — — — — — — — — — — 4(1/0) — — — 2(1/0) — — — 7(1/0) — — — 5(1/0) 6(1/0) 5(1/0) 3(0/0) 7(1/0) — — — 5(1/0) 6(1/0) 5(1/0) 3(0/0) Freescale Semiconductor —...
Page 75: Branch Instruction Execution Times
Opcode <EA> — — <ea> — <ea> — — — Table 3-19. Bcc Instruction Execution Times Opcode MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) — — — 2(0/1) — —...
Page 76 ColdFire Core MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 3-32 Freescale Semiconductor...
Page 77: Introduction
The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor (Figure 4-1).
Page 78: Memory Map/Register Definition
2 ( )x i 2 – Table 4-1. MAC Memory Map Width Register (bits) Equation 4-1. b 3 ( )x i 3 – – Access Reset Value Section/Page 0x0000_0000 4.2.1/4-2 0xFFFF_FFFF 4.2.2/4-4 Undefined 4.2.3/4-5 Freescale Semiconductor Eqn. 4-1 Eqn. 4-2...
Page 79 Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 4-2. MAC Status Register (MACSR) Table 4-2. MACSR Field Descriptions Description Section 4.3.1.1,...
Page 80: Mask Register (Mask)
No round on accumulator stores Signed, fractional Round on MAC.L and MSAC.L No round on accumulator stores Unsigned, integer Signed, fractional Truncate on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Signed, fractional Round on MAC.L and MSAC.L Round-to-16-bits on accumulator stores Freescale Semiconductor...
Page 81: Accumulator Register (Acc)
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 4-3. Mask Register (MASK) Table 4-4.
Page 82: Functional Description
MAC + MOVE instructions. The register application with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Table 4-5. ACC Field Descriptions Description Freescale Semiconductor...
Page 83: Fractional Operation Mode
MAC registers are accessed. Consider the memory structure containing the MAC programming model: struct macState { int acc; int mask; MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor /* R0.L = 0x8000 */ Multiply-Accumulate Unit (MAC)
Page 84: Mac Instruction Set Summary
Multiplies two operands, combines the product to the accumulator while loading a register with the memory operand Loads the accumulator with a 32-bit operand Writes the contents of the accumulator to a CPU register Description Freescale Semiconductor...
Page 85: Mac Instruction Execution Times
32-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with the accumulator cannot be represented in the given number of bits. This indicator is MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Mnemonic Writes a value to MACSR...
Page 86 (MACSR.OMC == 1) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 4-10 (MACSR)”. /* product overflow */ then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000 then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[31:0] = 0x8000_0000 Freescale Semiconductor...
Page 87 (result[31:0] == 0x0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor else result[31:0] = 0x7fff_ffff /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” */ if (inst == MSAC &&...
Page 88 2: /* unsigned integers */ MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 4-12 then product[63:32] = product[63:32] + 1 saturationMode enabled */ if (result[31] == 1) then result[31:0] = 0x7fff_ffff else result[31:0] = 0x8000_0000 0x0000} 0x0000} Freescale Semiconductor...
Page 89 = {0, product[31:1]} break; /* combine with accumulator */ if (MACSR.V == 0) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor /* product overflow */ then /* overflowed MAC, saturationMode enabled */ result[31:0] = 0xffff_ffff /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<<...
Page 90 = result[31:0] MACSR.N = result[31] if (result[31:0] == 0x0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break;} MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 4-14 then /* overflowed MAC, saturationMode enabled */ result[31:0] = 0xffff_ffff Freescale Semiconductor...
Page 91: Register Descriptions
Byte, word, and longword address capabilities Memory Map/Register Description The SRAM programming model shown in register (RAMBAR), SRAM initialization, and power management. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 5-1 includes a description of the SRAM base address...
Page 92: Sram Base Address Register (Rambar)
(bits) Supervisor Access Only Registers Table 5-2. RAMBAR Field Descriptions Description Written Access Reset Value w/ MOVEC See Section Figure 5-1. Access: User write-only PRIU PRIL SPV WP C/I SC SD UC UD V Freescale Semiconductor Section/Page 5.2.1/5-2 Debug read/write...
Page 93: Initialization/Application Information
If the SRAM requires initialization with instructions or data, perform the following steps: 1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description PRIU,PRIL Upper Bank Priority Section 12.5.2, “Memory Base Address Register (RAMBAR).”...
Page 94: Power Management
;clear 4 bytes of SRAM ;clear 4 bytes of SRAM ;clear 4 bytes of SRAM ;decrement loop counter ;if done, then exit; else continue looping Table 5-3 shows examples of typical RAMBAR settings. RAMBAR[7:0] Instruction Only Data Only 0x2B 0x35 0x21 Freescale Semiconductor...
Page 95: Modes Of Operation
POR. Thus, if the relaxation oscillator is selected as the timer’s input source, subsequent attempts to select the relaxation oscillator as the system clock’s source are blocked until the MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 96: Low-Power Mode Operation
Exit not caused by clock module, but normal clocking resumes upon mode exit Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit Exit not caused by clock module shows the clock module Mode Exit Freescale Semiconductor...
Page 97: Block Diagram
RFD value plus one before entering stop mode. In external clock mode, there are no wakeup periods for oscillator startup or PLL lock. Block Diagram Figure 6-1 shows a block diagram of the entire clock module. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 98 Interrupt Controller PPRML[17] DMA Timers PPRML[16:13] QSPI PPRML[10] PPRML[9] UARTs PPRML[7:5 PPRML[4] Figure 6-1. Clock Module Block Diagram Low Power Divider STOP MODE LPD[3:0] CLKSRC PPRMH[11] PPRMH[9] PPRMH[8] PPRMH[7] PITs PPRMH[4:3] Edge Port PPRMH[1] GPIO / Ports PPRMH[0] Freescale Semiconductor...
Page 99: Signal Descriptions
These inputs are used to select the clock mode during chip configuration as described in CLKMOD[1:0] XTAL MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 6-2 and a brief description follows. For more detailed Table 6-2. Signal Properties...
Page 100: Memory Map And Registers
Supervisor Mode Access Only Section 10.5.1, “Reset Control Access Reset Value Section/Page 0x1002 6.7.1.1/6-7 0x00 6.7.1.2/6-9 See note 6.7.1.3/6-11 0x00 6.7.1.4/6-11 0x05 6.7.1.5/6-12 See note 6.7.1.6/6-12 See note 6.7.1.7/6-13 See note 6.7.1.8/6-14 0x00 6.7.1.9/6-15 0x00 6.7.1.10/6-16 0x00 8.2.1/8-2 0x01 8.2.1/8-2 Freescale Semiconductor...
Page 101: Synthesizer Control Register (Syncr)
MFD[2:0] bits or entering stop mode with the PLL disabled. 0 No reset on loss of lock 1 Reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor MFD1 MFD0 LOCRE FWKUP —...
Page 102 1/32 3/64 1/16 × 2(MFD + 2) / 2 × 2(MFD + 2) ≤ (Max_Spec) MHz, f < 3 MHz MFD[2:0] (10x) (12x) (14x) (16x) (18x) 5/16 7/16 9/16 5/32 3/16 7/32 9/32 5/64 3/32 7/64 9/64 ≤ Freescale Semiconductor...
Page 103 See note 1 Note: 1. Reset state determined during reset configuration. 2. See the LOCKS and LOCK bit descriptions. Figure 6-3. Synthesizer Status Register (SYNSR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description CRYOSC LOCKS LOCK See note 2...
Page 104 1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with FWKUP = 1 Note: The LOCS flag is always 0 in external clock mode. 1–0 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-10 Table 6-6. SYNSR Field Descriptions Description Freescale Semiconductor...
Page 105: Relaxation Oscillator Control Register (Rocr)
4 bit field). The clock change takes effect with the next rising edge of the system clock. IPSBAR Offset: 0x12_0007 (LPDR) — — Reset: Figure 6-5. Low-Power Divider Register (LPDR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor — — — — TRIM5 TRIM4 TRIM3 Table 6-7.
Page 106: Clock Control High Register (Cchr)
OSCSEL is set. Similarly, when switching the clock source to the external oscillator, OCLR[OSCEN] should be set before OSCSEL is cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-12 Table 6-8. LPDR Field Descriptions Description — — — Table 6-9. CCHR Field Descriptions Description Access: Supervisor read/write CCHR2 CCHR1 CCHR0 Freescale Semiconductor...
Page 107: Oscillator Control High Register (Ochr)
Table 6-11. CCLR[OSCSEL1] and CCLR[OSCSEL0] Settings OSCSEL1 6.7.1.7 Oscillator Control High Register (OCHR) The OCHR is used to enable and configure the relaxation oscillator. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor — — — Table 6-10. CCLR Field Descriptions Description Table 6-11.
Page 108: Oscillator Control Low Register (Oclr)
The OSCEN and REFS reset states are determined during reset configuration. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-14 — — — Table 6-12. OCHR Field Descriptions Description — LPEN RANGE Access: Supervisor read/write — — — Access: Supervisor read/write — — — Freescale Semiconductor...
Page 109 The KHZEN bit selects the operating frequency range of the oscillator KHZEN 0 Oscillator operates in the kHz range. 1 Oscillator operates in the MHz range. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 6-13. OCLR Field Descriptions Description — OSCEN KHZEN Table 6-14.
Page 110: Backup Watchdog Timer Control Register (Bwcr)
The BWCR is reset to these values only after a Power-On Reset. The register contents are preserved during a warm reset. Field 7–2 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-16 Description Module”). NOTE — — — Table 6-15. BWCR Field Descriptions Description Access: Supervisor read/write — BWDSTOP BWDSEL Freescale Semiconductor...
Page 111: Functional Description
In external clock mode, the system is static and does not recognize reset until a clock is generated from the reference clock source selected by the CLKMOD pins (see MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description sys/2 PLL Options ×...
Page 112: System Clock Generation
Actual component values depend on crystal specifications. The following subsections describe each major block of the PLL. Refer to functional sub-blocks interact. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-18 NOTE Figure 6-12 to see how these Freescale Semiconductor...
Page 113 The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge, respectively, from the loop filter. The filter is integrated on the chip. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 48 MHz CRYSTAL CONFIGURATION C1 = C2 = 18 pF RF = 1 MΩ...
Page 114 In external clock mode, the PLL is disabled and cannot lock. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-20 Figure 6-13 shows the sequence Freescale Semiconductor...
Page 115 In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the LOLRE bit has no effect. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Loss of Lock Detected Set Tight Lock Criteria...
Page 116 NOTE Table 6-18. Loss of Clock Summary Reference Failure Alternate Clock Selected by LOC Circuit Until Reset PLL self-clocked mode None Section 6.7, “Memory PLL Failure Alternate Clock Selected by LOC Circuit Until Reset PLL reference Figure 6-12. Freescale Semiconductor...
Page 117 Off Off 1 Lose lock, f.b. clock, reference clock Off On 0 Lose lock MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 6-19. Stop Mode Operation PLL Action MODE During Stop Stop — — Lose reference...
Page 118 0–>1 ‘LC ‘LC — — — 0–>1 ‘LC ‘LC — — — Reset immediately ‘LK ‘LC — — — Reset immediately ‘LK ‘LC REF not entered during stop; SCM entered during stop only during oscillator startup — — — Freescale Semiconductor...
Page 119 On On 0 On On 1 On On X Off X Lose lock, f.b. clock, reference clock MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PLL Action MODE During Stop Stop Regain No f.b. clock or Stuck lock regain...
Page 120 Comments ‘LK ‘LC — — — Reset immediately — — — ‘LC ‘LK ‘LC — — — Reset immediately 0–>1 ‘LC ‘LC ‘LK ‘LC — — — Reset immediately — — — Wakeup without lock Wakeup without lock Freescale Semiconductor...
Page 121 1–>‘LC = current value is 1 until clock is regained which then is the previous value before entering stop 1–> = current value is 1 until clock is regained but CLK is never expected to regain MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PLL Action MODE...
Page 122 Clock Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 6-28 Freescale Semiconductor...
Page 123: Modes Of Operation
Modes of Operation This section describes the operation of the BWT in low-power modes of operation. These modes are described in Chapter 8, “Power MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 7-1. IPBUS 16-bit WCNTR Divide by...
Page 124: Memory Map And Register Definition
(BWCR),” for a detailed description. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Table 7-1. BWT Memory Map Width Register (bits) Section 6.7.1.10, “Backup Watchdog Timer Control Access Reset Value Section/Page 0x02 7.2.2.1/7-3 0xFFFF 7.2.2.2/7-4 0xFFFF 7.2.2.3/7-4 0x00 7.2.2.4/7-5 0x02 6.7.1.10/6-16 Freescale Semiconductor...
Page 125 BWT Enable bit. This read-always/write-once bit enables the BWT. 0 BWT is disabled. 1 BWT is enabled. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE Section 7.2.2.2, “Backup Watchdog Timer Modulus Table 7-2. WCR Field Descriptions Description...
Page 126 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 NOTE Table 7-3. WMR Field Descriptions Description ) 4096 ⋅ ) 4096 ⋅ 7-4, reflects the current value in the BWT counter. This counter is reset to Access: Supervisor read/write ]τ ]τ Freescale Semiconductor...
Page 127 BWT service field. To service the BWT, the software must write the values 0x5555 and 0xAAAA, in that order, to this field before the BWT timeout period is reached. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 7-4. WCNTR Field Descriptions Description Table 7-5.
Page 128: Functional Description
5. To prevent a reset, service the BWT by writing 0x5555 and 0xAAAA, in that order, to the WSR before the timeout period is reached. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Section 6.7.1.10, “Backup Watchdog Timer Control Register Chapter 6, “Clock (BWCR)”) Freescale Semiconductor...
Page 129: Introduction
The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 8-1. Power Management Memory Map Register...
Page 130: Peripheral Power Management Registers (Ppmrh, Ppmrl)
PPMRH definition. IPSBAR Offset: 0x000C (PPMRH) Reset Reset Reset CDADC Reset Figure 8-1. Peripheral Power Management Register High (PPMRH) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 NOTE CDCFM CDPIT1 CDPIT0 Access: read/write CDPWM CDGPT CDEPORT CDPORTS Freescale Semiconductor...
Page 131 1 EPORT module clock is disabled Disable clock to the Ports module. CDPORTS 0 Ports module clock is enabled 1 Ports module clock is disabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 8-2. PPMRH Field Descriptions Description Power Management...
Page 132: Peripheral Power Management Register Low (Ppmrl)
TMR0 module clock is enabled TMR0 module clock is disabled 12–11 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 CDTMR0 CDUART0 CDDMA Table 8-3. PPMRL Field Descriptions Description Access: read/write CDINTC0 CDTMR3 CDQSPI CDI2C Freescale Semiconductor...
Page 133: Low-Power Interrupt Control Register (Lpicr)
STOP instruction is issued. If this field is set to enter stop mode, then the ENBSTOP bit in the LPICR must also be set. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description NOTE Power Management...
Page 134 Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the XLPM_IPL low-power mode.Refer to [2:0] MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 NOTE XLPM_IPL[2:0] Table 8-4. LPICR Field Description Description Table 8-5. Access: read/write Freescale Semiconductor...
Page 135: Peripheral Power Management Set Register (Ppmrs)
0–63 Set corresponding bit in PPMRx, disabling the module clock 64–127 Set all bits in PPMRx, disabling all the module clocks MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 8-5. XLPM_IPL Settings Interrupts Level Needed to Exit Low-Power Mode Any interrupt request exits low-power mode Interrupt request levels 2–7 exit low-power mode...
Page 136: Peripheral Power Management Clear Register (Ppmrc)
STOP instruction is issued, and controls clock activity in this low-power mode. IPSBAR Offset: 0x11_0007 (LPCR) LPMD Reset: Figure 8-6. Low-Power Control Register (LPCR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 PPMRC Table 8-7. PPMRC Field Descriptions Description STPMD Figure 8-5 Access: write-only Access: read/write LVDSE Freescale Semiconductor...
Page 137: Ips Bus Timeout Monitor
IPS module enable and continues to count until the bus cycle is terminated via the negation of ips_xfr_wait. If the programmed timeout value is reached before a termination, the bus monitor completes MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 8-8. LPCR Field Descriptions Description...
Page 138: Functional Description
During stop mode, the system clock is stopped low. For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 8-10 Table 8-9. IPSBMT Field Description Description Access: read/write Freescale Semiconductor...
Page 139: Wait Mode
Most peripherals may be disabled by software to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Power Management 8-11...
Page 140: Peripheral Behavior In Low-Power Modes
During this mode, the UART clocks are shut down. Coming out of stop mode returns the UARTs to operation from the state prior to the low-power mode entry. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 8-12 Section 8.4.1, “Low-Power Modes” for Freescale Semiconductor...
Page 141 CPU’s status register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Power Management 8-13...
Page 142: Clock Module
In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 8-14 Freescale Semiconductor...
Page 143: Summary Of Peripheral State During Low-Power Modes
Table 8-10. CPU and Peripherals in Low-Power Modes Module SRAM Flash System Control Module DMA Controller UART0, UART1 and UART2 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Peripheral Status / Wakeup Capability Wait Mode Doze Mode Stopped Stopped Stopped...
Page 144 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Program Enabled Program Enabled Enabled Program Program Enabled Enabled Enabled Enabled Stop Mode Stopped Stopped Stopped Enabled Enabled Enabled Stopped Stopped Enabled Stopped Stopped Stopped Stopped Stopped Enabled Enabled Freescale Semiconductor...
Page 145: External Signal Descriptions
TEST The use of external pull-up/down resistors is highly recommended. Refer to Chapter 6, “Clock Module” MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 9-1. Signal Properties Function Reset configuration select Clock mode select JTAG or BDM mode selection Test mode selection for more information.
Page 146: Memory Map/Register Definition
The reset configuration register (RCON) indicates the default chip configuration. • The chip identification register (CIR) contains a unique part number. Table 9-2. Write-Once Bits Read/Write Accessibility Configuration All configurations Debug operation MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Chapter 6, Read/Write Access Read-always Write-always Freescale Semiconductor...
Page 147: Memory Map
101 EzPort Mode 100 Reserved 0xx Reserved 7–0 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Width Register (bits) Supervisor Mode Access Only Unimplemented for a description of the LPCR. It is shown here only to warn against accidental writes Mode Table 9-4.
Page 148: Reset Configuration Register (Rcon)
Figure 9-3. Chip Identification Register (CIR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Table 9-5. RCON Field Descriptions Description – – – – – – Access: Supervisor read-only RLOAD Access: read-only – – – – – Freescale Semiconductor MODE –...
Page 149 Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order, beginning with zero. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 9-6. CIR Field Description Description...
Page 150 Chip Configuration Module (CCM) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 151: Introduction
LVD control and status bits for setup and use of LVD reset or interrupt 10.3 Block Diagram Figure 10-1 illustrates the reset controller and is explained in the following sections. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-1...
Page 152: Signals
Reset control register (RCR)—selects reset controller functions • Reset status register (RSR)—reflects the state of the last reset source MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 10-2 RSTI Reset Controller Input Direction Hysteresis — RSTO To Internal Resets Input Synchronization — Freescale Semiconductor...
Page 153: Reset Control Register (Rcr)
Also, LVDF is not cleared at reset; however, it always initializes to a zero because the part does not come out of reset while in a low-power state (LVDE/LVDRE bits are enabled out of reset). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Register LVDF LVDIE Figure 10-2.
Page 154: Reset Status Register (Rsr)
1 Last reset state was caused by an LVD reset 0 Last reset state was not caused by an LVD reset MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 10-4 Description SOFT Figure 10-3. Reset Status Register (RSR) Table 10-4. RSR Field Descriptions Description Access: User read-only Freescale Semiconductor...
Page 155: Functional Description
(CCR). Then, if the current bus cycle is not terminated normally, the bus monitor terminates the cycle based on the length of time programmed in the BMT field of the CCR. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Table 10-5. Reset Source Summary...
Page 156: Software Reset
RSTO for approximately 512 cycles. Then the device exits reset and resumes operation. 10.6.1.6 LVD Reset The LVD reset occurs when the supply input voltage, V MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 10-6 drops below V (minimum). Freescale Semiconductor has reached a...
Page 157: Reset Control Flow
10-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 158 ENABLE BUS MONITOR BUS CYCLE COMPLETE? ASSERT RSTO AND LATCH RESET STATUS RSTI NEGATED? PLL MODE? WAIT 512 CLKOUT CYCLES RCON ASSERTED? Figure 10-4. Reset Control Flow POR OR LVD ASSERT RSTO AND LATCH RESET STATUS PLL LOCKED? LATCH CONFIGURATION Freescale Semiconductor...
Page 159: Concurrent Resets
(5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Reset Controller Module Figure 10-4.
Page 160 For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared to 0, even if another type of reset condition is detected during the reset sequence for LVD. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 161: Introduction
Full clock—days, hours, minutes, seconds • Minute countdown timer with interrupt • Programmable daily alarm with interrupt • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor SECOND MINUTE 1 PPM CLOCK CONTROL INTERRUPT ALARM COMPARATOR...
Page 162: Memory Map/Register Definition
RTC Interrupt Status Register (RTCISR) RTC Interrupt Enable Register (RTCIENR) Stopwatch Minutes Register (STPWCH) RTC Days Counter Register (DAYS) RTC Day Alarm Register (ALRM_DAY) Reserved Access read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write — read/write read/write Freescale Semiconductor...
Page 163 7–6 Reserved, should be cleared. 5–0 Minutes setting; can be set to any value between 0 and 59. MINUTES MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor HOURS Table 11-2. HOURMIN Field Descriptions Description Memory Map/Register Definition Figure 11-2.
Page 164 Reserved, should be cleared. 5–0 Seconds setting; can be set to any value between 0 and 59. SECONDS MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-4 Figure 11-3. Table 11-3. SECONDS Field Descriptions Description Access: User read/write SECONDS Freescale Semiconductor...
Page 165 Reserved, should be cleared. 5–0 Alarm minute setting; can be set to any value between 0 and 59. MINUTES MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor HOURS Table 11-4. ALRM_HM Field Descriptions Description Memory Map/Register Definition Access: User read/write...
Page 166 Reserved, should be cleared. 5–0 Alarm seconds setting; can be set to any value between 0 and 59. SECONDS MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-6 Table 11-5. ALRM_SEC Field Descriptions Description Access: User read/write SECONDS Freescale Semiconductor...
Page 167: Rtc Control Register (Rtcctl)
Software Reset bit. This bit resets the RTC to its default state. However, a software reset has no effect on the EN bit. 0 No effect 1 Reset the module to its default state MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 11-6. RTCCTL Field Descriptions Description Memory Map/Register Definition...
Page 168: Rtc Interrupt Status Register (Rtcisr)
Stopwatch flag bit. This bit indicates that the stopwatch countdown has timed out. 0 The stopwatch did not time out. 1 The stopwatch timed out. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-8 Table 11-7. RTCISR Field Descriptions Description Access: User read/write Freescale Semiconductor...
Page 169 Bit description 1 = Stopwatch interrupt is enabled. 0 = Stopwatch interrupt is disabled. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 11-8. RTCIENR Field Descriptions Description Memory Map/Register Definition Access: User read/write...
Page 170 0.5 minutes. For better accuracy, enable the stopwatch by polling the MIN bit of the RTCISR register or by polling the minute interrupt service routine. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-10 Table 11-9. STPWCH Field Descriptions Description Access: User read/write Freescale Semiconductor...
Page 171 15–0 Day Setting. This field indicates the current day count, and can be set to any value between 0 and 65535. DAYS MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DAYS Table 11-10. DAYS Field Descriptions Description Memory Map/Register Definition...
Page 172 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-12 DAYSAL Table 11-11. ALRM_DAY Field Descriptions Description Description”. RTCGOCNT[31:16] Table 11-12. RTCGOCU Field Descriptions Description Section 11.3, “Functional Description”. Access: User read/write Access: User read/write Freescale Semiconductor...
Page 173: Functional Description
The 16-bit day counter is located in the DAYR register These counters cover a 24-hour clock over 65536 days. All three registers can be read or written at any time. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor RTCGOCNT[15:0] Table 11-13. RTCGOCL Field Descriptions Description Section 11.3, “Functional...
Page 174: Initialization/Application Information
The actual delay includes the seconds from setting the stopwatch to the next minute tick. 11.4 Initialization/Application Information 11.4.1 Flow Chart of RTC Operation Figure 11-14 shows the flow chart of a typical RTC operation. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-14 Freescale Semiconductor...
Page 175: Code Example For Initializing The Real-Time Clock
MCF_RTC_HOURMIN = MCF_RTC_HOURMIN_MINUTES(((uint32)time_temp % 60)); MCF_RTC_SECONDS = MCF_RTC_SECONDS_SECONDS(((uint32)time_temp % 60)); Figure 11-15. Code Example for Initializing the Real-Time Clock MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Configure RTC Control Register Config RTC Days Counter Register Config RTC Seconds Counter Reg...
Page 176 Real-Time Clock MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 11-16 Freescale Semiconductor...
Page 177: Introduction
— Core reset status register (CRSR) indicates type of last reset — Core watchdog service register (CWSR) services watchdog timer — Core watchdog control register (CWCR) for watchdog timer control • System bus master arbitration programming model (MPARK) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 178: Memory Map And Register Definition
0x00 8.2.1/8-2 12.5.3/12-6 0x00 12.5.4/12-7 0x00 8.2.2/8-5 12.5.5/12-8 0x00 17.3.1/17-4 0x01 8.2.1.1/8-4 0x30E10000 12.6.3/12-10 0x03 12.7.3.1/12-14 0x00 8.2.3/8-7 0x00 8.2.4/8-8 0x08 8.3/8-9 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 0x00 12.7.3.2/12-14 Freescale Semiconductor...
Page 179: Register Descriptions
(IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 12-1. SCM Register Map (continued) Register Table 12-2.
Page 180: Memory Base Address Register (Rambar)
For example, a DMA channel in a typical double-buffer application (also MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-4 NOTE NOTE for descriptions of the bits in IPSBAR. Table 12-3. IPSBAR Field Description Description Access: read/write Freescale Semiconductor...
Page 181 RAMBAR specifies the base address of the SRAM. • All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor BA22 Table 12-4. RAMBAR Field Description Description (RAMBAR).”...
Page 182: Core Reset Status Register (Crsr)
Reserved, should read as 0. Do not write to these locations. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-6 NOTE for more information. NOTE Module”). Table 12-5. CRSR Field Descriptions Description Section 5.2.1, “SRAM Base Address Access: read/write Freescale Semiconductor...
Page 183: Core Watchdog Control Register (Cwcr)
IPSBAR Offset: 0x0011 (CWCR) CWRI Reset: Figure 12-4. Core Watchdog Control Register (CWCR) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor CWT[2:0] System Control Module (SCM) Access: read/write CWTA CWTAVAL CWTIF...
Page 184: Core Watchdog Service Register (Cwsr)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-8 Table 12-6. CWCR Field Description Description CWT Time-Out Period Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Bus clock frequency Figure 12-5 Freescale Semiconductor...
Page 185: Overview
All remaining requesting ports are evaluated by the arbitration algorithm to determine the next-state arbitration pointer. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor CWSR[7:0] Figure Figure 12-6. Arbiter Module Functions...
Page 186: Bus Master Park Register (Mpark)
MPARK[PRK_LAST] is set or parks on the master that last requested the bus if cleared. 12.6.3 Bus Master Park Register (MPARK) The MPARK controls the operation of the system bus arbitration module. The platform bus master connections are defined as the following: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-10 Freescale Semiconductor...
Page 187 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor M2_P BCR2 4BIT LCKOUT_TIME Table 12-7.
Page 188: Overview
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes the following: • Supervisor instruction fetch • Supervisor operand read • Supervisor operand write • User instruction fetch • User operand read MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-12 Description Freescale Semiconductor...
Page 189: Memory Map/Register Definition
[27:24] Offset 0x020 0x024 PACR0 0x028 PACR4 0x02C PACR8 0x030 GPACR0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 12-8. SACU Register Memory Map [23:20] [19:16] [15:12] PPMRS PACR1 PACR5 — GPACR1 System Control Module (SCM) [11:8]...
Page 190: Master Privilege Register (Mpr)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-14 [23:20] [19:16] [15:12] — — — Table 12-9. MPR[n] Field Descriptions Description Figure 12-12. [11:8] [7:4] — — — — — — Access: read/write MPR[3:0] 12-9. For a list of PACRs and the modules Freescale Semiconductor [3:0]...
Page 191 The encodings for this field are shown in Table 12-11. PACR ACCESSCTRL Bit Encodings Table 12-12. Peripheral Access Control Registers (PACRs) IPSBAR Offset 0x024 0x025 0x026 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ACCESS_CTRL1 LOCK0 Table 12-10. PACR Field Descriptions Description Table 12-11. Table 12-11.
Page 192 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 12-16 Modules Controlled Name ACCESS_CTRL1 PACR3 UART2 PACR4 PACR5 — PACR6 DTIM0 PACR7 DTIM2 PACR8 INTC0 NOTE Figure 12-10. GPACR Register ACCESS_CTRL0 — QSPI — DTIM1 DTIM3 — Access: read/write ACCESS_CTRL Freescale Semiconductor...
Page 193 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Table 12-14. Supervisor Mode User Mode Read / Write No Access Read No Access Read Read Read...
Page 194 Table 12-15. GPACR Address Space Space Protected (IPSBAR Offset) Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, CFM (Control) CFM (Flash module’s backdoor access for programming or access by a bus master other than the core) Modules Protected Freescale Semiconductor...
Page 195: Introduction
DTIN0 / PTC[0] / DTOUT0 / PWM0 Figure 13-1. General Purpose I/O Module Block Diagram MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 13-1 is a block diagram of the MCF52211 ports. UCTS2 / PUC[3] / SCL1...
Page 196: Memory Map/Register Definition
Descriptions,” for more detailed information on the different signals and pins. 13.5 Memory Map/Register Definition 13.5.1 Ports Memory Map Table 13-1 summarizes all the registers in the MCF52211 ports address space. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-2 Freescale Semiconductor...
Page 197 The register address is the sum of the IPSBAR address and the value in this column. S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 23–16 15–8 Reserved...
Page 198: Port Output Data Registers (Portn)
13-4 Figure Table 13-2, which applies to all PORTn registers. PORTn5 PORTn4 PORTn3 PORTn3 PORTUB, PORTUC) Figure 13-2. The remaining PORTn 13-3, Figure 13-4, Figure 13-5, Access: User read/write PORTn2 PORTn1 PORTn0 Access: User read/write PORTn2 PORTn1 PORTn0 Freescale Semiconductor...
Page 199: Port Data Direction Registers (Ddrn)
13-10, and Figure 13-11. The fields are described in registers. The DDRn registers are read/write. At reset, all bits in the DDRn registers are cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PORTn5 PORTn4 PORTn3 PORTn5 PORTn4 PORTn3 Table 13-2.
Page 200 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-6 DDRn5 DDRn4 DDRn3 DDRn3 DDRUB, DDRUC) DDRn5 DDRn4 DDRn3 DDRn5 DDRn4 DDRn3 Access: User read/write DDRn2 DDRn1 DDRn0 Access: User read/write DDRn2 DDRn1 DDRn0 Access: User read/write DDRn2 DDRn1 DDRn0 Access: User read/write DDRn2 DDRn1 Freescale Semiconductor...
Page 201: Port Pin Data/Set Data Registers (Portnp/Setn)
0x10_003A (PORTANP/SETAN) PORTnP7 PORTnP6 Reset: Figure 13-12. Port Pin Data/Set Data Registers with Bits 7:0 Implemented (PORTDD/SETDD, MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 13-3. DDRn Field Descriptions Description Figure 13-16. The fields are described in PORTnP5...
Page 202 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-8 PORTnP3 PORTnP5 PORTnP4 PORTnP3 PORTnP5 PORTnP4 PORTnP3 Access: User read/write PORTnP2 PORTnP1 PORTnP0 Access: User read/write PORTnP2 PORTnP1 PORTnP0 Access: User read/write PORTnP2 PORTnP1 Access: User read/write PORTnP1 PORTnP0 Freescale Semiconductor...
Page 203: Port Clear Output Data Registers (Clrn)
0x10_005A (CLRUB) 0x10_005B (CLRUC) Reset: Figure 13-18. Port Clear Output Data Registers with Bits 3:0 Implemented (CLRTA, CLRTC, CLRTD, CLRUA, MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure Table 13-5, which applies to all CLRn CLRn5...
Page 204: Pin Assignment Registers
Table 13-5. CLRn Field Descriptions Description Table 2-1 for the different functions assignable to each Table 2-1). However, a signal should not be assigned Access: User read/write CLRn2 CLRn1 CLRn0 Access: User read/write CLRn2 CLRn1 Access: User read/write CLRn1 CLRn0 Freescale Semiconductor...
Page 205 1 (secondary), alternate 2 (tertiary), and GPIO (quaternary) functions. The fields are described in Table 13-7, which applies to all quad-function registers. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PnPAR5 PnPAR4 PnPAR3 PnPAR3...
Page 206 Pin assumes the alternate 2 function MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-12 PnPAR6 PnPAR5 PnPAR2 PnPAR1 PnPAR1 PnPAR2 PnPAR1 PTDPAR, PUAPAR, PUBPAR) Description Access: User read/write PnPAR4 PnPAR0 Access: User read/write PnPAR0 Access: User read/write PnPAR0 Freescale Semiconductor...
Page 207: Pad Control Registers
1 in EzPort and FAST mode. The fields are described in The slew rate control bits corresponding to each pin/signal are listed in MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 13-7 for the encodings for the different fields. The...
Page 208 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-14 PSRR29 PSRR28 PSRR27 PSRR21 PSRR20 PSRR19 PSRR13 PSRR12 PSRR11 PSRR5 PSRR4 PSRR3 Table 13-8. PSRR Field Descriptions Description Access: User read/write PSRR26 PSRR25 PSRR24 PSRR18 PSRR17 PSRR16 PSRR10 PSRR9 PSRR8 PSRR2 PSRR1 PSRR0 Freescale Semiconductor...
Page 209: Ports Interrupts
1 Pin is configured for high drive strength (10mA) 0 Pin is configured for low drive strength (2mA) 13.7 Ports Interrupts The ports module does not generate interrupt requests. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PDSR29 PDSR28 PDSR27 See note 1 PDSR21...
Page 210 General Purpose I/O Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 13-16 Freescale Semiconductor...
Page 211: K/Coldfire Interrupt Architecture Overview
(IACK) cycle, with the ColdFire implementation using a special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch from a normal memory access. The MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 212: Interrupt Controller Theory Of Operation
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-2 for more information on the stack frame Determination.” Table 14-1. Interrupt Priority Within a Level ICR[2:0] Priority 7 (Highest) — Fixed Midpoint Priority Table Interrupt Sources 8–63 8–63 8–63 8–63 1–7 Freescale Semiconductor 14-1.
Page 213: Interrupt Prioritization
1 is active and acknowledged, if interrupt source 2 is active and acknowledged, MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ICR[2:0] Priority 0 (Lowest)
Page 214: Memory Map
Interrupt Force Register Low (INTFRCLn), [31:1] IACKLPRn[7:0] Reserved ICRn01 ICRn04 ICRn05 ICRn08 ICRn09 ICRn12 ICRn13 ICRn16 ICRn17 then Vector number = then Vector number = then Vector number = 126 Bits[15:8] Bits[7:0] Reserved ICRn02 ICRn03 ICRn06 ICRn07 ICRn10 ICRn11 ICRn14 ICRn15 ICRn18 ICRn19 Freescale Semiconductor...
Page 215: Register Descriptions
GL5IACK IPSBAR + 0x0FF8 GL6IACK IPSBAR + 0x0FFC GL7IACK 14.3 Register Descriptions The interrupt controller registers are described in the following sections. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Bits[23:16] ICRn20 ICRn21 ICRn24 ICRn25 ICRn28 ICRn29 ICRn32...
Page 216: Interrupt Pending Registers (Iprhn, Iprln)
Figure 14-2. Interrupt Pending Register Low (IPRLn) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-6 Figure 14-1 Figure 14-2, each 32 bits, provide a bit map for each INT[63:48] INT[47:32] Table 14-3. IPRHn Field Descriptions Description INT[31:16] INT[15:1] Access: Read-only Access: Read-only Freescale Semiconductor...
Page 217: Interrupt Mask Register (Imrhn, Imrln)
IMRHn bit is set. 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 14-4. IPRLn Field Descriptions Description INT_MASK[63:48] INT_MASK[47:32] Table 14-5.
Page 218: Interrupt Force Registers (Intfrchn, Intfrcln)
(1 = force MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-8 INT_MASK[31:16] INT_MASK[15:1] Table 14-6. IMRLn Field Descriptions Description NOTE Access: Read/write Freescale Semiconductor MASK...
Page 219 INTFRCL 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor INTFRCH[63:48] INTFRCH[47:32] Table 14-7. INTFRCHn Field Descriptions Description INTFRCL[31:16] INTFRCL[15:1] Table 14-8.
Page 220: Interrupt Acknowledge Level And Priority Register (Iacklprn)
IPSBAR Offset: 0x0C19 (IACKLPRn) Reset: Figure 14-8. IACK Level and Priority Register (IACKLPRn) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-10 IRQ[7:1] Table 14-9. IRLRn Field Descriptions Description Figure 14-8 Table 14-10. LEVEL Access: Read-only Access: Read-only Freescale Semiconductor...
Page 221: Interrupt Control Registers (Icrnx)
If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state. ICRn8 – ICRn63 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 14-10. IACKLPRn Field Descriptions Description Table 14-11. ICRnx Register Accessibility...
Page 222 111b represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field always reads as 000b. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-12 Table 14-12. ICRnx Field Descriptions Description Access: R/W (Read only for ICRn1-ICRn7) Freescale Semiconductor...
Page 223: Interrupt Sources
DTIM1 interrupt DTIM2 DTIM2 interrupt DTIM3 DTIM3 interrupt MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 14-13. Interrupt Source Assignments Source Description Not used (Reserved) Write EPF1 = 1 Write EPF2 = 1 Write EPF3 = 1...
Page 224 Section 15.4.1.5, “OTG Interrupt Status Register (OTG_INT_STAT)” and Status Register Not used (Reserved) Write PIF = 1 or write PMR Write PIF = 1 or write PMR Not Used (Reserved) Write CBEIF = 1 Flag Clearing Mechanism Section 15.4.1.9, “Interrupt (INT_STAT)” Freescale Semiconductor...
Page 225: Software And Level M Iack Registers (Swiackn, Lmiackn)
Offsets: (SWIACKn, LmIACKn) Reset: Figure 14-10. Software and Level m IACK Registers (SWIACKn, LmIACKn) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Source Description Cleared automatically Cleared automatically Cleared automatically Write IIF = 0 C interrupt (RTCISR)”...
Page 226: Global Level M Iack Registers (Glmiack)
7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0–6. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-16 Description (Section 14.3.7, “Software and Level m IACK Registers VECTOR Description NOTE Access: read-only Freescale Semiconductor...
Page 227 LPICR[6:4], then the interrupt controller asserts the wake-up output signal, which is routed to the SCM and PLL module to re-enable the device’s clock trees and resume processing. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 14-17...
Page 228 Interrupt Controller Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 14-18 Freescale Semiconductor...
Page 229: Introduction
The attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE 15-1...
Page 230 For additional information, refer to the USB2.0 specification [2]. Host PC External Hub External Hub USB Cable Root Host Software USB Cable USB Cable USB Peripherals USB Cables Figure 15-1. Example USB 2.0 System Configuration MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 231: Usb On-The-Go
For additional information, refer to the On-The-Go Supplement to the USB 2.0 Specification [3]. Print Photos Keyboard Input Swap Songs Hot Sync Download Songs Figure 15-2. Example USB 2.0 On-The-Go Configurations MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 232: Functional Description
The BD also contains indirect address pointers to where the actual buffer resides in system memory. This indirect address mechanism is shown in the following diagram. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-4 Figure 15-3. Freescale Semiconductor...
Page 233: Addressing Buffer Descriptor Table Entries
Sixteen bytes are needed for each USB endpoint direction. Applications with less than 16 End Points require less RAM to implement the BDT. The BDT Page Registers point to the starting location of the MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor BDT Page Buffer in Memory Figure 15-3.
Page 234: Buffer Descriptor Formats
The format for the BD is shown in the following figure. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-6 23:16 15:9 BDT_PAGE_02 BDT_PAGE_01[7:1] Figure 15-4. BDT Address Calculation Table 15-2. BDT Address Calculation Fields Description End Point IN ODD 000 Freescale Semiconductor...
Page 235 In host mode this field is used to report the last returned PID or a transfer status indication. The possible values returned are: 0x3 DATA0, 0xb DATA1, 0x2 ACK, 0xe STALL, 0xa NAK, 0x0 Bus Timeout, 0xf Data Error. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor KEEP/ NINC/ DATA0/1...
Page 236: Usb Transaction
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-8 Interrupt Generated DATA DATA DATA Function Figure 15-6. USB Token Transaction (ERR_STAT)”) as appropriate for the class of transaction. The DMA_ERR TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated TOK_DNE Interrupt Generated Section 15.4.1.11, Freescale Semiconductor...
Page 237: Memory Map/Register Definitions
IPSBAR + 0x1C_0090 IPSBAR + 0x1C_0094 IPSBAR + 0x1C_0098 IPSBAR + 0x1C_009C IPSBAR + 0x1C_00A0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 15-4. Table 15-4. USB Interface Memory Map Register USB OTG Registers Peripheral ID Register...
Page 238: Capability Registers
Endpoint Control Register 15 USB Control Register USB OTG Observe Register USB OTG Control Register Acronym Bits FRM_NUMH TOKEN SOF_THLD BDT_PAGE_02 BDT_PAGE_03 ENDPT0 ENDPT1 ENDPT2 ENDPT3 ENDPT4 ENDPT5 ENDPT6 ENDPT7 ENDPT8 ENDPT9 ENDPT10 ENDPT11 ENDPT12 ENDPT13 ENDPT14 ENDPT15 USB_CTRL USB_OTG_OBSERVE USB_OTG_CONTROL Freescale Semiconductor...
Page 239 Field 7–6 These bits always read ones 5–0 Ones complement of peripheral identification bits. NIDx MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 15-11. PER_ID Field Descriptions Description Figure 15-8 shows the ID_COMP register. NID5 NID4 NID3 Table 15-12.
Page 240 Figure 15-9. Peripheral Revision Register Table 15-13. REV Field Descriptions Description shows the ADD_INFO register. IRQ_NUM Table 15-14. ADD_INFO Field Descriptions Description Figure 15-9 shows the REV register. Access: User read-only REV2 REV1 Access: User read-only Freescale Semiconductor REV0 IEHOST...
Page 241 Reserved Reserved This bit is set when a change in VBUS is detected on an A device. A_VBUS _CHG MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Reserved LINE_STATE SESS_VLD _CHG – Figure 15-11. OTG Interrupt Status Register...
Page 242: Ipsbar
A_VBUS_EN 0 The A_VBUS_CHG interrupt is disabled 1 The A_VBUS_CHG interrupt is enabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-14 shows the OTG_INT_EN register. Reserved LINE_STATE_ SESS_VLD – Description Access: User read/write Reserved B_SESS A_VBUS – Freescale Semiconductor...
Page 243: Sess_Vld B_Sess
A VBUS Valid A_VBUS 0 The VBUS voltage is below the A VBUS Valid threshold _VLD 1 The VBUS voltage is above the A VBUS Valid threshold MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Reserved LINE_STATE SESS_VLD _STABLE –...
Page 244 When this bit is set, the VBUS signal is discharged through a resistor. VBUS _DSCHG MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-16 DP_LOW DM_LOW VBUS_ON Figure 15-14. OTG Control Register Table 15-18. OTG_CTRL Field Descriptions Description Access: User read/write VBUS_ OTG_EN Freescale Semiconductor VBUS_ DSCHG...
Page 245 0x00 into the address register and enable endpoint 0. USB_RST is set after a USB reset has been detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been removed and then reasserted. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 15-15 shows the INT_STAT register. RESUME...
Page 246 1 The USB_RST interrupt is enabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-18 Figure 15-16 shows the INT_ENB register. RESUME TOK_DNE SLEEP_EN Figure 15-16. Interrupt Enable Register Table 15-20. INT_ENB Field Descriptions Description Access: User read/write SOF_TOK ERROR_E Freescale Semiconductor USB_RST...
Page 247 This bit is set when the PID check field fails. PID_ERR MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor (ERR_ENB)”). All bits of this Register are logically OR’d together and Figure 15-17 DMA_ERR...
Page 248 PID_ERR 0 The PID_ERR interrupt is not enabled 1 The PID_ERR interrupt is enabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-20 DMA_ERR BTO_ERR DFN8_EN Table 15-22. ERR_ENB Field Descriptions Description Access: User read/write CRC5_EOF PID_ERR CRC16_EN Freescale Semiconductor...
Page 249: Status Register (Stat)
Buffer Descriptor updated was in the odd bank of the BDT. 1 - 0 Reserved MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 15-19. Status Register Table 15-23. STAT Field Descriptions Description...
Page 250 SIE. When host mode is enabled, clearing this bit causes the SIE to stop sending SOF tokens. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-22 TXSUSPEND/ HOST_ RESET TOKENBUSY MODE_EN Figure 15-20. Control Register Table 15-24. CTL Field Descriptions Description Access: User read/write USB_EN/ RESUME ODD_RST SOF_EN Freescale Semiconductor...
Page 251 USB address. This 7-bit value defines the USB address that the USB Module decodes in peripheral mode, or ADDR transmit when in host mode. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ADDR Figure 15-21. ADDR Register Table 15-25. ADDR Field Descriptions...
Page 252 This bit is always zero. The 32-bit BDT Base Address is always aligned on 512 byte boundaries in memory. NOT USED MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-24 BDT_BA13 BDT_BA12 BDT_BA11 Figure 15-22. BDT_PAGE_01 Register Description Figure 15-22 shows the BDT Access: User read/write BDT_BA10 BDT_BA9 NOT USED Freescale Semiconductor...
Page 253 These 3 bits represent the high-order bits of the11-bit Frame Number FRM[10:8] 7–3 This bits always read zero. NOT USED MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor FRM5 FRM4 FRM3 Figure 15-23. FRM_NUML Register Table 15-27. FRM_NUML Field Descriptions Description Figure 15-24.
Page 254 Table 15-29. TOKEN Field Descriptions Description OUT Token USB Module performs an OUT (TX) transaction IN Token USB Module performs an In (RX) transaction SETUP Token USB Module performs a SETUP (TX) transaction Figure 15-25 shows the TOKEN Access: User read/write TOKEN_ENDPT Freescale Semiconductor...
Page 255 Reset: Field 7 – 0 This 8 bit field represents the SOF count threshold in byte times. CNT[7:0] MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 15-26 CNT5 CNT4 CNT3 Figure 15-26. SOF_THLD Register Table 15-30. SOF_THLD Field Descriptions...
Page 256 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-28 BDT_BA21 BDT_BA20 BDT_BA19 Figure 15-27. BDT_PAGE_02 Register Description BDT_BA29 BDT_BA28 BDT_BA27 Figure 15-28. BDT_PAGE_03 Register Description Section 15.4.1.16, “BDT Access: User read/write BDT_BA18 BDT_BA17 BDT_BA16 Section 15.4.1.16, “BDT Access: User read/write BDT_BA26 BDT_BA25 BDT_BA24 Freescale Semiconductor...
Page 257 NAKed, the BDT PID field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When this bit is cleared NAKed transactions is retried in hardware. This bit must be set when the host is attempting to poll an interrupt endpoint. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor EP_CTL EP_RX _DIS Figure 15-29.
Page 258 Endpoint Enable / Direction Control Disable Endpoint Enable Endpoint for TX transfers only Enable Endpoint for RX transfers only Enable Endpoint for RX and TX transfers Enable Endpoint for RX and TX as well as control (SETUP) transfers SeeTable 15-34 Freescale Semiconductor...
Page 259 Determines the clock source for the USB 48 MHZ clock CLK_SRC USB_ALT_CLK pin Oscillator clock Reserved System clock source MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor — — — Figure 15-30. USB Control Register Table 15-35. USB_CTRL Field Descriptions Description...
Page 260 OTG control module via a serial interface. 0 VBUS Discharge is negated. 1 VBUS Discharge is asserted. Reserved. Reserved MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-32 DM_PD VBUSE Figure 15-31. USB OTG Observe Register Description Access: User read/write VBUSCHG VBUSDIS Freescale Semiconductor...
Page 261: Otg And Host Mode Operation
PC. In the palmtop computer application, a USB compliant keyboard/mouse can be connected to the palmtop computer with the obvious advantages of easier interaction. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor — VBUSD Figure 15-32. USB OTG Control Register...
Page 262: Host Mode Operation Examples
6. Enable SOF packet to keep the connected device from going to suspend (CTL[USB_EN=1]) 7. Start enumeration by sending a sequence of Chapter 9, device frame work packets to the default control pipe of the connected device. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 263 (INT_STAT[TOK_DNE]) interrupt is asserted. This completes the data phase of the setup transaction as referenced in chapter 9 of the USB specification. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor for information on the device framework command set. Universal Serial Bus, OTG Capable Controller...
Page 264: Otg Dual Role A Device Operation
USB Type Mini A connector is plugged into the device, he is considered the A device. A dual role A device operates as the following flow diagram and state description table illustrates. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-36 Freescale Semiconductor...
Page 265 If the A device is finished with session or if the A device wants to allow the B device to take bus. ID Interrupt or the B device disconnects MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Universal Serial Bus, OTG Capable Controller A_IDLE A_WAIT_VRISE...
Page 266: Otg Dual Role B Device Operation
Go to A_HOST Go to A_WAIT_VFALL Turn off DRV_VBUS. Go to A_WAIT_BCON Turn on Host Mode Go to A_IDLE A_IDLE B_SRP_INIT Response Go to A_IDLE Go to B_PERIPHERAL Turn on DP_HIGH Go to B_SRP_INIT Pulse CHRG_VBUS Pulse DP_HIGH 5-10 ms Freescale Semiconductor...
Page 267: Power
Alternately, the clock may be shut off to the core to conserve power. Again, this may only be done after the USB operations on the bus have been disabled and the device has been disconnected from the USB. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Universal Serial Bus, OTG Capable Controller Figure 15-34...
Page 268: Usb Suspend State
VM signals can be used to construct a circuit that is able to detect the resume signaling on the bus and restore the clocks to the rest of the circuit when the USB host takes the bus out of the suspend state. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 15-40 Freescale Semiconductor...
Page 269: Introduction
The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to prior to configuring the edge-port module. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE to determine which signals are available. Stop...
Page 270: Memory Map/Register Definition
Any IRQn interrupt at or above level in CR Level-sensing only Any IRQn interrupt set for level-sensing at or above level in CR. See note below. NOTE shows EPORT-module operation in Mode Exit Table 16-2 for a description of Freescale Semiconductor...
Page 271: Eport Pin Assignment Register (Eppar)
10 Pin IRQn falling edge triggered 11 Pin IRQn falling edge and rising edge triggered 1–0 Reserved, must be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 16-2. Edge Port Module Memory Map Register Supervisor Access Only Registers Supervisor/User Access Registers...
Page 272: Edge Port Interrupt Enable Register (Epier)
Reserved, must be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 16-4 EPDD5 EPDD4 EPDD3 Table 16-4. EPDDR Field Descriptions Description EPIE5 EPIE4 EPIE3 Table 16-5. EPIER Field Descriptions Description Access: Supervisor read/write EPDD2 EPDD1 Access: User read/write EPIE2 EPIE1 Freescale Semiconductor...
Page 273: Edge Port Pin Data Register (Eppdr)
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7–IRQ1. Writing to EPPDn EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR. Reserved, must be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor EPD5 EPD4 EPD3 Table 16-6. EPDR Field Descriptions...
Page 274: Edge Port Flag Register (Epfr)
0 Selected edge for IRQn pin has not been detected. 1 Selected edge for IRQn pin has been detected. Reserved, must be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 16-6 EPF5 EPF4 EPF3 Table 16-8. EPFR Field Descriptions Description Access: User read/write EPF2 EPF1 Freescale Semiconductor...
Page 275: Introduction
(SARn), destination address register (DARn), byte count register (BCRn), control register (DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART and GPIOs. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE Figure 17-1, has four channels that...
Page 276: Features
Channel Attributes Channel System Bus Address Enables System Bus Size Current Master Attributes Control Arbitration/ Control Data Path Control Figure 17-1. DMA Signal Diagram NOTE (DMAREQC).” DREQ3 SAR3 DAR3 Interrupts BCR3 DCR3 DSR3 Bus Interface Registered Bus Signals Freescale Semiconductor...
Page 277: Memory Map/Register Definition
This section describes each internal register and its bit assignment. Modifying DMA control registers during a DMA transfer can result in undefined operation. controller registers. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Modes).” Control and Data Memory/...
Page 278: Dma Request Control (Dmareqc)
DMA Control Register 2 (DCR2) Source Address Register 3 (SAR3) Destination Address Register 3 (DAR3) Byte Count Register 3 (BCR3) and DMA Status Register 3 (DSR3) DMA Control Register 3 (DCR3) DMAC2 DMAC1 [15:8] [7:0] Access: read/write DMAC0 Freescale Semiconductor...
Page 279: Destination Address Registers (Darn)
Destination Address Registers (DARn) DARn, shown in Figure 17-5, holds the address to which the DMA controller sends data. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 17-2. DMAREQC Field Description Description NOTE Section 5.2.1, “SRAM Base Address Register...
Page 280: Byte Count Registers (Bcrn) And Dma Status Registers (Dsrn)
DSRn[CE] is set and no transfer occurs. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 17-6 Figure 17-6. The address used to access both registers is the same; DSRn Figure 17-6) are shown in Access: read/write Figure 17-7. In response to an Freescale Semiconductor...
Page 281 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 17-7. DMA Status Registers (DSRn) Table 17-3. DSRn Field Descriptions...
Page 282: Dma Control Registers (Dcrn)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 17-8 Figure 17-8 DMOD D_REQ Figure 17-8. DMA Control Registers (DCRn) Table 17-4. DCRn Field Descriptions Description Section 17.4.4.1, Table 17-4. SINC SSIZE DINC DSIZE LINKCC LCH1 “Auto-Alignment.” Freescale Semiconductor START LCH2...
Page 283 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Number of kilobytes per block DMA has priority and does not negate its request until transfer completes.
Page 284 Buffer Disabled Buffer Disabled 0001 0001 16 Bytes 16 Bytes 0010 0010 32 Bytes 32 Bytes 1111 1111 256 Kbytes 256 Kbytes DMOD Circular Buffer Size 0000 Buffer Disabled 0001 16 Bytes 0010 32 Bytes 1111 256 Kbytes Freescale Semiconductor...
Page 285: Functional Description
A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and DCRn[DSIZE]. See “DMA Control Registers (DCRn).” MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description DMA Controller Module 17.3.5, 17-11...
Page 286: Transfer Requests (Cycle-Steal And Continuous Modes)
If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 17-12 Freescale Semiconductor...
Page 287: Channel Initialization And Startup
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DMA Controller Module 17-13...
Page 288: Data Transfer
If auto-alignment is enabled, DCRn[AA] equals 1, the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 17-14 Freescale Semiconductor...
Page 289: Termination
DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DMA Controller Module Section 13.6.3,...
Page 290 DMA Controller Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 17-16 Freescale Semiconductor...
Page 291: Introduction
It is not possible to read from any flash logical block while the same logical block is being erased, programmed, or verified. Flash logical blocks are divided into multiple logical pages that can be erased separately. An erased bit reads 1 and a programmed bit reads 0. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-1...
Page 292: Features
COMMON FLASH BUS EVEN COMMON FLASH BUS INTERFACE EVEN BLOCK ODD BLOCK ARRAY 0 ARRAY 1 ARRAY 2 ARRAY 3 FLASH MEMORY CONTROLLER FLASH COMMAND CONTROLLER INTERNAL FLASH BUS INTERFACE INTERNAL FLASH BUS Figure 18-1. CFM Block Diagram Freescale Semiconductor...
Page 293: Memory Map And Register Definition
CFM protection and access restriction scheme out of reset. A description of each byte found in the flash configuration field is given in Table 18-1. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor • • • BLOCK 0 ODD (4Bytes)
Page 294: Flash Base Address Register (Flashbar)
CFM Data Access Flash Security Word (see Section 18.3.3.3, “CFMSEC — CFM Security Register”) (CCM)” for more details). All other bits are unaffected. NOTE Chapter 9, “Chip Configuration Module Factory Default 0xFFFF_FFFF_FFFF_FFF 0xFFFF_FFFF 0xFFFF_FFFF Register”) 0xFFFF_FFFF Register”) 0xFFFF_FFFF Figure 18-3. Freescale Semiconductor...
Page 295 The value of WP is determined at power-on reset. The reset value for the valid bit is determined by the chip mode selected at reset (see (CCM)”). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE NOTE for more details. When the default reset —...
Page 296 1 Contents of FLASHBAR are valid Table 18-3. CFM Register Address Map Register Bits 31 - 24 23 - 16 CFMMCR RESERVED CFMSEC RESERVED CFMPROT CFMSACC CFMDACC Chapter 8, “Power Table 18-3. 15 - 8 7 - 0 CFMCLKD RESERVED Freescale Semiconductor...
Page 297: Register Descriptions
PVIOL in the CFMUSTAT register, is set. 1 = An interrupt is requested when the PVIOL flag is set. 0 = PVIOL interrupt disabled. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 18-3. CFM Register Address Map Register Bits 31 - 24...
Page 298 The CFMCLKD register is used to control the period of the clock used for timed events in program and erase algorithms. IPSBAR Offset: 0x1D_0002 (CFMCLKD) DIVLD PRDIV8 Reset: Figure 18-5. CFM Clock Divider Register (CFMCLKD) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-8 Description Access: User read/write Freescale Semiconductor...
Page 299 Flash memory security status SECSTAT 1 = Flash security is enabled. 0 = Flash security is disabled. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 18-5. CFMCLKD Field Descriptions Description Section 18.4.2.3.1, “Writing the CFMCLKD Table 18-6. CFMSEC Field Descriptions...
Page 300 18-10 Table 18-6. CFMSEC Field Descriptions Description Figure 18-6. Table 18-7. CFM Security States Description Flash Memory Secured Flash Memory Unsecured Section 18.4.3, “Flash Security PROTECT PROTECT Table 18-7, which defines the single code Operation”. Access: User read/write Freescale Semiconductor...
Page 301 (PROGRAM_ARRAY_BASE + $0001_1000) (PROGRAM_ARRAY_BASE + $0001_0000) (PROGRAM_ARRAY_BASE + $0000_F000) (PROGRAM_ARRAY_BASE + $0000_E000) (PROGRAM_ARRAY_BASE + $0000_1000) PROTECT[0] (PROGRAM_ARRAY_BASE + $0000_0000) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 18-8. CFMPROT Field Descriptions Description PROTECT[31:0] — SECTOR 31 • • •...
Page 302 SUPV[M] = 1: Flash logical sector M is placed in supervisor address space. SUPV[M] = 0: Flash logical sector M is placed in unrestricted address space. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-12 SUPV SUPV Table 18-9. Description Access: User read/write Freescale Semiconductor...
Page 303 IPSBAR Offset: 0x1D_0020 (CFMUSTAT) CCIF CBEIF Reset: Figure 18-11. CFM User Status Register (CFMUSTAT) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DACC DACC Table 18-10. CFMDACC Field Descriptions Description PVIOL ACCERR ColdFire Flash Module (CFM)
Page 304 1 = Access error has occurred. 0 = No access error has been detected. Reserved, should read 0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-14 NOTE Table 18-11. CFMUSTAT Field Descriptions Description for details on what action sets the ACCERR Freescale Semiconductor...
Page 305 ACCERR flag in the CFMUSTAT register to set. Table 18-13. CFM Flash Memory Commands MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 18-11. CFMUSTAT Field Descriptions Description Table 18-12. CFMCMD Field Descriptions...
Page 306: Functional Description
Single-Cycle Flash Block Read Access Two-cycle Flash Block Read Access Mode”) Operation”) Operation”) (Section 18.4.2.3, “Program, Erase, and Verify Mode”) (Section 18.4.3, “Flash Security Access: User read/write CLKSEL Table 18-15 describes the setting that Burst Read Access 1-1-1-1 2-1-1-1 Operation”) Freescale Semiconductor...
Page 307: Flash Normal Mode
If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1, else DIV = INT (FCLK[KHz] / 200kHz) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) 18-17...
Page 308: Command Write Sequence
The CBEIF flag is set again indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-18 CAUTION NOTE Section 18.4.2.3.5, “Flash Normal Mode Illegal Operations.” Freescale Semiconductor...
Page 309 15 internal flash bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set in the CFMUSTAT register. Upon completion of the blank MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure 18-11, upon command completion.
Page 310 NOTE: command write sequence Write: Register CFMUSTAT aborted by writing 0x00 to Clear bit CBEIF 0x80 CFMUSTAT register. Read: Register CFMUSTAT CCIF Set? Read: Register CFMUSTAT BLANK Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 EXIT Flash Memory EXIT Not Erased Freescale Semiconductor...
Page 311 If any address in the selected flash logical page is not erased, the page erase verify operation terminates and the BLANK flag remains clear. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) Figure 18-15. The page erase...
Page 312 Write: Register CFMUSTAT aborted by writing 0x00 to Clear bit CBEIF 0x80 CFMUSTAT register. Read: Register CFMUSTAT CCIF Set? Read: Register CFMUSTAT BLANK Set? Write: Register CFMUSTAT Clear bit BLANK 0x04 EXIT Flash Logical Page EXIT Not Erased Freescale Semiconductor...
Page 313 CCIF flag in the CFMUSTAT register sets after the program operation has completed unless a new command write sequence has been buffered. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) Figure 18-16.
Page 314: Page Erase
NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. Write: Register CFMUSTAT PVIOL Clear bit PVIOL 0x20 Set? Change Protection CBEIF Set? CCIF Set? EXIT Next Write? • Freescale Semiconductor...
Page 315 CCIF flag in the CFMUSTAT register sets after the page erase operation has completed, unless a new command write sequence has been buffered. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) Figure 18-17.
Page 316 NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. NOTE: Command write sequence aborted by writing 0x00 to CFMUSTAT register. Write: Register CFMUSTAT PVIOL Clear bit PVIOL 0x20 Set? Change Protection CBEIF Set? CCIF Set? EXIT Next Write? • Freescale Semiconductor...
Page 317 CCIF flag in the CFMUSTAT register sets after the mass erase operation has completed, unless a new command write sequence has been buffered. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) Figure 18-18.
Page 318 NOTE: command write sequence aborted by writing 0x00 to CFMUSTAT register. NOTE: command write sequence aborted by writing 0x00 to CFMUSTAT register. Write: Register CFMUSTAT PVIOL Clear bit PVIOL 0x20 Set? Change Protection CBEIF Set? CCIF Set? EXIT Next Write? • Freescale Semiconductor...
Page 319 As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended not to execute the stop instruction during program and erase operations. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor CAUTION ColdFire Flash Module (CFM) 18-29...
Page 320: Flash Security Operation
The contents of the flash security word at address offset 0x0414 must be changed by programming that address when the device is unsecured and the sector containing the flash configuration field is unprotected. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-30 NOTE Freescale Semiconductor...
Page 321: Blank Check
Doing so clears the flash security (FS) bit in the EzPort status register, after which a reset chip (RESET) command can be issued to regain access to the device. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ColdFire Flash Module (CFM) 18-31...
Page 322 ColdFire Flash Module (CFM) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 18-32 Freescale Semiconductor...
Page 323: Features
The rest of the micro-controller is disabled when the EzPort is enabled to avoid conflicts. • Disabled—When the EzPort is disabled, the rest of the micro-controller can access flash memory as normal. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-1...
Page 324: Overview
Reset Microcontroller Core Figure 19-1. EzPort Block Diagram Table 19-1. Signal Descriptions Description EzPort Clock EzPort Chip Select EzPort Serial Data In EzPort Serial Data Out EZPCS EZPCK EZPD EZPQ Reset Out Reset Controller Input Input Input Output Freescale Semiconductor...
Page 325: Command Definition
Page Program Sector Erase Bulk Erase RESET Reset Chip Lists the compatible commands on the ST Microelectronics Serial Flash Memory parts. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 19-2. EzPort Commands Address Code Bytes 0x06 0x04...
Page 326: Command Descriptions
Bulk Erase command. The flag clears after a Read Status Register (RDSR) command. 0 No error on previous erase/program command. 1 Error on previous erase/program command. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 19-4 Figure 19-2. EzPort Status Register Descriptions Access: read/write Freescale Semiconductor...
Page 327 This command should not be used if the write error flag is set, a write is in progress, or the configuration register has already been loaded (as it is a write-once register). IPSBAR Offset: PRDIV8 Reset: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Descriptions Figure 19-3. EzPort Configuration Register Access: read/write DIV[5:0] EzPort 19-5...
Page 328 The write error flag sets if there is an attempt to program a protected area of the flash memory. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 19-6 Descriptions Freescale Semiconductor...
Page 329: Functional Description
The serial data out from the EzPort is tri-stated unless data is being driven, allowing the signal to be shared among several different EzPort (or compatible) devices in parallel, provided they have different chip selects. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor EzPort 19-7...
Page 330: Initialization/Application Information
Fclk is less than 150 kHz. Incomplete programming and erasure can occur when Fclk is greater than 200 kHz. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 19-8 Fsys ------------------------------------------------------------------------------ - 2x200kHzx 1 PRDIV8x7 Fsys Fclk ----------------------------------------------------------------------------------- - )x 1 2x DIV PRDIV8x7 Freescale Semiconductor...
Page 331: Low-Power Mode Operation
Low-power modes are described in the power management module, Management.” Table 20-1 shows the PIT module operation in low-power modes and how it can exit from each mode. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Internal Bus 16-bit PCNTRn COUNT = 0 16-bit PIT Counter...
Page 332: Memory Map/Register Definition
No. Any interrupt is serviced upon normal exit stopped otherwise from debug mode Table 20-2) and describes the register structure for PIT0–PIT1. Width Register (bits) Supervisor Access Only Registers User/Supervisor Access Registers Mode Exit Access Reset Value Section/Page 0x0000 20.2.1/20-3 0xFFFF 20.2.2/20-4 0xFFFF 20.2.3/20-5 Freescale Semiconductor...
Page 333: Pit Control And Status Register (Pcsrn)
1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DOZE DBG OVW Figure 20-2. PCSRn Register Table 20-3.
Page 334: Pit Modulus Register (Pmrn)
PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF. IPSBAR 0x15_0002 (PMR0) Offset: 0x16_0002 (PMR1) Reset MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 20-4 Description Figure 20-3. PIT Modulus Register (PMRn) Access: Supervisor Freescale Semiconductor read/write...
Page 335: Functional Description
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 20-4. PMRn Field Descriptions Description Figure 20-4.
Page 336: Free-Running Timer Operation
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 20-6 0x0001 0x0005 0x0001 0x0005 Figure 20-6. Counter in Free-Running Mode × PRE[3:0] (PM[15:0] Table 20-6. PIT Interrupt Requests Flag Timeout 0x0000 0x0005 0x0000 0xFFFF × Eqn. 20-1 Enable Bit Freescale Semiconductor...
Page 337 The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-7...
Page 338 Programmable Interrupt Timers (PIT0–PIT1) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 20-8 Freescale Semiconductor...
Page 339: Introduction
• Programmable prescaler • Pulse-widths variable from microseconds to seconds • Single 16-bit pulse accumulator • Toggle-on-overflow feature for pulse-width modulator (PWM) generation • External timer clock input (SYNCA/SYNCB) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 21-1...
Page 340: Block Diagram
Interrupt Interrupt Request Logic CH. 0 Capture GPTx0 LOGIC CH. 0 Compare CH. 1 Capture GPTx1 LOGIC CH. 1 Compare CH.3 Capture PA Input GPTx3 LOGIC CH. 3 Compare EDGE DETECT PAIF Divide System Divide-by-64 by 2 Clock Freescale Semiconductor...
Page 341: Low-Power Mode Operation
The GPT3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. This pin is available for general-purpose I/O when not configured for timer functions. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 8, “Power Watchdog Operation...
Page 342: Memory Map And Registers
Access Reset Value Section/Page 0x00 21.6.1/21-5 0x00 21.6.2/21-6 0x00 21.6.3/21-6 0x00 21.6.4/21-7 0x00 21.6.5/21-7 0x00 21.6.5/21-7 0x00 21.6.6/21-8 0x00 21.6.7/21-9 0x00 21.6.8/21-9 0x00 21.6.9/21-10 0x00 21.6.10/21-10 0x00 21.6.11/21-11 0x00 21.6.12/21-12 0x00 21.6.13/21-12 21.6.14/21-13 21.6.14/21-13 21.6.14/21-13 21.6.14/21-13 21.6.14/21-13 21.6.14/21-13 21.6.14/21-13 Freescale Semiconductor...
Page 343: Gpt Input Capture/Output Compare Select Register (Gptios)
These bits are read anytime (always read 0x00), write anytime. 1 Output compare enabled 0 Input capture enabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-3. GPT Memory Map (continued) Register Table 21-4. GPTIOS Field Descriptions...
Page 344: Gpt Output Compare 3 Mask Register (Gptoc3M)
GPT Output Compare 3 Mask Register (GPTOC3M) IPSBAR Offset: 0x1A_0002 (GPTOC3M) Reset: Figure 21-4. GPT Output Compare 3 Mask Register (GPTOC3M) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-6 Table 21-5. GPTCFORC Field Descriptions Description NOTE Access: Supervisor read/write Access: Supervisor read/write OC3M Freescale Semiconductor...
Page 345: Gpt Output Compare 3 Data Register (Gptoc3D)
21.6.5 GPT Counter Register (GPTCNT) IPSBAR Offset: 0x1A_0004 (GPTCNT) Reset Figure 21-6. GPT Counter Register (GPTCNT) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-6. GPTOC3M Field Descriptions Description Table 21-7. GPTOC3D Field Descriptions Description NOTE CNTR...
Page 346: Gpt System Control Register 1 (Gptscr1)
1 Fast flag clearing 0 Normal flag clearing 3–0 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-8 Table 21-8. GPTCNT Field Descriptions Description TFFCA Table 21-9. GPTSCR1 Field Descriptions Description Access: Supervisor read/write Freescale Semiconductor...
Page 347: Gpt Toggle-On-Overflow Register (Gpttov)
IPSBAR Offset: 0x1A_0009 (GPTCTL1) Reset: Figure 21-10. GPT Control Register 1 (GPTCTL1) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Write GPTFLG1 Register Data Bit n TFFCA Figure 21-8. Fast Clear Flag Logic Table 21-10. GPTTOV Field Description...
Page 348: Gpt Interrupt Enable Register (Gptie)
Figure 21-12. GPT Interrupt Enable Register (GPTIE) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-10 Table 21-11. GPTCL1 Field Descriptions Description EDG2B EDG2A EDG1B Table 21-12. GPTLCTL2 Field Descriptions Description Access: Supervisor read/write EDG1A EDG0B Access: Supervisor read/write Freescale Semiconductor EDG0A...
Page 349: Gpt System Control Register 2 (Gptscr2)
0x0000 all the time. When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-13. GPTIE Field Descriptions Description...
Page 350: Gpt Flag Register 1 (Gptflg1)
21.6.13 GPT Flag Register 2 (GPTFLG2) IPSBAR Offset: 0x1A_000F (GPTFLG2) Reset: Figure 21-15. GPT Flag Register 2 (GPTFLG2) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-12 Description Table 21-15. GPTFLG1 Field Descriptions Description Access: Supervisor read/write Access: Supervisor read/write Freescale Semiconductor...
Page 351: Pulse Accumulator Control Register (Gptpactl)
21.6.15 Pulse Accumulator Control Register (GPTPACTL) IPSBAR Offset: 0x1A_0018 (GPTPACTL) Reset: Figure 21-17. Pulse Accumulator Control Register (GPTPACTL) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-16. GPTFLG2 Field Descriptions Description CCNT Table 21-17. GPTCn Field Descriptions Description...
Page 352: Pulse Accumulator Flag Register (Gptpaflg)
21.6.16 Pulse Accumulator Flag Register (GPTPAFLG) IPSBAR Offset: 0x1A_0019 (GPTPAFLG) Reset: Figure 21-18. Pulse Accumulator Flag Register (GPTPAFLG) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-14 Table 21-18. GPTPACTL Field Descriptions Description Access: Supervisor read/write PAOVF Freescale Semiconductor PAIF...
Page 353: Pulse Accumulator Counter Register (Gptpacnt)
To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-19. GPTPAFLG Field Descriptions Description...
Page 354: Functional Description
The general purpose timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-16 Table 21-21. GPTPORT Field Descriptions Description Table 21-22. GPTDDR Field Descriptions Description Access: Supervisor read/write PORTT Access: Supervisor read/write DDRT Freescale Semiconductor...
Page 355: Prescaler
When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor General Purpose Timer Module (GPT) 21-17...
Page 356: Gated Time Accumulation Mode
3 output mode (OM3) and output level (OL3) bits. Also clear the channel 3 output compare mask bit (OC3M3). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-18 NOTE NOTE NOTE Freescale Semiconductor...
Page 357: General-Purpose I/O Ports
3. Clear the pin’s DDR bit in PORTTnDDR. 4. Write to the OMn/OLn bits in GPTCTL1 to select the output action. Table 21-23 shows how various timer settings affect pin functionality. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE PULSE ACCUMULATOR OC3M3...
Page 358 Pin readable only if DDR = 0 compare Output Pin driven by OC action compare Output Pin readable only if DDR = 0 compare (ch 3) Output Pin driven by channel OC action and compare/ OC3Dn via channel 3 OC OC3Dn (ch 3) Freescale Semiconductor...
Page 359: Pulse Accumulator Overflow (Paovf)
When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 21-24. GPT Interrupt Requests Flag PAOVF...
Page 360: Pulse Accumulator Input (Paif)
When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 21-22 NOTE NOTE Freescale Semiconductor...
Page 361: Introduction
The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to prior to configuring the DMA Timers. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE NOTE Chapter 13, “General Purpose I/O Module”)
Page 362: Features
(indicates capture or when DTCN = DTRRn) Figure 22-1. DMA Timer Block Diagram Table 22-1, can be modified at any time. DMA Timer Extended Mode Mode Bits Register (DTXMRn) DMA Timer Reference Register (DTRRn) (reference value for comparison with DTCN) Freescale Semiconductor...
Page 363: Dma Timer Mode Registers (Dtmrn)
22-2, program the prescaler and various timer modes. IPSBAR 0x00_0400 (DTMR0) Offset: 0x00_0440 (DTMR1) 0x00_0480 (DTMR2) 0x00_04C0 (DTMR3) Reset MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Register Figure 22-2. DTMRn Registers DMA Timers (DTIM0–DTIM3) Width Access Reset Value Section/Page (bits) 0x0000 22.2.1/22-3...
Page 364: Dma Timer Extended Mode Registers (Dtxmrn)
The DTXMRn register programs DMA request and increment modes for the timers. IPSBAR 0x00_0402 (DTXMR0) Offset: 0x00_0442 (DTXMR1) 0x00_0482 (DTXMR2) 0x00_04C2 (DTXMR3) DMAEN HALTED Reset: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 22-4 Table 22-2. DTMRn Field Descriptions Description Figure 22-3. DTXMRn Registers Access: User read/write MODE16 Freescale Semiconductor...
Page 365: Dma Timer Event Registers (Dtern)
0x00_0403 (DTER0) Offset: 0x00_0443 (DTER1) 0x00_0483 (DTER2) 0x00_04C3 (DTER3) Reset: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 22-3. DTXMRn Field Descriptions Description Section 22.3.3, “Reference Compare.” Figure 22-4. DTERn Registers DMA Timers (DTIM0–DTIM3) Access: User read/write...
Page 366: Dma Timer Reference Registers (Dtrrn)
Capture on any edge & trigger interrupt Capture on any edge & trigger DMA 22-5, contains the reference value compared with the respective No event No request asserted No request asserted Interrupt request asserted DMA request asserted No event Freescale Semiconductor...
Page 367: Dma Timer Capture Registers (Dtcrn)
DTCNn clears it. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTINn). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor REF (32-bit reference value) Figure 22-5. DTRRn Registers Table 22-5.
Page 368: Reference Compare
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 22-8 CNT (32-bit timer counter value count) Figure 22-7. DMA Timer Counters (DTCNn) Table 22-7. DTCNn Field Descriptions Description Access: User read/write divided by 1 or 16) or from the Freescale Semiconductor...
Page 369: Initialization/Application Information
*[FRR] = 1, restart mode enabled *[CLK] = 10, internal bus clock/16 *[RST] = 0, timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE DMA Timers (DTIM0–DTIM3) 22-9...
Page 370: Calculating Time-Out Values
;If so, end timer0 example. Otherwise jump back. ;writing one to TER0[REF] clears the event flag ;End processing. Example is finished × × 1 or 16 DTMRn[PS] × × × ------------------- - 64453 × × Eqn. 22-1 DTRRn[REF] 2.00 s Eqn. 22-2 Freescale Semiconductor...
Page 371: Introduction
Control Logic Status Regs Control Regs Delay Counter Internal Bus Internal Bus Clock (f MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 80-byte QSPI Done QSPI Address Register Chip Selects 8/16 Bit Shift Reg. Rx/Tx Data Reg. Logic...
Page 372: External Signal Description
Although QSPI_CSn functions as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-2 NOTE Chapter 13, “General Purpose I/O Chapter 2, “Signal Descriptions,” Module”) for details on which chip-selects are Freescale Semiconductor...
Page 373: Memory Map/Register Definition
(QMR[MSTR]) must be set for the QSPI module to operate correctly. IPSBAR 0x00_0340 (QMR) Offset: MSTR DOHIE Reset MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Hi-Z or Actively Driven Configurable Actively driven Actively driven Table 23-2. QSPI Memory Map Register...
Page 374 / (2 × [desired QSPI_CLK baud rate]) QMR[BAUD] = f sys/ MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-4 Table 23-3. QMR Field Descriptions Description BITS Bits per Transfer 0000 0001–0111 Reserved 1000 1001 1010 1011 1100 1101 1110 1111 Freescale Semiconductor...
Page 375: Qspi Delay Register (Qdlyr)
Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 23-4. QSPI Delay Register (QDLYR) Table 23-4. QDLYR Field Descriptions Description Section 23.4.3, “Transfer Delays”...
Page 376: Qspi Interrupt Register (Qir)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-6 ENDQP Figure 23-5. QSPI Wrap Register (QWR) Table 23-5. QWR Field Descriptions Description SPIFE Figure 23-6. QSPI Interrupt Register (QIR) Access: User read/write CPTQP NEWQP Access: User read/write WCEF ABRT Freescale Semiconductor SPIF...
Page 377: Qspi Address Register (Qar)
QAR does not wrap after the last queue entry within each section of the RAM. The application software must manage address range errors. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 23-6. QIR Field Descriptions Description NOTE...
Page 378: Command Ram Registers (Qcr0–Qcr15)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-8 Figure 23-7. QSPI Address Register (QAR) Table 23-7. QAR Field Descriptions Description DATA Figure 23-8. QSPI Data Register (QDR) Table 23-8. QDR Field Descriptions Description Access: User read/write ADDR Access: User read/write Freescale Semiconductor...
Page 379: Functional Description
• 16 command control bytes (command RAM) • 32 transmit data bytes (transmit data RAM) • 32 receive data bytes (receive data RAM) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE QSPI_CS — — — — —...
Page 380 The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-10 NOTE Freescale Semiconductor...
Page 381: Qspi Ram
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data words with less than 16 bits are MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Relative Register...
Page 382: Baud Rate Selection
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the internal bus clock divided by two. A baud rate value of zero turns off the QSPI_CLK. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-12 Freescale Semiconductor...
Page 383: Transfer Delays
(DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1: Delay after transfer MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ----------------------------------------------------------------------------------- × [desired QSPI_CLK baud rate]...
Page 384: Data Transfer
QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-14 ------ - (DT = 0) Eqn. 23-4 Freescale Semiconductor...
Page 385: Initialization/Application Information
11. Write QAR with 0x0010 to select the first receive RAM entry. 12. Read QDR to get the received data for each transfer. 13. Repeat steps 5 through 13 to do another transfer. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Queued Serial Peripheral Interface (QSPI) 23-15...
Page 386 Queued Serial Peripheral Interface (QSPI) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 23-16 Freescale Semiconductor...
Page 387: Introduction
• Internal channel control logic Interrupt Request (to Interrupt Controller) Transmit DMA Request Receive DMA Request (To DMA Controller) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE Internal Bus UART Registers Serial Internal Channel Communications Control Logic...
Page 388: Features
False-start bit detection • Line-break detection and generation • Detection of breaks originating in the middle of a character • Start/end break interrupt/status MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-2 NOTE NOTE Chapter 13, “General Purpose I/O Module”) Freescale Semiconductor...
Page 389: Memory Map/Register Definition
UART registers are accessible only as bytes. Interrupt can mean an interrupt request asserted to the CPU or a DMA request. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 24-1. UART Module Signals Description UART RS-232 Transceiver...
Page 390 Width Access Reset Value Section/Page (bit) 0x00 24.3.1/24-5 24.3.2/24-6 0x00 24.3.3/24-7 See Section 24.3.4/24-9 0x00 24.3.5/24-9 0xFF 24.3.6/24-11 0x00 24.3.7/24-12 See Section 24.3.8/24-12 0x00 24.3.9/24-13 0x00 24.3.10/24-13 0x00 0x00 24.3.11/24-15 0x00 24.3.11/24-15 0xFF 24.3.12/24-15 0x00 24.3.13/24-16 0x00 24.3.13/24-16 Freescale Semiconductor...
Page 391: Uart Mode Registers 1 (Umr1N)
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor RESET MODE REGISTER POINTER Table 24-3. UMR1n Field Descriptions Description command for the UART was issued.
Page 392: Uart Mode Register 2 (Umr2N)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-6 Description Parity Mode Parity Type (PT= 0) With parity Even parity Force parity Low parity No parity Multidrop mode Data character TXRTS TXCTS Parity Type (PT= 1) Odd parity High parity Address character Access: User read/write Freescale Semiconductor...
Page 393: Uart Status Registers (Usrn)
3 selects two stop bits for transmission. 24.3.3 UART Status Registers (USRn) The USRn registers, shown in Figure MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 24-4. UMR2n Field Descriptions Description Section 24.4.3, “Looping Modes,” describes individual modes. 5 Bits 6–8 Bits...
Page 394 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-8 TXEMP Figure 24-5. UART Status Registers (USRn) Table 24-5. USRn Field Descriptions Description command in UCRn clears OE. Access: User read-only TXRDY FFULL Freescale Semiconductor RXRDY...
Page 395: Uart Clock Select Registers (Ucsrn)
24-7, supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, cannot be specified in one command. TRANSMITTER MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description See Note Table 24-6. UCSRn Field Descriptions Description UART Modules Section 24.4.1, “Transmitter/Receiver...
Page 396 Transmitter must be enabled for the command to be accepted. This command ignores the state of UCTSn. Causes UTXDn to go high (mark) within two bit times. Any characters in the transmit buffer are sent. Access: User write-only when RECEIVER DISABLE when reconfiguring the transmitter. Freescale Semiconductor...
Page 397: Uart Receive Buffers (Urbn)
FIFO while the receiver shifts and updates from the bottom when the shift register is full (see Figure 24-18). RB contains the character in the receiver. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Description Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled;...
Page 398: Uart Input Port Change Registers (Uipcrn)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-12 Figure 24-8. UART Receive Buffer (URBn) Figure 24-9. UART Transmit Buffer (UTBn) 24-10, hold the current state and the change-of-state for UCTSn. Access: User read-only Access: User write-only Access: User read-only Freescale Semiconductor UCTSn...
Page 399: Uart Interrupt Status/Mask Registers (Uisrn/Uimrn)
The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 24-8. UIPCRn Field Descriptions Description Table 24-9.
Page 400 Receiver is ready, Do not interrupt Receiver is ready, interrupt Access: User read/write FFULL/ TXRDY RXRDY FFULL/ TXRDY RXRDY (UCRn),” describes the 1 (FIFO) FIFO not full FIFO not full FIFO is full, Do not interrupt FIFO is full, interrupt Freescale Semiconductor...
Page 401: Uart Baud Rate Generator Registers (Ubg1N/Ubg2N)
Offset: 0x00_0274 (UIP1) 0x00_02B4 (UIP2) Reset: Figure 24-15. UART Input Port Registers (UIPn) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Rates.” Divider MSB Divider LSB NOTE 24-15, show the current state of the UCTSn input. UART Modules...
Page 402: Functional Description
16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-16 Table 24-11. UIPn Field Descriptions Description Description Access: User write-only Freescale Semiconductor...
Page 403: Programmable Divider
When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor When not divided, On-Chip Timer Module...
Page 404: Transmitter And Receiver Operating Modes
UART Status Register (USRn) Transmitter Holding Register Transmitter Shift Register Receiver Holding Register 1 Receiver Holding Register 2 Receiver Holding Register 3 Receiver Shift Register is the external clock extc UTXDn FIFO External Interface URXDn Freescale Semiconductor Eqn. 24-2 Eqn. 24-3...
Page 405 The transmitter must be manually reenabled by reasserting URTSn before the next message is sent. Figure 24-19 shows the functional timing information for the transmitter. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 24-19...
Page 406 Parity error, MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-20 C1 in transmission Start break command Figure 24-19. Transmitter Timing Diagram Section 24.3.5, “UART Command Registers Break C4 Stop break transmitted Manually asserted Freescale Semiconductor...
Page 407 In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break (RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 24-20. Receiver Timing Diagram UART Modules...
Page 408: Looping Modes
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-22 command. Status is updated as characters reach the top of the FIFO. NOTE Figure 24-20. These modes Freescale Semiconductor...
Page 409: Automatic Echo Mode
Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until next valid start bit is detected. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 24-21, the UART automatically resends received data bit by bit.
Page 410: Multidrop Mode
CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-24 Disabled URXDn Input Disabled UTXDn Output Figure 24-23. Remote Loopback Figure 24-24. Freescale Semiconductor...
Page 411 If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Master Station ADD1...
Page 412: Initialization/Application Information
1. Initialize the appropriate ICRx register in the interrupt controller. 2. Unmask appropriate bits in IMR in the interrupt controller. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-26 24-25, consists of: Section 14.3.6.1, “Interrupt Sources,” for details on interrupt Freescale Semiconductor...
Page 413 The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 24-13. Table 24-13. UART Interrupts...
Page 414: Uart Module Initialization Sequence
Select number of bits per character (B/Cx bits). 6. UMR2n: a) Select the mode of operation (CM bits). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-28 Table 24-14. UART DMA Requests DMA Request Receive DMA request Transmit DMA request Freescale Semiconductor...
Page 415 Channel Interrupts CHK1 Call CHCHK Save Channel Status Figure 24-25. UART Mode Programming Flowchart (Sheet 1 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Enable Errors? Enable Receiver Assert Request To Send SINITR Return UART Modules...
Page 416 To Transmitter RxCHK Character Been Received? Figure 24-25. UART Mode Programming Flowchart (Sheet 2 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-30 Waited Too Long? Waited Too Long? Set Transmitter- Never-ready Flag Set Receiver- Never-ready Flag Freescale Semiconductor...
Page 417 From Receiver Same As Transmitted Character? Set Incorrect Character Flag Figure 24-25. UART Mode Programming Flowchart (Sheet 3 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor UART Modules RSTCHN Disable Transmitter Restore To Original Mode Return...
Page 418 Stack And Monitor Warm Start Address SIRQR Figure 24-25. UART Mode Programming Flowchart (Sheet 4 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-32 INCH Does Channel A Receiver Have A Character? Place Character In D0 Return Freescale Semiconductor...
Page 419 UART Modules OUTCH Transmitter Ready? Send Character To Transmitter Return Figure 24-25. UART Mode Programming Flowchart (Sheet 5 of 5) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 24-33...
Page 420 UART Modules MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 24-34 Freescale Semiconductor...
Page 421: Introduction
‘n’, with n = 0 or 1, is used throughout this chapter to refer to registers associated with one of the two identical I MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C programming model registers. It NOTE...
Page 422: Overview
Shift Register Start, Stop, Arbitration Control Address Compare Figure 25-1. I C Module Block Diagram Section 25.2, “Memory Map/Register Internal Bus Address Data Data MUX C Data C Address I/O Register Register (I2DR) (IADR) Definition”: C bus allows Freescale Semiconductor...
Page 423: Features
Bus-busy detection 25.2 Memory Map/Register Definition The below table lists the configuration registers used in the I MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE C bus protocol. For NOTE Chapter 13, “General Purpose I/O C module.
Page 424 Figure 25-2. I2ADRn Registers Table 25-2. I2ADRn Field Descriptions Description Access Reset Value Section/Page 0x00 25.2.1/25-4 0x00 25.2.2/25-4 0x00 25.2.3/25-5 0x81 25.2.4/25-7 0x00 25.2.5/25-8 Access: User read/write C module. Slave mode is the default I C clock for Freescale Semiconductor C mode...
Page 425 C Control Registers (I2CRn) The I2CRn enable the I C modules and the I a slave or a master. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 25-3. I2FDRn Registers Table 25-3. I2FDRn Field Descriptions Description Divider...
Page 426 C module. If the module is enabled in the middle of a byte C module to lose arbitration, after which bus operation returns to normal. C interrupt occurs if I2SR[IIF] is also set. C bus is a receiver. Access: User read/write RSTA Freescale Semiconductor...
Page 427 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 25-5. I2SRn Registers Table 25-5. I2SRn Field Descriptions...
Page 428: Functional Description
Figure 25-6. I2DRn Registers Table 25-6. I2DRn Field Description Description C module should return to the default slave receiver state. See for exceptions. Figure 25-7). A START signal is defined as a C has received its slave address. Access: User read/write Freescale Semiconductor...
Page 429: Slave Address Transmission
Bit5 Bit4 Slave Address START Signal MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor SCL held low while Interrupt bit set Interrupt is serviced (Byte complete) C Standard Communication Protocol C master must not transmit its own slave address; it cannot...
Page 430: Repeated Start
START”) to start a new calling sequence. Bit7 Bit6 Bit5 Bit4 Bit3 START Signal Figure 25-9. Acknowledgement by Receiver Section 25.3.6, “Repeated START.” Figure 25-10. The master uses a repeated START to communicate with Figure Bit0 Bit2 Bit1 Figure 25-7). The master Freescale Semiconductor 25-9.
Page 431 Example 3: 7-bit Slave Address Master Reads from Slave Figure 25-11. Data Transfer, Combined Format MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Repeated START Signal Figure 25-10. Repeated START is the case of master-transmitter transmitting to slave-receiver.
Page 432: Clock Synchronization And Arbitration
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 25-12 Start counting high period Wait Internal Counter Reset Figure 25-12. Clock Synchronization Master 2 Loses Arbitration, and becomes slave-receiver Figure 25-13. Arbitration Procedure Figure 25-12). When all Figure 25-13). In this case, transition Freescale Semiconductor...
Page 433: Initialization/Application Information
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period, the processor MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C bus interface system. NOTE C bus module is enabled, execute the ;...
Page 434: Post-Transfer Software Response
2. Get value from transmitting counter, TXCNT. If no more data, go to step #5. 3. Transmit next byte of data via I2DR. 4. Decrement TXCNT and go to step #1 5. Generate a stop condition by clearing I2CR[MSTA]. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 25-14 Freescale Semiconductor...
Page 435: Generation Of Repeated Start
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor C Interface 25-15...
Page 436 Arbitration Lost? Clear IAL IAAS=1 IAAS=1 Data Cycle SRW=1 Tx/Rx (WRITE) ACK from Receiver Read Data Tx Next from I2DR Byte and Store Switch to Set RX Rx Mode Mode Dummy Read Dummy Read from I2DR from I2DR Freescale Semiconductor...
Page 437: Chapter 26 Analog-To-Digital Converter (Adc)
1. In loop mode, the time between each conversion is 6 ADC clock cycles (1.2 μs at 5.0 MHz). Using simultaneous conversion, two samples are captured in 1.2 μs, providing an overall sample rate of 1.66 million samples per second. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor μ μ...
Page 438: Block Diagram
Digital Output Storage Registers • • • Bus Interface Data Width Access Reset Value Section/Page (bits) 0x5005 26.4.1/26-3 0x0002 26.4.2/26-5 0x0000 26.4.3/26-8 0x3210 26.4.4/26-8 0x7654 26.4.4/26-8 0x0000 26.4.5/26-10 0x0000 26.4.6/26-11 0x0000 26.4.7/26-13 0x0000 26.4.8/26-14 0x0000 26.4.9/26-14 0x0000 26.4.10/26-15 Freescale Semiconductor...
Page 439: Control 1 Register (Ctrl1)
START0 bit again is ignored until the end of the current scan. The ADC must be in a stable power configuration prior to writing to START0 (see 0 No action 1 Start command is issued MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Register Figure 26-2, is used to configure and control the ADC module. The Table 26-2.
Page 440 The raw result value is compared to ADHLMT[HLMT] before the offset register value is subtracted. 0 Interrupt disabled 1 Interrupt enabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-4 Description Management”). Freescale Semiconductor...
Page 441: Control 2 Register (Ctrl2)
IPSBAR Offset: 0x19_0002 (CTRL2) Reset Figure 26-3. Control 2 Register (CTRL2) Under Sequential Scan Modes MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Inputs AN0–AN1 Configured as differential pair (AN0 is + and AN1 is –) Both configured as single ended inputs AN2–AN3...
Page 442 The ADC must be in a stable power configuration prior to writing to START1 (see Section 26.5.8, “Power 0 No action 1 Start command is issued MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-6 Description Description Management”). Table 26-5 Access: read/write SIMU Freescale Semiconductor...
Page 443 200 kHz Sys Clock 00000 00001 00010 00011 00100 — — MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description ROSC Normal 400 kHz 8 MHz 4 MHz Sys Clock 32 MHz Sys Clock 100 kHz 2.00 MHz 100 kHz 1.00 MHz...
Page 444: Channel List 1 And 2 Registers (Adlst1 And Adlst2)
011. Likewise, because converter B only has access to analog inputs AN4 through AN7, sample slots MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-8 — — 100 kHz 62.5 kHz ZCE5 ZCE4 ZCE3 Table 26-6. ADZCC Field Descriptions Description — — 500 kHz CLK/128 Access: read/write ZCE2 ZCE1 Freescale Semiconductor ZCE0...
Page 445 Sample input channel select 0. The settings for this field are given in SAMPLE0 IPSBAR Offset: 0x19_0008 (ADLST2) SAMPLE7 Reset Figure 26-7. Channel List 2 Register (ADLST2) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Samples” and SAMPLE2 Table 26-7. ADLST1 Field Descriptions Description SAMPLE6 Analog-to-Digital Converter (ADC) Section 26.5.2.2,...
Page 446: Sample Disable Register (Adsdis)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-10 Table 26-8. ADLST2 Field Descriptions Description Parallel Mode n=4,5,6,7 Single Ended (Conv. B) Table 26-9. Table 26-9. Table 26-9. Table 26-9. ADC Input Pins Selected Differential AN0+, AN1– AN2+, AN3– AN4+, AN5– AN6+, AN7– Freescale Semiconductor...
Page 447: Status Register (Adstat)
Offset: 0x19_000C (ADSTAT) R CIP0 CIP1 EOSI1 EOSI0 Reset MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 26-10. ADSDIS Field Descriptions Description LLMTI HLMTI RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 Figure 26-9. Status Register (ADSTAT)
Page 448 It is cleared by writing 1 to all active ADLSTAT[LLS] bits. 0 No low limit interrupt request 1 Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-12 Table 26-11. ADSTAT Field Descriptions Description Freescale Semiconductor...
Page 449: Limit Status Register (Adlstat)
1 Sample n is less than the associated low-limit value Note: These bits are sticky, and can only be cleared by writing a 1 to them. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Table 26-12. ADLSTAT Field Descriptions...
Page 450: Zero Crossing Status Register (Adzcstat)
Accept the number as presented in the register, knowing there are missing codes, because the lower three LSBs are always zero MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-14 (ADZCC)”). ZCS7 ZCS6 ZCS5 ZCS4 ZCS3 ZCS2 ZCS1 ZCS0 Table 26-13. ADLSTAT Field Descriptions Description Access: read/write Section 26.4.3, “Zero Crossing Freescale Semiconductor...
Page 451: Low And High Limit Registers (Adllmtn And Adhlmtn)
Limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high limit and 0x0000 for the low limit. At reset, limit checking is disabled. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor RSLT Figure 26-12. Result Registers (ADRSLTn) Table 26-14.
Page 452 Reserved, should be cleared. 14–3 High limit. HLMT 2–0 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-16 LLMT Table 26-15. ADLLMTn Field Descriptions Description HLMT Table 26-16. ADHLMTn Field Descriptions Description Access: read/write Access: read/write Freescale Semiconductor...
Page 453: Power Control Register (Power)
4. Active state The ADC module is active when at least one of the two converters has a scan in process. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor OFFSET Figure 26-15. Offset Registers (ADOFSn) Table 26-17. ADOFSn Field Descriptions...
Page 454 0 ADC converter B is currently enabled 1 ADC converter B is currently disabled MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-18 Section 26.5.9, “ADC PUDELAY Table 26-18. POWER Field Descriptions Description Section 26.5, “Functional Description” Clock,” for a more Access: read/write Freescale Semiconductor...
Page 455 (powering-down) converter A and converter B automatically powers-down the voltage reference. 0 Manually power-up voltage reference circuit 1 Power-down voltage reference circuit is controlled by PD0 and PD1 (default) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Analog-to-Digital Converter (ADC) Description 26-19...
Page 456: Voltage Reference Register (Cal)
Source bit. This bit selects the source of the V REFL SEL_VREFL 0 VRL 1 AN6 13–0 Reserved, should be cleared. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-20 Description Table 26-19. CAL Field Descriptions Description Access: read/write reference for conversions. REFH reference for conversions. REFL Freescale Semiconductor...
Page 457: Functional Description
AN6-7. When configured as a differential pair, a reference to either member of the differential pair by a sample slot results in a differential measurement using that differential pair. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ADHLMT[0:3] ADLLMT[0:3] Zero Crossing Logic –...
Page 458 ADLLMT[0:3] Zero Crossing Logic – ADOFS[0:3] ADHLMT[4:7] ADLLMT[4:7] Zero Crossing Logic – ADOFS[4:7] ADC0 > ADC1 ADC2 < End of Scan A Interrupt ADRSLT[0:3] Zero Crossing or Error Limit Interrupt > End of Scan B Interrupt < ADRSLT[4:7] Freescale Semiconductor...
Page 459: Input Mux Function
Table 26-20. Analog MUX Controls for Each Conversion Mode Conversion Mode Sequential, Single Ended Sequential, Differential MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 26-20. The channel select and single ended vs. differential Table 26-20. Internally, all measurements are performed...
Page 460 A/D. Channel Select Converter A Interface Function V– Differential Channel Select Single-Ended vs Differential Channel Select Converter B Interface Function V– Differential Channel Select Single-Ended vs Differential Freescale Semiconductor...
Page 461: Adc Sample Conversion
A mix and match combination of differential and single-ended configurations may exist. Examples: • AN0 and AN1 differential, AN2 and AN3 single-ended • AN4 and AN5 differential, AN6 and AN7 single-ended MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ADCA Interface V– Function ADCB Interface V–...
Page 462 Figure 26-22 REFH REFL – × ------------------------------------------ - 4095 round – REFH REFLO REFL × , return 0 when the REFH REFL shows typical configurations × and V REFH REFL REFH and the minus (−) input is at Freescale Semiconductor...
Page 463: Adc Data Processing
3 bits (as shown in the ADRSLT register definition) and does not include the sign bit. The sign bit (SEXT) is calculated during subtraction of the corresponding ADOFSn offset value. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor – AN–...
Page 464: Sequential Vs. Parallel Sampling
> ADLLMT[0:3] < Zero Crossing Logic ADRSLT[0:3] – ADOFS[0:3] ADHLMT[4:7] > ADLLMT[4:7] < Zero Crossing Logic ADRSLT[4:7] – ADOFS[4:7] End of Scan A Interrupt ADC0 ADC1 ADC2 Zero Crossing or Error Limit Interrupt End of Scan B Interrupt Freescale Semiconductor...
Page 465: Scan Sequencing
Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 26-29...
Page 466: Scan Configuration And Control
During non-simultaneous scans, the A and B converters operate asynchronously with each converter using its own independent set of controls (CTRL1 for A and CTRL2 for B). Refer to Section 26.4.2.2, “CTRL2 Under Parallel Scan Modes,” for more information. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-30 Freescale Semiconductor...
Page 467 ADSDIS register or completes all 4 samples. If external sync is enabled (SYNC0=1), new scans are started for each sync pulse as long as the ADC has completed the previous scan (STAT[CIPn]=0). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 26-31...
Page 468: Power Management Modes
ADC clock and powers down the converters when idle. A startup delay of MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-32 Figure 26-24. ADC Interrupt Sources ADCA Conversion Complete (ADC_CC0_INT) ADCB Conversion Complete (ADC_CC1_INT) ADC Zero Crossing or Limit Error (ADC_ERR_INT) Section 26.5.9, Freescale Semiconductor...
Page 469 The following paragraphs provide an explanation of how to use PUDELAY when starting the ADC up or changing modes. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Analog-to-Digital Converter (ADC) 26-33...
Page 470: Adc Clock
26.5.9 ADC Clock 26.5.9.1 General The ADC has two external clock inputs used to drive two clock domains within the ADC module. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-34 Freescale Semiconductor...
Page 471 The oscillator clock feeds an 80:1 divider, generating the auto standby clock. The auto standby clock is selected as the ADC clock during the auto standby power mode when both converters are idle. The auto MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 26-22. ADC Clock Summary Characteristics Maximum rate is PLL output divided by 2 if PLL enabled.
Page 472 Sequential and Simultaneous Parallel Modes MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-36 26-27, the first scan started is re-synchronized to the system clock, ADC Conversion Clock Resynchronized ADC Scans Start ADCA Scan ADCB Scan Figure 26-26 Freescale Semiconductor...
Page 473 REFH the amplitude of V . It is imperative that special precautions be taken to assure the voltage applied to MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ADC Conversion Clock Resynchronized ADCA Scan Start START1 Asserted ADCB Scan Should Start Here...
Page 474: Supply Pins
Dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy. The power provided to these pins is suggested to come from a low noise filtered source. Uncoupling capacitors ought to be connected between V and V MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 26-38 Freescale Semiconductor...
Page 475: Introduction
With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter. Internal Bus Clock select Clock (f Control MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 27-1, generates a synchronous series of pulses having programmable PWM Clocks PWM Channels Channel 7 Period and Duty Channel 6...
Page 476: Memory Map/Register Definition
Chapter 13, “General Purpose I/O Table 27-1. PWM Memory Map Width Register (bits) Module”) Access Reset Value Section/Page 0x00 27.2.1/27-3 0x00 27.2.2/27-4 0x00 27.2.3/27-4 0x00 27.2.4/27-5 0x00 27.2.5/27-6 0x00 27.2.6/27-7 0x00 27.2.7/27-8 0x00 27.2.8/27-9 0x00 27.2.9/27-9 0xFF 27.2.10/27-10 0xFF 27.2.11/27-11 0x00 27.2.12/27-12 Freescale Semiconductor...
Page 477: Pwm Enable Register (Pwme)
If PWMCTL[CON23] is set, then this bit has no effect and PWMOUT2 is disabled. 0 PWM output disabled 1 PWM output enabled, if PWMCTL[CON23]=0 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor for more information. PWME5 PWME4 PWME3 Figure 27-2.
Page 478: Pwm Clock Select Register (Pwmclk)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-4 Description PPOL5 PPOL4 PPOL3 Table 27-3. PWMPOL Field Descriptions Description Access: User Read/Write PPOL2 PPOL1 PPOL0 Freescale Semiconductor...
Page 479: Pwm Prescale Clock Select Register (Pwmprclk)
IPSBAR 0x1B_0003 (PWMPRCLK) Offset: Reset: Figure 27-5. PWM Prescale Clock Select Register (PWMPRCLK) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PCLK5 PCLK4 PCLK3 Table 27-4. PWMCLK Field Descriptions Description Section 27.2.7, “PWM Scale A Register (PWMSCLA)”...
Page 480: Pwm Center Align Enable Register (Pwmcae)
Internal bus clock ÷ 2 Internal bus clock ÷ 2 PCKA Clock A Rate Internal bus clock ÷ 2 Internal bus clock ÷ 2 Internal bus clock ÷ 2 Section 27.3.2.6, “Center-Aligned Outputs” CAE5 CAE4 CAE3 Access: User Read/Write CAE2 CAE1 Freescale Semiconductor CAE0...
Page 481: Pwm Control Register (Pwmctl)
16-bit PWM signal, and PWMOUT0 is disabled. The channel 1 clock select, polarity, center align enable, and enable bits control this concatenated output. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 27-6. PWMCAE Field Descriptions Description Section 27.3.2.7, “PWM 16-Bit Functions”...
Page 482: Pwm Scale A Register (Pwmscla)
Part of divisor used to form Clock SA from Clock A. SCALEA MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-8 Description Clock A Clock SA ---------------------------------------- - × PWMSCLA SCALEA Table 27-8. PWMSCLA Field Descriptions Description SCALEA Value 0x00 0x01 0x02 0xFF Eqn. 27-1 Access: User Read/Write Freescale Semiconductor...
Page 483: Pwm Channel Counter Registers (Pwmcntn)
The counter is also cleared at the end of the effective period (see Section 27.3.2.6, “Center-Aligned Outputs” MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Clock B Clock SB --------------------------------------- - ×...
Page 484: Pwm Channel Period Registers (Pwmpern)
Boundary Cases”. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-10 Section 27.3.2.4, “PWM Timer Counters.” COUNT Table 27-10. PWMCNTn Field Descriptions Description × PWMCAE CAEn Access: User Read/Write Section 27.3.2.3, × PWMPERn Section 27.3.2.8, “PWM Freescale Semiconductor Eqn. 27-3...
Page 485: Pwm Channel Duty Registers (Pwmdtyn)
0x1B_0020 (PWMDTY4) 0x1B_0021 (PWMDTY5) 0x1B_0022 (PWMDTY6) 0x1B_0023 (PWMDTY7) Reset: Figure 27-12. PWM Duty Registers (PWMDTYn) MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PERIOD Table 27-11. PWMPERn Field Descriptions Description for other special cases. ⎛ PWMDTYn 1 PWMPOL PPOLn –...
Page 486: Pwm Shutdown Register (Pwmsdn)
PWM channel 7 input status. Reflects the current status of the PWMOUT7 pin. Read only. PWM7IN MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-12 Table 27-12. PWMDTYn Field Descriptions Description RESTART Table 27-13. PWMSDN Field Descriptions Description Section 27.3.2.8, Access: Read/Write PWM7IN PWM7IL SDNEN Freescale Semiconductor...
Page 487: Functional Description
PWM channel has the capability of selecting one of two clocks, the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in the scaled clocks are created. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Pulse-Width Modulation (PWM) Module Description Figure 27-14...
Page 488 PWMPRCLK [PCKB] Clock B PCLR0 Clock to PWM0 Clock to PWM1 PCLR1 PCLR4 Clock to ÷2 PWM4 Clock to PWM5 PCLR5 PCLR2 Clock to ÷2 PWM2 Clock to PWM3 PCLR3 PCLR6 Clock to PWM6 Clock to PWM7 PCLR7 Freescale Semiconductor...
Page 489: Pwm Channel Timers
The starting polarity of the output is also selectable on a per channel basis. timer. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Clock A Clock SA ---------------------------------------- - ×...
Page 490 This forces the counter to reset and the new duty MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-16 PWMDTYn PWMEn PPOLn PWMPERn PWMCAE = 1 PWMCAE = 0 for more detail. PWMOUTn Freescale Semiconductor...
Page 491 Counter Clears (0x00) When PWMCNTn register written to any value Effective period ends MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 27-15. When the PWM counter matches the duty register, Section 27.3.2.5, “Left-Aligned Outputs” NOTE Section 27.3.2.5, “Left-Aligned Outputs”...
Page 492 --------------------------------------------------------- - PWMPERn ⎛ PWMDTYn ------------------------------- 1 PWMPOL PPOLn – – ⎝ PWMPERn ⎞ × -- - 100% ⎠ Figure 27-15. When the 27.3.2.3. The counter counts from 0 to the ⎞ × 100% ⎠ Freescale Semiconductor Eqn. 27-7 Eqn. 27-8...
Page 493 PWMn frequency The PWMn duty cycle (high time as a percentage of period) is expressed as: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor DUTY CYCLE = 75% PERIOD = 100ns Figure 27.3.2.3. The counter counts from 0 up to the value PWMPERn Period = PWMPERn ×...
Page 494 ------------------------------- 1 PWMPOL PPOLn – – ⎝ PWMPERn ⎞ × -- - 100% ⎠ DUTY CYCLE = 75% PERIOD = 200ns Figure 27-20. The polarity of the resulting PWM ⎞ × Eqn. 27-10 100% ⎠ E = 25ns Freescale Semiconductor...
Page 495 PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (left- or center-aligned) and 8-bit (normal) or 16-bit (concatenation): MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor High PWMCNT6 PWMCNT7...
Page 496 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 27-22 Table 27-16. PWM Boundary Cases PWMPERn PPOLn >0x00 >0x00 0x00 (indicates no period) 0x00 (indicates no period) PWMn Output Always Low Always High Always High Always Low Always High Always Low Freescale Semiconductor...
Page 497: Introduction
External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the option allows interrupts to occur. See MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 28-1. ColdFire CPU Core...
Page 498: Signal Descriptions
BKPT configurable interrupt (CSR[BKD]) Level 1 and level 2 triggers on OR condition, in addition to AND command to display the processor’s current PC SYNC 3 new PC breakpoint registers PBR1–3 Pinout”. Table 28-2. Debug Module Signals Description Section 28.4.2, Freescale Semiconductor...
Page 499: Real-Time Trace Support
DDATA port, one nibble at a time starting with the least significant bit (lsb). MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Table 28-3 describes PST values.
Page 500 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until the processor is restarted or reset. See MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-4 Table 28-3. Processor Status Encoding Definition Section 28.5.1, “CPU Halt”. 0x5)”. Also indicates that the Freescale Semiconductor...
Page 501: Begin Execution Of Taken Branch (Pst = 0X5)
DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor default default...
Page 502: Memory Map/Register Definition
These commands contain a Access Reset Value 0x0090_0000 28.4.2/28-7 See Note 0x05 28.4.3/28-10 0x0005 28.4.4/28-10 0x0000_0000 28.4.5/28-12 Undefined 28.4.6/28-15 Undefined 28.4.6/28-15 Undefined 28.4.7/28-17 Undefined 28.4.7/28-17 Undefined 28.4.8/28-18 Undefined 28.4.8/28-18 See Section 28.4.6/28-15 See Section 28.4.6/28-15 See Section 28.4.6/28-15 Freescale Semiconductor Section/ Page...
Page 503: Configuration/Status Register (Csr)
BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the commands. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE command. In addition, the WDMREG...
Page 504 Only commands from the external development system can modify IPW. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-8 TRG HALT BKPT Table 28-6. CSR Field Descriptions Description command or reading CSR (from the BDM port only) clear TRG. Access: Supervisor write-only BDM read/write Freescale Semiconductor...
Page 505 0 Core services any pending interrupt requests that were signalled while in single-step mode. 1 Core ignores any pending interrupt requests signalled while in single-instruction-step mode. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Section 28.6.1.1, “Emulator Table 28-3.
Page 506: Address Attribute Trigger Register (Aatr)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-10 Description command, the processor executes the next instruction and halts again. Table 28-7. BAAR Field Descriptions Description Section 28.4.4, “Address Attribute Trigger Register Section 28.4.4, “Address Attribute Trigger Register Access: Supervisor write-only BDM write-only Freescale Semiconductor...
Page 507 Size. Compared to the processor’s local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 28-8. AATR Field Descriptions Description Debug Module command. WDMREG Access: Supervisor write-only...
Page 508: Trigger Definition Register (Tdr)
Reserved Reserved NOTE TT=11 (acknowledge/CPU space transfers) CPU space access Interrupt ack level 1 Interrupt ack level 2 Interrupt ack level 3 Interrupt ack level 4 Interrupt ack level 5 Interrupt ack level 6 Interrupt ack level 7 Freescale Semiconductor...
Page 509 DBR contents. 0 No inversion 1 Invert data breakpoint comparators. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Second Level Trigger L2ED First Level Trigger L1ED Figure 28-6.
Page 510 Address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR. Address breakpoint low. The breakpoint is based on the address in the ABLR. (PBR0 & PBMR) | PBR1 | PBR2 | PBR3 Eqn. 28-1 Freescale Semiconductor...
Page 511: Program Counter Breakpoint/Mask Registers (Pbr0–3, Pbmr)
(PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Description Data longword.
Page 512 Address Figure 28-7. PC Breakpoint Register (PBR0) Table 28-10. PBR0 Field Descriptions Description Address Table 28-11. PBRn Field Descriptions Description command. PBMR only masks PBR0. Section 28.5.3.3, “Command Access: Supervisor write-only BDM write-only Access: Supervisor write-only BDM write-only Freescale Semiconductor...
Page 513: Address Breakpoint Registers (Ablr, Abhr)
Field 31–0 High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range. Address MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Mask Table 28-12. PBMR Field Descriptions Description Address Table 28-13. ABLR Field Description Description Table 28-14.
Page 514: Data Breakpoint And Mask Registers (Dbr, Dbmr)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-18 Data Table 28-15. DBR Field Descriptions Description Mask Table 28-16. DBMR Field Descriptions Description Table 28-17 Access: Supervisor write-only BDM write-only Access: Supervisor write-only BDM write-only shows relationships between processor Freescale Semiconductor...
Page 515: Background Debug Mode (Bdm)
BKPT. This type of halt is always first marked as pending in the pocessor, which samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Access Size Operand Location Byte...
Page 516: Bdm Serial Interface
DSI is sampled and DSO is driven. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-20 command into the debug module. Execution continues at the Table 28-2. The development system serves as the serial communication command depends on the set of Freescale Semiconductor...
Page 517: Receive Packet Format
Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 28.5.2.1 Receive Packet Format The basic receive packet consists of 16 data bits and 1 status bit MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Current Current State Past NOTE Data Figure 28-14.
Page 518: Bdm Command Set
Data Message xxxx Valid data transfer FFFF Status OK 0000 Not ready with response; come again 0001 Error–Terminated bus cycle; data invalid FFFF Illegal Command Data Figure 28-15. Transmit BDM Packet Description Table 28-22 for register address encodings. Freescale Semiconductor...
Page 519 Freescale reserves unassigned command opcodes. All unused command formats within any revision level perform a and return the illegal command response. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 28-20. BDM Command Summary Description to dump large blocks of memory. An...
Page 520: Coldfire Bdm Command Format
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-24 Op Size Extension Word(s) Figure 28-16. BDM Command Format Table 28-21. BDM Field Descriptions Description Table 28-20. Operand Size Byte Word Longword Reserved Register Bit Values 8 bits 16 bits 32 bits — Table 28-22. Freescale Semiconductor...
Page 521: Command Sequence Diagrams
At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 28-17 shows serial bus traffic for commands. Each bubble...
Page 522: Command Set Descriptions
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-26 Table NOTE Interface,” describes the receive packet RAREG RDREG D[31:16] D[15:0] Command Format RAREG RDREG MS RESULT BERR Command Sequence RAREG RDREG 28-20. Register NEXT CMD LS RESULT NEXT CMD ’NOT READY’ Freescale Semiconductor...
Page 523 Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor WAREG WDREG D[31:16]...
Page 524 ’NOT READY’ LOCATION READ LS ADDR MEMORY ’NOT READY’ LOCATION Figure 28-23. Command Sequence READ D[7:0] ’NOT READY’ NEXT CMD RESULT NEXT CMD BERR ’NOT READY’ ’NOT READY’ NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Freescale Semiconductor...
Page 525 Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command Formats: Byte Word Longword MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor WRITE A[31:16] A[15:0] A[31:16] A[15:0] D[15:0]...
Page 526 ’NOT READY’ LOCATION NEXT CMD ’CMD COMPLETE’ BERR NEXT CMD ’NOT READY’ WRITE MEMORY ’NOT READY’ LOCATION NEXT CMD ’CMD COMPLETE’ BERR NEXT CMD ’NOT READY’ is executed to READ is not executed READ command retrieves subsequent DUMP Freescale Semiconductor...
Page 527 DUMP (B/W) ’ILLEGAL’ DUMP (LONG) ’ILLEGAL’ Operand Data: None MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE , or another command. Otherwise, an illegal READ DUMP can be used for intercommand padding command is processed, allowing the operand size to be...
Page 528 FILL NOTE FILL command is processed, allowing the operand size to be altered FILL D[15:0] D[31:16] D[15:0] Figure 28-28. Command Format FILL WRITE command FILL is a valid FILL , or a command. WRITE command can D[7:0] Freescale Semiconductor...
Page 529: Resume Execution
BDM command while the processor is halted, the updated value is used when prefetching resumes. If a command issues and the CPU is not halted, the command is ignored. Command Sequence: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor WRITE LS DATA MEMORY ’NOT READY’...
Page 530 HALT READ RESUME Command Formats: MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-34 Figure 28-32. Command Format NEXT CMD ’CMD COMPLETE’ Figure 28-33. Command Sequence command is pending. SYNC Freescale Semiconductor...
Page 531 The 12-bit Rc field is the same the processor’s MOVEC instruction uses. Command/Result Formats: Command Result Figure 28-36. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 28-34. Command Format SYNC SYNC_PC NEXT CMD CMD COMPLETE Figure 28-35.
Page 532 MAC Mask Register (MASK) MAC Accumulator (ACC) Status Register (SR) Program Register (PC) Flash Base Address Register (FLASHBAR) RAM Base Address Register (RAMBAR) ’NOT READY’ NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD BERR ’NOT READY’ Freescale Semiconductor...
Page 533 Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor WCREG D[31:16] D[15:0]...
Page 534 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-38 RDMREG D[31:16] D[15:0] Command/Result Formats RDMREG Mnemonic Reserved — RDMREG MS RESULT ’ILLEGAL’ Figure 28-41. Command Sequence RDMREG WDMREG Initial State Page 0x0090_0000 p. 28-7 — — NEXT CMD LS RESULT NEXT CMD ’NOT READY’ Freescale Semiconductor...
Page 535: Real-Time Debug Support
As shown in triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor BDM Command Format WDMREG D[31:16]...
Page 536 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-40 CSR[BSTAT] Breakpoint Status 0000 No breakpoints enabled 0001 Waiting for level-1 breakpoint 0010 Level-1 breakpoint triggered 0101 Waiting for level-2 breakpoint 0110 Level-2 breakpoint triggered Freescale Semiconductor...
Page 537: Concurrent Bdm And Processor Operation
After the debug module bus cycle, the processor reclaims the bus. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Section 28.5.1, “CPU Halt”. Debug Module...
Page 538: Processor Status, Debug Data Definition
In this definition, the y suffix generally denotes the source, and x denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The DD nomenclature refers to the DDATA outputs. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-42 NOTE NOTE Freescale Semiconductor...
Page 539 <ea>y,Dx divu.l <ea>y,Dx MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PST/DDATA PST = 0x1, {PST = 0xB, DD = source operand} PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} PST = 0x1, {PST = 0xB, DD = source operand}...
Page 540 PST = 0x1, {PST = 0xB, DD = source operand} PST = 0x1, {PST = 0x9, DD = source operand} PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1, {PST = 0xB, DD = source operand} Freescale Semiconductor...
Page 541 <ea>y wddata.w <ea>y MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PST/DDATA PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} PST = 0x1 PST = 0x1, {PST = 0xB, DD = destination operand}...
Page 542 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1 PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} Freescale Semiconductor...
Page 543: Freescale-Recommended Bdm Pinout
Freescale-Recommended BDM Pinout The ColdFire BDM connector is a 26-pin Berg connector arranged 2 x 13 as shown below. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PST = 0x1 PST = 0x1, {PST = 0xB, DD = source},...
Page 544 DDATA0 Freescale reserved IVDD Pins reserved for BDM developer use. Supplied by target Figure 28-44. Recommended BDM Connector MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 28-48 BKPT DSCLK Developer reserved PST3 PST1 DDATA3 DDATA1 Freescale reserved PSTCLK Freescale Semiconductor...
Page 545: Introduction
4-bit TAP Instruction Register JTAG_EN TCLK TMS/BKPT TRST/DSCLK JTAG Module MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor TAP Controller 1-bit Bypass Register 32-bit IDCODE Register 3-bit TEST_CTRL Register Disable DSCLK Force BKPT = 1 to Debug Module Figure 29-1.
Page 546: External Signal Description
JTAG Test reset input / BDM Development serial clock Table 29-2 summarizes the pin function selected depending on Section 28.5, “Background Table 29-1. Reset State Pull up — — — Active — Active — Active — Active Hi-Z / 0 — Freescale Semiconductor...
Page 547: Test Data Input/Development Serial Input (Tdi/Dsi)
(lsb) first. The TDI pin has an internal pull-up resistor. The DSI pin provides data input for the debug module serial communication port. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 29-2. Pin Function Selected JTAG_EN = 0...
Page 548: Memory Map/Register Definition
The IDCODE is a read-only register; its value is chip dependent. For more information, see Section 29.4.3.1, “IDCODE Instruction”. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 29-4 Access: User read/write Instruction Code Reset Figure 29-2. 4-Bit Instruction Register (IR) for a list of possible instruction codes. Freescale Semiconductor...
Page 549: Jtag_Cfm_Clkdiv Register
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor See note Figure 29-3. IDCODE Register Table 29-4.
Page 550: Functional Description
TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 29-6 Freescale Semiconductor...
Page 551: Jtag Instructions
JTAG Instructions Table 29-5 describes public and private instructions. Instruction IR[3:0] EXTEST IDCODE SAMPLE/PRELOAD ENABLE_TEST_CTRL MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR Table 29-5. JTAG Instructions Instruction Summary 0000...
Page 552: Idcode Instruction
Selects bypass register while tri-stating all output pins and asserting functional reset 1100 Selects bypass while applying fixed values to output pins and asserting functional reset 1111 Selects bypass register for data operations Decoded to select bypass register NOTE Freescale Semiconductor...
Page 553 CLAMP enhances test efficiency by reducing the overall shift path MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor IEEE 1149.1 Test Access Port (JTAG) 29-9...
Page 554: Restrictions
However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 29-10 or left unconnected. Freescale Semiconductor...
Page 555: Appendix A Register Memory Map Quick Reference
CPU @ 0x806 CPU @ 0x80E CPU @ 0x80F CPU @ 0xC04 CPU @ 0xC05 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Other Stack Pointer Vector Base Register MAC Status Register MAC Mask Register MAC Accumulator...
Page 556 64 bytes 196 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 64 bytes 1792 bytes 256 bytes 256 bytes 256 bytes 256 bytes 1M-6K Freescale Semiconductor...
Page 557 IPSBAR + 0x0028 IPSBAR + 0x0029 IPSBAR + 0x002A IPSBAR + 0x002B IPSBAR + 0x002C IPSBAR + 0x0030 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Module Reserved General Purpose Timer USB-OTG CFM (Flash) Control Registers Reserved CFM (Flash) Memory for IPS Reads and Writes Table A-3.
Page 558 Size (bits) GPACR1 SAR0 DAR0 BCR0 / DSR0 DCR0 SAR1 DAR1 BCR1 / DSR1 DCR1 SAR2 DAR2 BCR2 / DSR2 DCR2 SAR3 DAR3 BCR3 / DSR3 DCR3 UMR10, UMR20 USR0 UCSR0 UCR0 URB0 UTB0 UIPCR0 UACR0 UISR0 UIMR0 UBG10 Freescale Semiconductor...
Page 559 (Write) UART Output Port Bit Reset Command Register 1 IPSBAR + 0x0280 IPSBAR + 0x0284 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name (Read) Reserved UART Baud Rate Generator Register 20 (Read) UART Input Port Register 0...
Page 560 QSPI Mode Register QSPI Delay Register QSPI Wrap Register QSPI Interrupt Register QSPI Address Register QSPI Data Register Mnemonic Size (bits) UCR2 URB2 UTB2 UIPCR2 UACR2 UISR2 UIMR2 UBG12 UBG22 UIP2 UOP12 UIP02 I2ADR0 I2FDR0 I2CR0 I2SR0 I2DR0 QDLYR Freescale Semiconductor...
Page 561 IPSBAR + 0x0442 IPSBAR + 0x0443 IPSBAR + 0x0444 IPSBAR + 0x0448 IPSBAR + 0x044C MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name C1 Registers C Address Register 1 C Frequency Divider Register 1 C Control Register 1...
Page 562 Interrupt Control Register 0-11 Mnemonic Size (bits) DTMR2 DTXMR2 DTER2 DTRR2 DTCR2 DTCN2 DTMR3 DTXMR3 DTER3 DTRR3 DTCR3 DTCN3 IPRH0 IPRL0 IMRH0 IMRL0 INTFRCH0 INTFRCL0 IRLR0 IACKLPR0 ICR001 ICR002 ICR003 ICR004 ICR005 ICR006 ICR007 ICR008 ICR009 ICR010 ICR011 Freescale Semiconductor...
Page 563 IPSBAR + 0x0C68 IPSBAR + 0x0C69 IPSBAR + 0x0C6A IPSBAR + 0x0C6B IPSBAR + 0x0C6C MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Interrupt Control Register 0-12 Interrupt Control Register 0-13 Interrupt Control Register 0-14 Interrupt Control Register 0-15...
Page 564 Global Level 6 Interrupt Acknowledge Register Mnemonic Size (bits) ICR045 ICR046 ICR047 ICR048 ICR049 ICR050 ICR051 ICR052 ICR053 ICR054 ICR055 ICR056 ICR057 ICR058 ICR059 ICR060 ICR061 ICR062 ICR063 SWACK0 L1IACK0 L2IACK0 L3IACK0 L4IACK0 L5IACK0 L6IACK0 L7IACK0 GL1IACK GL2IACK GL3IACK GL4IACK GL5IACK GL6IACK Freescale Semiconductor...
Page 565 IPSBAR + 0x10_0018 IPSBAR + 0x10_0019 IPSBAR + 0x10_001A IPSBAR + 0x10_001B IPSBAR + 0x10_001C IPSBAR + 0x10_001D MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Global Level 6 Interrupt Acknowledge Register GPIO Registers Reserved Reserved Reserved...
Page 566 Port AS Pin Data/Set Data Register Mnemonic Size (bits) — — DDRNQ — DDRAN DDRAS DDRQS — DDRTA DDRTC DDRTD DDRUA DDRUB DDRUC DDRDD — — — — — — — — — — — PORTNQP/ SETNQ — PORTANP/ SETAN PORTASP/ SETAS Freescale Semiconductor...
Page 567 IPSBAR + 0x10_0054 IPSBAR + 0x10_0055 IPSBAR + 0x10_0056 IPSBAR + 0x10_0057 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Port QS Pin Data/Set Data Register Reserved Port TA Pin Data/Set Data Register Port TC Pin Data/Set Data Register...
Page 568 Pin Drive Strength Register Mnemonic Size (bits) CLRTD CLRUA CLRUB CLRUC CLRDD — — — — — — — — — — — PNQPAR PANPAR PASPAR PQSPAR PTAPAR PTCPAR PTDPAR PUAPAR PUBPAR PUCPAR PDDPAR — — — PSRR PDSR Freescale Semiconductor...
Page 569 IPSBAR + 0x13_0006 IPSBAR + 0x14_0000 IPSBAR + 0x14_0002 IPSBAR + 0x14_0004 IPSBAR + 0x14_0006 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Reset Control Register Reset Status Register Chip Configuration Register Low-Power Control Register Reset Configuration Register...
Page 570 GPT System Control Register 1 GPT Toggle-on-Overflow Register Mnemonic Size (bits) PCSR0 PMR0 PCNTR0 PCSR1 PMR1 PCNTR1 CTRL1 CTRL2 ADZCC ADLST1 ADLST2 ADSDIS ADSTAT ADLSTAT ADZCSTAT ADRSLT0-7 ADLLMT0-7 ADHLMT0-7 ADOFS0-7 POWER GPTIOS GPTCFORC GPTOC3M GPTOC3D GPTCNT GPTSCR1 GPTTOV Freescale Semiconductor...
Page 571 IPSBAR + 0x1B_0010 IPSBAR + 0x1B_0011 IPSBAR + 0x1B_0012 IPSBAR + 0x1B_0013 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name GPT Control Register 1 GPT Control Register 2 GPT Interrupt Enable Register GPT System Control Register 2...
Page 572 Error Interrupt Enable Register Status Register Control Register Mnemonic Size (bits) PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN PER_ID ID_COMP ADD_INFO OTG_INT_STAT OTG_INT_EN OTG_STATUS OTG_CTRL INT_STAT INT_ENB ERR_STAT ERR_ENG STAT Freescale Semiconductor...
Page 573 IPSBAR + 0x1C_0104 IPSBAR + 0x1C_0108 IPSBAR + 0x1C_010C IPSBAR + 0x1D_0000 IPSBAR + 0x1D_0002 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Name Address Register BDT Page Register 1 Frame Number Register Low Frame Number Register High...
Page 574 MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 A-20 Name CFM Security Register CFM Protection Register CFM Supervisor Access Register CFM Data Access Register CFM User Status Register CFM Command Register CFM Clock Select Register Mnemonic Size (bits) CFMSEC CFMPROT CFMSACC CFMDACC CFMUSTAT CFMCMD CFMCLKSEL Freescale Semiconductor...
Page 575: B.1 Changes Between Rev. 1 And Rev. 2
Changed the description for SEL_VREFH=0 and SEL_VREFL=0 (were “Internal VRx”, are “VRH” and “VRL”, respectively). Section 28.4 / Page 28-6 Clarified the last sentence of the first paragraph regarding quiscent DSCLK during WDEBUG. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description...
Page 576: B.2 Changes Between Rev. 0 And Rev. 1
• Corrected the acronym for the SOF threshold register (was OSOF_THLDL, is SOF_THLD). • Deleted the entry for the (nonexistent) GSWIACK register. • Added entries for the RTCGOCU and RTCGOCL registers. MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2 Description Freescale Semiconductor...

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Coldfire mcf52212 Coldfire mcf52211 Coldfire mcf52213

Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

Signal Descriptions

Chapter 1 Overview

Chapter 7 Backup Watchdog Timer

Chapter 2 Signal Descriptions

Chapter 3 Coldfire Core

Chapter 4

Chapter 5 Static RAM (SRAM)

Chapter 21

Chapter 6 Clock Module

Chapter 8 Power Management

Chapter 9 Chip Configuration Module (CCM)

Chapter 10 Reset Controller Module

Chapter 11 Real-Time Clock

Chapter 12 System Control Module (SCM)

Chapter 13 General Purpose I/O Module

Chapter 14 Interrupt Controller Theory of Operation

Chapter 15

15.4.1.5 Otg Interrupt Status Register (Otg_Int_Stat)

Chapter 16 Edge Port Module (EPORT)

Chapter 17 DMA Controller Module

Chapter 19 Detailed Signal Descriptions

Chapter 20

Chapter 22 DMA Timers (DTIM0-DTIM3)

Chapter 18

Chapter 23 Queued Serial Peripheral Interface (QSPI)

Chapter 24 UART Modules

Chapter 25 I 2 C Interface

Chapter 26 Analog-To-Digital Converter (ADC)

Chapter 27 Pulse-Width Modulation (PWM) Module

Chapter 28 Debug Module

Chapter 29 IEEE 1149.1 Test Access Port (JTAG)

Appendix A Register Memory Map Quick Reference

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Chapters

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