Freescale Semiconductor MCF54455 Reference Manual page 113

Memory Management Unit (MMU)
4.3.1.2.2 MMU Access
The MMU TLB control registers are memory-mapped. The TLB entries are read and written indirectly
through MMU control registers. Memory space for these resources is defined by a new supervisor program
model register, the MMU base-address register (MMUBAR). This defines a supervisor-mode, data-only
space. It has the highest priority for the data-processor local-bus address-mode determination.
4.3.1.2.3 Virtual Mode
Every processor local-bus instruction and data reference is a virtual or physical address mode access. The
following are always physical accesses:
• All addresses for special mode (interrupt acknowledges, emulator mode operations, etc.) accesses
• All addresses if the MMU is not enabled
If the MMU is enabled, the address mode for normal accesses is determined by the MMUBAR,
RAMBARs, and ACRs in the priority order listed:
• Addresses that hit in these registers are treated as physical references. These addresses are not
translated and their address attributes are sourced from the highest priority mapping register they
hit.
• If an address hits none of these mapping registers, it is a virtual address and is sent to the MMU. If
the MMU is enabled, the default CACR information is not used.
4.3.1.2.4 Virtual Memory References
The ColdFire MMU architecture references the MMU for all virtual mode accesses to the processor local
bus. MMU, SRAM and ACR memory spaces are treated as physical address spaces and all permissions
applying to these spaces are contained in the respective mapping register. The virtual mode access either
hits or misses in the TLB of the MMU. A TLB miss generates an access fault in the processor, allowing
software to either load the appropriate translation into the TLB and restart the faulting instruction or abort
the process. Each TLB hit checks permissions based on the access control information in the referenced
TLB entry.
4.3.1.2.5 Instruction and Data Cache Addresses
For a given page size, virtual address bits that reference within a page are called the in-page address. All
bits above this are the virtual page number. Likewise, the physical address has a physical page number and
in-page address bits. Virtual and physical in-page address bits are the same; the MMU translates the virtual
page number to the physical page number.
Instruction and data caches are accessed with the untranslated processor local-bus address. The translated
address is used for cache allocation. That is, caches are virtual-address accessed and physical-address
tagged. If instruction and data cache addresses are not larger than the in-page address for the smallest
active MMU page, the cache is physically accessed; if they are larger, the cache can have aliasing problems
between virtual and cache addresses. Software handles these problems by forcing the virtual address to be
equal to the physical address for those bits addressing the cache, but above the in-page address of the
smallest active page size. The number of these bits depends on cache and page sizes.
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