Reset Configuration Register (Rcon) - Freescale Semiconductor MCF54455 Reference Manual

Field
3 Oscillator clock mode.
OSCMODE 0 Crystal oscillator mode
1 Oscillator bypass mode
2–0 PLL clock mode. Reflects the chosen PLL clock mode as set by the reference clock multiplier used to generate
PLLMULT the VCO clock.
Note: The PLLMULT field value may not be valid following serial boot, because serial boot reset configuration can
select reference clock multipliers not shown in the above table.
The PLL output frequency can also be programmed after reset via the PLL output divider registers (PODR) and
PLL feedback divider register (PFDR). See
settings (values used to divide the VCO clock down to the system clocks) are shown in the below table.
11.3.2

Reset Configuration Register (RCON)

At reset, the RCON register determines the default operation of certain chip functions. All default
functions defined by the RCON values can be overridden only during reset configuration (see
Section 11.4.1, "Reset Configuration") if the external BOOTMOD[1:0] pins are driven to 10 or 11. RCON
is a read-only register and contains the same fields as the CCR register.
Two versions of the RCON are available, depending on package type. These versions are shown in
Figure 11-4 and Figure 11-5. Only two versions are available, unlike three versions for the CCR, because
there are only two sets of default values. Those default values make one of the three CCR versions (360-pin
PCI-disabled) unavailable as a default configuration.
Freescale Semiconductor
Table 11-5. CCR Field Descriptions 256-pin (continued)
PLLMULT VCO
20  REF
000
10  REF
001
24  REF
010
18  REF
011
Chapter 8, "Clock Module,"
Clock
CPU
System bus
FlexBus (FB_CLK)
USB clock
Description
PLLMULT
12  REF
100
6  REF
101
16  REF
110
8  REF
111
for more details. The default output divider
OUTDIV
PLL clock
Value
OUTDIV1 2
OUTDIV2 4
OUTDIV3 8
OUTDIV5 8
Chip Configuration Module (CCM)
VCO
PODR
1
3
7
7
11-7