Freescale Semiconductor MCF54455 Reference Manual page 529

PCI Bus Controller
Address: 0xFC0A_8024 (PCIBAR5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREF RANGE IO/M#
BAR5
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
1
See Figures Base address register n. Applies only when the PCI controller is target. These bits are programmable.
BAR0
1
See Figures Reserved, must be cleared.
3 Prefetchable access. Indicates if memory space defined by BAR0 is prefetchable. For PCIBAR0 this value is fixed
PREF to 0, while the other PCIBAR registers are fixed to 1.
0 Un-prefetchable
1 Prefetchable
2–1 Fixed to 00. Indicates the base address is 32 bits wide and can be mapped anywhere in 32-bit address space.
RANGE Configuration software should write 00 to these bit locations.
0 IO or memory space. Fixed to 0. Indicates that the base address is for memory space. Configuration software
IO/M# should write a 0 to this bit location.
0 Memory
1 I/O
1
See corresponding PCIBARn figure above for bit numbers for the BARn and reserved bit fields.
22.3.1.6 CardBus CIS Pointer Register (PCICCPR)—PCI Dword A
This optional register contains the pointer to the card information structure (CIS) for the CardBus card. All
32 bits of the register are programmable by the slave bus. This register can only be read from the PCI bus,
not written.
22-12
Figure 22-11. PCIBAR5 Register
Table 22-7. PCIBARn Field Descriptions
Description
Bit Field
BATn
Width
BAT0 14
BAT1 12
BAT2 10
BAT3
BAT4
BAT5
9 8 7 6
Boundary Size
256 Kbye
1 Mbyte
4 Mbyte
8 16 Mbyte
5 128 Mbyte
3 512 Mbyte
Access: User read/write
5 4 3 2 1 0
1 0 0 0
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