Uart Module Initialization Sequence - Freescale Semiconductor MCF54455 Reference Manual

UART Modules
should be configured to use RXRDY directly (and not FFULL) to remove any complications related to
retrieving the final characters from the FIFO buffer.
The implementation described in this section allows independent DMA processing of transmit and receive
data while continuing to support interrupt notification to the processor for CTS change-of-state and delta
break error managing.
Table 32-14 shows the DMA requests.
Register
UISRn
UISRn
32.5.2

UART Module Initialization Sequence

The following shows the UART module initialization sequence.
1. UCRn:
a) Reset the receiver and transmitter.
b) Reset the mode pointer (MISC[2–0] = 0b001).
2. UIMRn: Enable the desired interrupt sources.
3. UACRn: Initialize the input enable control (IEC bit).
4. UCSRn: Select the receiver and transmitter clock. Use timer as source if required.
5. UMR1n:
a) If preferred, program operation of receiver ready-to-send (RXRTS bit).
a) Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit).
b) Select character or block error mode (ERR bit).
c) Select parity mode and type (PM and PT bits).
d) Select number of bits per character (B/Cx bits).
6. UMR2n:
a) Select the mode of operation (CM bits).
b) If preferred, program operation of transmitter ready-to-send (TXRTS).
c) If preferred, program operation of clear-to-send (TXCTS bit).
d) Select stop-bit length (SB bits).
7. UCRn: Enable transmitter and/or receiver.
32-27
Table 32-14. UART DMA Requests
Bit
1 Receive DMA request
0 Transmit DMA request
DMA Request
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