Interrupt Registers - Freescale Semiconductor MCF54455 Reference Manual

Address: 0x9000_0024 (ATA_CR)
7
R
FEN
W
Reset 0
Field
7 This field controls if the internal FIFO is in reset or enabled
FEN 0 FIFO reset
1 FIFO normal operation
6 Controls the level on the ATA_RESET pin, and controls the reset of the internal ATA protocol engine.
RESET 0 ATA_RESET = 0, ATA drive is reset, and internal protocol engine reset.
1 ATA_RESET = 1, ATA drive is not reset, and internal protocol engine normal operation.
5 FIFO transmit enable. Controls if the FIFO makes transmit data requests to the DMA. If enabled, the FIFO
FREFILL requests the DMA to refill it when FIFO filling drops below the alarm level.
0 FIFO refill by DMA disabled
1 FIFO refill by DMA enabled
4 FIFO receive enable. Controls if the FIFO makes receive data requests to the DMA. If enabled, the FIFO
FEMPTY requests the DMA to empty it whenr FIFO filling becomes greater or equal to the alarm level.
0 FIFO empty by DMA disabled
1 FIFO empty by DMA enabled
3 DMA pending bit. This bit controls if the ATA interface responds to a DMA request originating in the drive.
DMAPEND If this bit asserts, the ATA interface starts a multiword DMA or ultra DMA burst when the drive asserts
ATA_DMARQ.
0 ATA interface does not start DMA burst
1 ATA interface starts multiword DMA or ultra DMA burst when drive asserts ATA_DMARQ
2 DMA mode. If a DMA burst starts, the UDMA or MDMA protocol is used.
DMAMODE 0 Multiword DMA protocol is used
1 Ultra DMA protocol is used
1 DMA burst direction. Indicates the data direction on any DMA burst started.
DMADIR 0 DMA in burst, ATA interface reads from drive
1 DMA out burst, ATA interface writes to drive
0 IORDY enable. Indicates if the ATA_IORDY handshake is used during PIO mode.
IORDYEN 0 IORDY is disregarded
1 IORDY handshake is used
23.3.6

Interrupt Registers

A group of three registers controls the interrupt interface from the ATA module to the CPU's interrupt
controller and DMA controller.
• Interrupt request. Bits 3–6 of the interrupt registers control ATA interrupts. A request to the
interrupt controller generates if one of the four bits is set in the interrupt status register (ATA_ISR),
while the same bit is set in the interrupt enable register (ATA_IER).
Freescale Semiconductor
6 5
RESET FREFILL FEMPTY
0 0
Figure 23-6. ATA Control Register (ATA_CR)
Table 23-4. ATA_CR Field Descriptions
Advanced Technology Attachment (ATA)
4 3 2
DMAPEND DMAMODE
0 0 0
Description
Access: User read/write
1 0
DMADIR IORDYEN
0 0
23-9