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The PIO mode is a slow protocol, mainly intended to program the ATA disc drive, but also possible
to transfer data to/from the disc drive. During PIO mode, the FIFO is not active.
•
DMA Mode
In DMA mode, data transfers between the ATA bus and the FIFO. Two different DMA protocols
are supported on the ATA bus: ultra DMA mode and multiword DMA mode. Acontrol register bit
selects which DMA mode.
A DMA transfer starts when DMA mode transfer is enabled by writing some control bit and when
the drive connected to the ATA bus pulls its DMARQ signal high.
During an ATA bus DMA transfer, data transfers between the ATA bus and the FIFO. The transfer
pauses to avoid FIFO overflow and FIFO underflow.
The host CPU or the host smart DMA unit must read data or write data to the FIFO to keep the
transfer going. Normally, the host (smart) DMA unit takes on this task. For this purpose, the FIFO
receive/transmit alarms are sent to the host DMA unit. The FIFO receive alarm informs the host
DMA unit of at least one packet of data waiting in the FIFO to be read by the host DMA. When
this alarm is asserted, the host DMA should transfer one packet of data from FIFO to the main
memory. Typical packet size is 32 bytes (8 longwords), but other packet sizes can be managed too.
FIFO transmit alarm informs the host DMA unit of space for at least one packet to be written by
the host DMA. When this alarm is asserted, the host DMA must transfer one packet of data from
main memory to the FIFO. Typical packet size is 32 bytes (8 longwords), but other packet sizes
can be managed too.
23.2
External Signal Description
See
Table 23-1
for the list of signals entering and exiting this module to peripherals within the device.
Name
ATA_RESET
ATA_DIOR
ATA_DIOW
ATA_CS[1:0]
ATA_DA[2:0]
ATA_DMARQ
ATA_DMACK
ATA_INTRQ
ATA_IORDY
ATA_DATA[15:0]
1
This signal is a standard ATA bus signal. It conforms with the ATA specification.
Freescale Semiconductor
Table 23-1. ATA Signal Properties
Function
1
ATA bus reset signal
ATA bus read strobe
ATA bus write strobe
ATA bus chip selects
ATA bus address line
ATA bus DMA request
ATA bus DMA acknowledge
ATA bus interrupt request
ATA bus I/O channel ready
ATA data bus (little-endian)
Advanced Technology Attachment (ATA)
Reset State
I/O
0
O
1
O
1
O
1
O
0
O
—
I/O
1
O
—
I/O
—
O
Hi-Z
Tri-state I/O
23-3
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