Freescale Semiconductor MCF54455 Reference Manual page 889

Debug Module
Additionally, writes to the accumulator extension registers must be performed after the corresponding
accumulators are updated because a write to any accumulator alters the corresponding extension register
contents.
For more information on saving and restoring the complete EMAC programming model, see
Section 5.3.1.2, "Saving and Restoring the EMAC Programming Model."
34.4.1.5.14 Write Control Register (
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7
stack pointers and the EMAC programming model.
Command/Result Formats:
15 14
Command
Result
Command Sequence:
WCREG MS ADDR
??? 'NOT READY'
Operand Data: This instruction requires two longword operands. The first selects the register to
the operand data writes to; the second contains the data.
Result Data: Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
34-47
WCREG
13 12 11 10
0x2 0x8
0x0 0x0
0x0
Figure 34-43.
WCREG
MS ADDR
'NOT READY'
Figure 34-44.
WCREG
)
9 8 7 6 5
0x8
0x0
Rc
D[31:16]
D[15:0]
Command/Result Formats
MS DATA
'NOT READY'
WRITE
LS DATA
CONTROL
'NOT READY'
REGISTER
Command Sequence
4 3 2 1 0
0x0
0x0
XXX
'NOT READY'
NEXT CMD
'CMD COMPLETE'
XXX
BERR
NEXT CMD
'NOT READY'
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