Table of Contents
Advertisement
Clock Module
8.1.3
Modes of Operation
The PLL operational mode must be configured during reset. The reset configuration pins must be driven
to the appropriate state for the desired mode from the time RSTOUT asserts until it negates. Refer to
Chapter 11, "Chip Configuration Module (CCM)."
The clock module can operate in normal PLL mode with crystal reference, normal PLL mode with external
reference, and input-clock limp mode.
8.1.3.1
Normal PLL Mode with Crystal Reference
In normal mode with a crystal reference, the PLL receives an input clock frequency from the crystal
oscillator circuit and multiplies the frequency to create the PLL output clock. It can synthesize frequencies
ranging from 4 – 34x the input frequency. The user must supply a crystal oscillator within the appropriate
input frequency range, the crystal manufacturer's recommended external support circuitry, and short signal
route from the device to the crystal.
8.1.3.2
Normal PLL Mode with External Reference
This second mode is the same as
EXTAL is driven by an external clock generator rather than a crystal oscillator. However, the input
frequency range is the same as the crystal reference. To enter normal mode with external clock generator
reference, the PLL configuration must be set at reset by overriding the default reset configuration. See
Chapter 11, "Chip Configuration Module (CCM),"
(oscillator bypass mode).
8.1.3.3
Input Clock (Limp) Mode
Through parallel RCON, serial boot, or the MISCCR[LIMP] bit, the device may be placed into a
low-frequency limp mode, in which the PLL is bypassed and the device runs from a factor of the input
clock (EXTAL). In this mode, EXTAL feeds a 5-bit programmable counter that divides the input clock by
n
2
, where n is the value of the programmable counter field, MISCCR[LPDIV]. For more information on
programming the divider, see
be changed without glitches or otherwise negative affects to the system.
While in this mode, the PLL is placed in bypass mode to reduce overall system power consumption. A 2:1
ratio is maintained between the core and the primary bus clock, while a 1:1 ratio is maintained between
FB_CLK and the internal bus clock (normally a 1:2 ratio). Because they do not function at speeds as low
as the minimum input-clock frequency, the SDRAM controller, FECs, ATA controller, and PCI controller
are not functional in limp mode. The USB controller is effectively disabled as well. However, it is able to
capture a wake-up event to release the processor from limp mode.
When switching from limp mode to normal functional mode, you must ensure that any peripheral
transactions in progress (Ethernet frame reception/transmission) are allowed to complete to avoid data loss
or corruption.
8-4
Section 8.1.3.1, "Normal PLL Mode with Crystal Reference,"
for details on setting the device for external reference
Chapter 9, "Power Management."
The programmed value of the divider may
Freescale Semiconductor
except
Advertisement
Table of Contents
