Address Attribute Trigger Registers (Aatr, Aatr1) - Freescale Semiconductor MCF54455 Reference Manual

external development system. To maintain compatibility with revision A, BAAR is loaded any time the
AATR is written. The BAAR is initialized to a value of 0x05, setting supervisor data as the default address
space.
DRc[4:0]: 0x05 (BAAR)
7
R
W R
Reset: 0
Field
7 Read/Write.
R 0 Write
1 Read
6–5 Size.
SZ 00 Longword
01 Byte
10 Word
11 Reserved
4–3 Transfer Type. See the TT definition in the AATR description,
TT (AATR, AATR1)".
2–0 Transfer Modifier. See the TM definition in the AATR description,
TM Registers (AATR,
34.3.4

Address Attribute Trigger Registers (AATR, AATR1)

The AATR and AATR1 define address attributes and a mask to be matched in the trigger. The register value
is compared with address attribute signals from the processor's local high-speed bus, as defined by the
setting of the trigger definition register (TDR) for AATR and the extended trigger definition register
(XTDR) for AATR1. AATRn is accessible in supervisor mode as debug control register 0x06 using the
WDEBUG instruction and through the BDM port using the
This register is expanded to include an optional ASID specification and a control bit that enables the use
of the ASID field.
Freescale Semiconductor
6 5
SZ
0 0
Figure 34-4. BDM Address Attribute Register (BAAR)
Table 34-8. BAAR Field Descriptions
AATR1)".
4 3 2
TT
0 0 1
Description
Section 34.3.4, "Address Attribute Trigger Registers
Section 34.3.4, "Address Attribute Trigger
command.
WDMREG
Debug Module
Access: Supervisor write-only
BDM write-only
1 0
TM
0 1
34-12