Freescale Semiconductor MCF54455 Reference Manual page 857

Debug Module
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WDMREG command.
DRc[4:0]: 0x07 (TDR)
31 30 29
R
W TRC L2EBL
Reset 0 0 0
15 14 13
R
W 0 0 L1EBL
Reset 0 0 0
Field
31–30 Trigger Response Control. Determines how the processor responds to a completed trigger condition. The trigger
TRC response is always displayed on PSTDDATA.
00 Display on PSTDDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29 Enable Level 2 Breakpoint. Global enable for the breakpoint trigger.
L2EBL 0 Disables all level 2 breakpoints
1 Enables all level 2 breakpoint triggers
28–22 Enable Level 2 Data Breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on
L2ED the size and placement on the processor's local data bus. Clearing all ED bits disables data breakpoints.
34-15
28 27 26 25
L2ED
0 0 0 0
12 11 10 9
L1ED
0 0 0 0
Figure 34-6. Trigger Definition Register (TDR)
Table 34-10. TDR Field Descriptions
TDR Bit
28 Data longword. Entire processor's local data bus.
27 Lower data word.
26 Upper data word.
25 Lower lower data byte. Low-order byte of the low-order word.
24 Lower middle data byte. High-order byte of the low-order word.
23 Upper middle data byte. Low-order byte of the high-order word.
22 Upper upper data byte. High-order byte of the high-order word.
Second Level Trigger
24 23 22 21
L2DI
0 0 0 0
First Level Trigger
8 7 6 5
L1DI
0 0 0 0
Description
Description
Access: Supervisor write-only
BDM write-only
20 19 18 17
L2EA L2EPC L2PCI
0 0 0 0
4 3 2 1
L1EA L1EPC L1PCI
0 0 0 0
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