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Signal Name
FEC_RXD1
X
—
X
FEC_RXD[3:2]
X
—
— These pins contain the Ethernet input data transferred from PHY to the media access controller
FEC_RXER
X
—
X
FEC_TXCLK
X
X
X
FEC_TXD0
X
X
X
FEC_TXD1
X
—
X
FEC_TXD[3:2]
X
—
— These pins contain the serial output Ethernet data and valid only during assertion of
FEC_TXEN
X
X
X
FEC_TXER
X
—
— When asserted for one or more clock cycles while FEC_TXEN is also asserted, PHY sends one
26.4
Memory Map/Register Definition
The FECs are programmed by a combination of control/status registers (CSRs) and buffer descriptors. The
CSRs control operation modes and extract global status information. The descriptors pass data buffers and
related buffer information between the hardware and software.
Each FEC implementation requires a 1-Kbyte memory map space, which is divided into two sections of
512 bytes each for:
•
Control/status registers
•
Event/statistic counters held in the MIB block
Table 26-2
defines the top level memory map.
0xFC03_0000 – FC03_01FF
0xFC03_0200 – FC03_02FF
0xFC03_4000 – FC03_41FF
0xFC03_4200 – FC03_42FF
Freescale Semiconductor
Table 26-1. FEC Signal Descriptions (continued)
This pin contains the Ethernet input data transferred from PHY to the media access controller
when FEC_RXDV is asserted.
when FEC_RXDV is asserted.
When asserted with FEC_RXDV, indicates PHY detects an error in the current frame. When
FEC_RXDV is not asserted, FEC_RXER has no effect.
Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER.
In RMII mode, this signal is the reference clock for receive, transmit, and the control interface.
The serial output Ethernet data and only valid during the assertion of FEC_TXEN.
This pin contains the serial output Ethernet data and valid only during assertion of FEC_TXEN.
FEC_TXEN.
Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble
of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.
or more illegal symbols. FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is negated.
Table 26-2. Module Memory Map
Address
Fast Ethernet Controllers (FEC0 and FEC1)
Description
Function
FEC0 Control/Status Registers
FEC0 MIB Block Counters
FEC1 Control/Status Registers
FEC1 MIB Block Counters
26-6
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