Freescale Semiconductor MCF54455 Reference Manual page 69

ColdFire Core
Instruction Fetch
Pipeline
IAG
Branch
Cache
IC2
Branch
Accel.
Operand Execution
Pipeline
DS
OAG
OC1
OC2
EX
DA
DSCLK DSI
The instruction fetch pipeline (IFP) is a four-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the five-stage operand execution pipeline (OEP), that decodes the
instruction, fetches the required operands, and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
3-3
IC1
IED
IB
secDS
Misalignment
Module
Debug
DSO PSTDDATA
Figure 3-1. V4 ColdFire Core Pipelines
Instruction
Memory
Data
(Operand)
Memory
DDATA
PSTCLK
Internal
Bus
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