Dspi Push Transmit Fifo Register (Dspi_Pushr) - Freescale Semiconductor MCF54455 Reference Manual

Field
28 DSPI finished request enable. Enables the DSPI_SR[EOQF] flag to generate an interrupt request.
EOQF_RE 0 EOQF interrupt requests are disabled
1 EOQF interrupt requests are enabled
27 Transmit FIFO underflow request enable. Enables the DSPI_SR[TFUF] flag to generate an interrupt request.
TFUF_RE 0 TFUF interrupt requests are disabled
1 TFUF interrupt requests are enabled
26 Reserved, must be cleared.
25 Transmit FIFO fill request enable. Enables the DSPI_SR[TFFF] flag to generate a request. The TFFF_DIRS bit
TFFF_RE selects between generating an interrupt request or a DMA requests.
0 TFFF interrupt or DMA requests are disabled
1 TFFF interrupt or DMA requests are enabled
24 Transmit FIFO fill DMA or interrupt request select. Selects between generating a DMA request or an interrupt
TFFF_DIRS request. When the DSPI_SR[TFFF] flag bit and the DSPI_RSER[TFFF_RE] bit are set, this bit selects between
generating an interrupt request or a DMA request.
0 TFFF flag generates interrupt requests
1 TFFF flag generates DMA requests
23–20 Reserved, must be cleared.
19 Receive FIFO overflow request enable. Enables the DSPI_SR[RFOF] flag to generate an interrupt request.
RFOF_RE 0 RFOF interrupt requests are disabled
1 RFOF interrupt requests are enabled
18 Reserved, must be cleared.
17 Receive FIFO drain request enable. Enables the DSPI_SR[RFDF] flag to generate a request. The RFDF_DIRS bit
RFDF_RE selects between generating an interrupt request or a DMA request.
0 RFDF interrupt or DMA requests are disabled
1 RFDF interrupt or DMA requests are enabled
16 Receive FIFO drain DMA or interrupt request select. Selects between generating a DMA request or an interrupt
RFDF_DIRS request. When the DSPI_SR[RFDF] flag bit and the DSPI_RSER[RFDF_RE] bit are set, the RFDF_DIRS bit selects
between generating an interrupt request or a DMA request.
0 RFDF flag generates interrupt requests
1 RFDF flag generates DMA requests
15–0 Reserved, must be cleared.
31.3.6

DSPI Push Transmit FIFO Register (DSPI_PUSHR)

The DSPI_PUSHR provides a means to write to the TX FIFO. SPI commands and data written to this
register is transferred to the TX FIFO. See
information. Write accesses of 8- or 16-bits to the DSPI_PUSHR transfer 32 bits to the TX FIFO.
Only the TXDATA field is used for DSPI slaves.
Freescale Semiconductor
Table 31-7. DSPI_RSER Field Descriptions (continued)
Section 31.4.2.4, "TX FIFO Buffering
NOTE
DMA Serial Peripheral Interface (DSPI)
Description
Mechanism," for more
31-17